drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controler.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <malloc.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <miiphy.h>
  17 #include <asm/errno.h>
  18 #include <asm/io.h>
  19
  20 #include "sh_eth.h"
  21
  22 #ifndef CONFIG_SH_ETHER_USE_PORT
  23 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  24 #endif
  25 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  26 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  27 #endif
  28
  29 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
  30 #define flush_cache_wback(addr, len)    \
  31                         flush_dcache_range((u32)addr, (u32)(addr + len - 1))
  32 #else
  33 #define flush_cache_wback(...)
  34 #endif
  35
  36 #define TIMEOUT_CNT 1000
  37
  38 int sh_eth_send(struct eth_device *dev, void *packet, int len)
  39 {
  40         struct sh_eth_dev *eth = dev->priv;
  41         int port = eth->port, ret = 0, timeout;
  42         struct sh_eth_info *port_info = &eth->port_info[port];
  43
  44         if (!packet || len > 0xffff) {
  45                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  46                 ret = -EINVAL;
  47                 goto err;
  48         }
  49
  50         /* packet must be a 4 byte boundary */
  51         if ((int)packet & 3) {
  52                 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
  53                 ret = -EFAULT;
  54                 goto err;
  55         }
  56
  57         /* Update tx descriptor */
  58         flush_cache_wback(packet, len);
  59         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  60         port_info->tx_desc_cur->td1 = len << 16;
  61         /* Must preserve the end of descriptor list indication */
  62         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  63                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  64         else
  65                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  66
  67         /* Restart the transmitter if disabled */
  68         if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
  69                 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
  70
  71         /* Wait until packet is transmitted */
  72         timeout = TIMEOUT_CNT;
  73         while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
  74                 udelay(100);
  75
  76         if (timeout < 0) {
  77                 printf(SHETHER_NAME ": transmit timeout\n");
  78                 ret = -ETIMEDOUT;
  79                 goto err;
  80         }
  81
  82         port_info->tx_desc_cur++;
  83         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
  84                 port_info->tx_desc_cur = port_info->tx_desc_base;
  85
  86 err:
  87         return ret;
  88 }
  89
  90 int sh_eth_recv(struct eth_device *dev)
  91 {
  92         struct sh_eth_dev *eth = dev->priv;
  93         int port = eth->port, len = 0;
  94         struct sh_eth_info *port_info = &eth->port_info[port];
  95         uchar *packet;
  96
  97         /* Check if the rx descriptor is ready */
  98         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
  99                 /* Check for errors */
 100                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 101                         len = port_info->rx_desc_cur->rd1 & 0xffff;
 102                         packet = (uchar *)
 103                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 104                         NetReceive(packet, len);
 105                 }
 106
 107                 /* Make current descriptor available again */
 108                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 109                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 110                 else
 111                         port_info->rx_desc_cur->rd0 = RD_RACT;
 112
 113                 /* Point to the next descriptor */
 114                 port_info->rx_desc_cur++;
 115                 if (port_info->rx_desc_cur >=
 116                     port_info->rx_desc_base + NUM_RX_DESC)
 117                         port_info->rx_desc_cur = port_info->rx_desc_base;
 118         }
 119
 120         /* Restart the receiver if disabled */
 121         if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
 122                 sh_eth_write(eth, EDRRR_R, EDRRR);
 123
 124         return len;
 125 }
 126
 127 static int sh_eth_reset(struct sh_eth_dev *eth)
 128 {
 129 #if defined(SH_ETH_TYPE_GETHER)
 130         int ret = 0, i;
 131
 132         /* Start e-dmac transmitter and receiver */
 133         sh_eth_write(eth, EDSR_ENALL, EDSR);
 134
 135         /* Perform a software reset and wait for it to complete */
 136         sh_eth_write(eth, EDMR_SRST, EDMR);
 137         for (i = 0; i < TIMEOUT_CNT ; i++) {
 138                 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
 139                         break;
 140                 udelay(1000);
 141         }
 142
 143         if (i == TIMEOUT_CNT) {
 144                 printf(SHETHER_NAME  ": Software reset timeout\n");
 145                 ret = -EIO;
 146         }
 147
 148         return ret;
 149 #else
 150         sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
 151         udelay(3000);
 152         sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
 153
 154         return 0;
 155 #endif
 156 }
 157
 158 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 159 {
 160         int port = eth->port, i, ret = 0;
 161         u32 tmp_addr;
 162         struct sh_eth_info *port_info = &eth->port_info[port];
 163         struct tx_desc_s *cur_tx_desc;
 164
 165         /*
 166          * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
 167          */
 168         port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
 169                                                  sizeof(struct tx_desc_s) +
 170                                                  TX_DESC_SIZE - 1);
 171         if (!port_info->tx_desc_malloc) {
 172                 printf(SHETHER_NAME ": malloc failed\n");
 173                 ret = -ENOMEM;
 174                 goto err;
 175         }
 176
 177         tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
 178                           ~(TX_DESC_SIZE - 1));
 179         flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
 180         /* Make sure we use a P2 address (non-cacheable) */
 181         port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
 182         port_info->tx_desc_cur = port_info->tx_desc_base;
 183
 184         /* Initialize all descriptors */
 185         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 186              cur_tx_desc++, i++) {
 187                 cur_tx_desc->td0 = 0x00;
 188                 cur_tx_desc->td1 = 0x00;
 189                 cur_tx_desc->td2 = 0x00;
 190         }
 191
 192         /* Mark the end of the descriptors */
 193         cur_tx_desc--;
 194         cur_tx_desc->td0 |= TD_TDLE;
 195
 196         /* Point the controller to the tx descriptor list. Must use physical
 197            addresses */
 198         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 199 #if defined(SH_ETH_TYPE_GETHER)
 200         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 201         sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 202         sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
 203 #endif
 204
 205 err:
 206         return ret;
 207 }
 208
 209 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 210 {
 211         int port = eth->port, i , ret = 0;
 212         struct sh_eth_info *port_info = &eth->port_info[port];
 213         struct rx_desc_s *cur_rx_desc;
 214         u32 tmp_addr;
 215         u8 *rx_buf;
 216
 217         /*
 218          * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
 219          */
 220         port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
 221                                                  sizeof(struct rx_desc_s) +
 222                                                  RX_DESC_SIZE - 1);
 223         if (!port_info->rx_desc_malloc) {
 224                 printf(SHETHER_NAME ": malloc failed\n");
 225                 ret = -ENOMEM;
 226                 goto err;
 227         }
 228
 229         tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
 230                           ~(RX_DESC_SIZE - 1));
 231         flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
 232         /* Make sure we use a P2 address (non-cacheable) */
 233         port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
 234
 235         port_info->rx_desc_cur = port_info->rx_desc_base;
 236
 237         /*
 238          * Allocate rx data buffers. They must be 32 bytes aligned  and in
 239          * P2 area
 240          */
 241         port_info->rx_buf_malloc = malloc(
 242                 NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
 243         if (!port_info->rx_buf_malloc) {
 244                 printf(SHETHER_NAME ": malloc failed\n");
 245                 ret = -ENOMEM;
 246                 goto err_buf_malloc;
 247         }
 248
 249         tmp_addr = (u32)(((int)port_info->rx_buf_malloc
 250                           + (RX_BUF_ALIGNE_SIZE - 1)) &
 251                           ~(RX_BUF_ALIGNE_SIZE - 1));
 252         port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
 253
 254         /* Initialize all descriptors */
 255         for (cur_rx_desc = port_info->rx_desc_base,
 256              rx_buf = port_info->rx_buf_base, i = 0;
 257              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 258                 cur_rx_desc->rd0 = RD_RACT;
 259                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 260                 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
 261         }
 262
 263         /* Mark the end of the descriptors */
 264         cur_rx_desc--;
 265         cur_rx_desc->rd0 |= RD_RDLE;
 266
 267         /* Point the controller to the rx descriptor list */
 268         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 269 #if defined(SH_ETH_TYPE_GETHER)
 270         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 271         sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 272         sh_eth_write(eth, RDFFR_RDLF, RDFFR);
 273 #endif
 274
 275         return ret;
 276
 277 err_buf_malloc:
 278         free(port_info->rx_desc_malloc);
 279         port_info->rx_desc_malloc = NULL;
 280
 281 err:
 282         return ret;
 283 }
 284
 285 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 286 {
 287         int port = eth->port;
 288         struct sh_eth_info *port_info = &eth->port_info[port];
 289
 290         if (port_info->tx_desc_malloc) {
 291                 free(port_info->tx_desc_malloc);
 292                 port_info->tx_desc_malloc = NULL;
 293         }
 294 }
 295
 296 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 297 {
 298         int port = eth->port;
 299         struct sh_eth_info *port_info = &eth->port_info[port];
 300
 301         if (port_info->rx_desc_malloc) {
 302                 free(port_info->rx_desc_malloc);
 303                 port_info->rx_desc_malloc = NULL;
 304         }
 305
 306         if (port_info->rx_buf_malloc) {
 307                 free(port_info->rx_buf_malloc);
 308                 port_info->rx_buf_malloc = NULL;
 309         }
 310 }
 311
 312 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 313 {
 314         int ret = 0;
 315
 316         ret = sh_eth_tx_desc_init(eth);
 317         if (ret)
 318                 goto err_tx_init;
 319
 320         ret = sh_eth_rx_desc_init(eth);
 321         if (ret)
 322                 goto err_rx_init;
 323
 324         return ret;
 325 err_rx_init:
 326         sh_eth_tx_desc_free(eth);
 327
 328 err_tx_init:
 329         return ret;
 330 }
 331
 332 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 333 {
 334         int port = eth->port, ret = 0;
 335         struct sh_eth_info *port_info = &eth->port_info[port];
 336         struct eth_device *dev = port_info->dev;
 337         struct phy_device *phydev;
 338
 339         phydev = phy_connect(
 340                         miiphy_get_dev_by_name(dev->name),
 341                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 342         port_info->phydev = phydev;
 343         phy_config(phydev);
 344
 345         return ret;
 346 }
 347
 348 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 349 {
 350         int port = eth->port, ret = 0;
 351         u32 val;
 352         struct sh_eth_info *port_info = &eth->port_info[port];
 353         struct eth_device *dev = port_info->dev;
 354         struct phy_device *phy;
 355
 356         /* Configure e-dmac registers */
 357         sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
 358                         (EMDR_DESC | EDMR_EL), EDMR);
 359
 360         sh_eth_write(eth, 0, EESIPR);
 361         sh_eth_write(eth, 0, TRSCER);
 362         sh_eth_write(eth, 0, TFTR);
 363         sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 364         sh_eth_write(eth, RMCR_RST, RMCR);
 365 #if defined(SH_ETH_TYPE_GETHER)
 366         sh_eth_write(eth, 0, RPADIR);
 367 #endif
 368         sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 369
 370         /* Configure e-mac registers */
 371         sh_eth_write(eth, 0, ECSIPR);
 372
 373         /* Set Mac address */
 374         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 375             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 376         sh_eth_write(eth, val, MAHR);
 377
 378         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 379         sh_eth_write(eth, val, MALR);
 380
 381         sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
 382 #if defined(SH_ETH_TYPE_GETHER)
 383         sh_eth_write(eth, 0, PIPR);
 384         sh_eth_write(eth, APR_AP, APR);
 385         sh_eth_write(eth, MPR_MP, MPR);
 386         sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
 387 #endif
 388
 389 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 390         sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 391 #endif
 392         /* Configure phy */
 393         ret = sh_eth_phy_config(eth);
 394         if (ret) {
 395                 printf(SHETHER_NAME ": phy config timeout\n");
 396                 goto err_phy_cfg;
 397         }
 398         phy = port_info->phydev;
 399         ret = phy_startup(phy);
 400         if (ret) {
 401                 printf(SHETHER_NAME ": phy startup failure\n");
 402                 return ret;
 403         }
 404
 405         val = 0;
 406
 407         /* Set the transfer speed */
 408         if (phy->speed == 100) {
 409                 printf(SHETHER_NAME ": 100Base/");
 410 #if defined(SH_ETH_TYPE_GETHER)
 411                 sh_eth_write(eth, GECMR_100B, GECMR);
 412 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 413                 sh_eth_write(eth, 1, RTRATE);
 414 #elif defined(CONFIG_CPU_SH7724)
 415                 val = ECMR_RTM;
 416 #endif
 417         } else if (phy->speed == 10) {
 418                 printf(SHETHER_NAME ": 10Base/");
 419 #if defined(SH_ETH_TYPE_GETHER)
 420                 sh_eth_write(eth, GECMR_10B, GECMR);
 421 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 422                 sh_eth_write(eth, 0, RTRATE);
 423 #endif
 424         }
 425 #if defined(SH_ETH_TYPE_GETHER)
 426         else if (phy->speed == 1000) {
 427                 printf(SHETHER_NAME ": 1000Base/");
 428                 sh_eth_write(eth, GECMR_1000B, GECMR);
 429         }
 430 #endif
 431
 432         /* Check if full duplex mode is supported by the phy */
 433         if (phy->duplex) {
 434                 printf("Full\n");
 435                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
 436                              ECMR);
 437         } else {
 438                 printf("Half\n");
 439                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
 440         }
 441
 442         return ret;
 443
 444 err_phy_cfg:
 445         return ret;
 446 }
 447
 448 static void sh_eth_start(struct sh_eth_dev *eth)
 449 {
 450         /*
 451          * Enable the e-dmac receiver only. The transmitter will be enabled when
 452          * we have something to transmit
 453          */
 454         sh_eth_write(eth, EDRRR_R, EDRRR);
 455 }
 456
 457 static void sh_eth_stop(struct sh_eth_dev *eth)
 458 {
 459         sh_eth_write(eth, ~EDRRR_R, EDRRR);
 460 }
 461
 462 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 463 {
 464         int ret = 0;
 465         struct sh_eth_dev *eth = dev->priv;
 466
 467         ret = sh_eth_reset(eth);
 468         if (ret)
 469                 goto err;
 470
 471         ret = sh_eth_desc_init(eth);
 472         if (ret)
 473                 goto err;
 474
 475         ret = sh_eth_config(eth, bd);
 476         if (ret)
 477                 goto err_config;
 478
 479         sh_eth_start(eth);
 480
 481         return ret;
 482
 483 err_config:
 484         sh_eth_tx_desc_free(eth);
 485         sh_eth_rx_desc_free(eth);
 486
 487 err:
 488         return ret;
 489 }
 490
 491 void sh_eth_halt(struct eth_device *dev)
 492 {
 493         struct sh_eth_dev *eth = dev->priv;
 494         sh_eth_stop(eth);
 495 }
 496
 497 int sh_eth_initialize(bd_t *bd)
 498 {
 499     int ret = 0;
 500         struct sh_eth_dev *eth = NULL;
 501     struct eth_device *dev = NULL;
 502
 503     eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 504         if (!eth) {
 505                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 506                 ret = -ENOMEM;
 507                 goto err;
 508         }
 509
 510     dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 511         if (!dev) {
 512                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 513                 ret = -ENOMEM;
 514                 goto err;
 515         }
 516     memset(dev, 0, sizeof(struct eth_device));
 517     memset(eth, 0, sizeof(struct sh_eth_dev));
 518
 519         eth->port = CONFIG_SH_ETHER_USE_PORT;
 520         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 521
 522     dev->priv = (void *)eth;
 523     dev->iobase = 0;
 524     dev->init = sh_eth_init;
 525     dev->halt = sh_eth_halt;
 526     dev->send = sh_eth_send;
 527     dev->recv = sh_eth_recv;
 528     eth->port_info[eth->port].dev = dev;
 529
 530         sprintf(dev->name, SHETHER_NAME);
 531
 532     /* Register Device to EtherNet subsystem  */
 533     eth_register(dev);
 534
 535         bb_miiphy_buses[0].priv = eth;
 536         miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
 537
 538         if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
 539                 puts("Please set MAC address\n");
 540
 541         return ret;
 542
 543 err:
 544         if (dev)
 545                 free(dev);
 546
 547         if (eth)
 548                 free(eth);
 549
 550         printf(SHETHER_NAME ": Failed\n");
 551         return ret;
 552 }
 553
 554 /******* for bb_miiphy *******/
 555 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 556 {
 557         return 0;
 558 }
 559
 560 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 561 {
 562         struct sh_eth_dev *eth = bus->priv;
 563
 564         sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
 565
 566         return 0;
 567 }
 568
 569 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 570 {
 571         struct sh_eth_dev *eth = bus->priv;
 572
 573         sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
 574
 575         return 0;
 576 }
 577
 578 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 579 {
 580         struct sh_eth_dev *eth = bus->priv;
 581
 582         if (v)
 583                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
 584         else
 585                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
 586
 587         return 0;
 588 }
 589
 590 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 591 {
 592         struct sh_eth_dev *eth = bus->priv;
 593
 594         *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
 595
 596         return 0;
 597 }
 598
 599 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 600 {
 601         struct sh_eth_dev *eth = bus->priv;
 602
 603         if (v)
 604                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
 605         else
 606                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
 607
 608         return 0;
 609 }
 610
 611 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 612 {
 613         udelay(10);
 614
 615         return 0;
 616 }
 617
 618 struct bb_miiphy_bus bb_miiphy_buses[] = {
 619         {
 620                 .name           = "sh_eth",
 621                 .init           = sh_eth_bb_init,
 622                 .mdio_active    = sh_eth_bb_mdio_active,
 623                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 624                 .set_mdio       = sh_eth_bb_set_mdio,
 625                 .get_mdio       = sh_eth_bb_get_mdio,
 626                 .set_mdc        = sh_eth_bb_set_mdc,
 627                 .delay          = sh_eth_bb_delay,
 628         }
 629 };
 630 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);