drivers/net/smc911x.c

   1 /*
   2  * SMSC LAN9[12]1[567] Network driver
   3  *
   4  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <net.h>
  28 #include <miiphy.h>
  29
  30 #if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
  31         defined (CONFIG_DRIVER_SMC911X_16_BIT)
  32 #error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
  33         CONFIG_DRIVER_SMC911X_16_BIT shall be set"
  34 #endif
  35
  36 #if defined (CONFIG_DRIVER_SMC911X_32_BIT)
  37 static inline u32 __smc911x_reg_read(u32 addr)
  38 {
  39         return *(volatile u32*)addr;
  40 }
  41 u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
  42
  43 static inline void __smc911x_reg_write(u32 addr, u32 val)
  44 {
  45         *(volatile u32*)addr = val;
  46 }
  47 void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
  48 #elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
  49 static inline u32 smc911x_reg_read(u32 addr)
  50 {
  51         volatile u16 *addr_16 = (u16 *)addr;
  52         return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  53 }
  54 static inline void smc911x_reg_write(u32 addr, u32 val)
  55 {
  56         *(volatile u16*)addr = (u16)val;
  57         *(volatile u16*)(addr + 2) = (u16)(val >> 16);
  58 }
  59 #else
  60 #error "SMC911X: undefined bus width"
  61 #endif /* CONFIG_DRIVER_SMC911X_16_BIT */
  62
  63 u32 pkt_data_pull(u32 addr) \
  64         __attribute__ ((weak, alias ("smc911x_reg_read")));
  65 void pkt_data_push(u32 addr, u32 val) \
  66         __attribute__ ((weak, alias ("smc911x_reg_write")));
  67
  68 #define mdelay(n)       udelay((n)*1000)
  69
  70 /* Below are the register offsets and bit definitions
  71  * of the Lan911x memory space
  72  */
  73 #define RX_DATA_FIFO             (CONFIG_DRIVER_SMC911X_BASE + 0x00)
  74
  75 #define TX_DATA_FIFO             (CONFIG_DRIVER_SMC911X_BASE + 0x20)
  76 #define TX_CMD_A_INT_ON_COMP                    0x80000000
  77 #define TX_CMD_A_INT_BUF_END_ALGN               0x03000000
  78 #define TX_CMD_A_INT_4_BYTE_ALGN                0x00000000
  79 #define TX_CMD_A_INT_16_BYTE_ALGN               0x01000000
  80 #define TX_CMD_A_INT_32_BYTE_ALGN               0x02000000
  81 #define TX_CMD_A_INT_DATA_OFFSET                0x001F0000
  82 #define TX_CMD_A_INT_FIRST_SEG                  0x00002000
  83 #define TX_CMD_A_INT_LAST_SEG                   0x00001000
  84 #define TX_CMD_A_BUF_SIZE                       0x000007FF
  85 #define TX_CMD_B_PKT_TAG                        0xFFFF0000
  86 #define TX_CMD_B_ADD_CRC_DISABLE                0x00002000
  87 #define TX_CMD_B_DISABLE_PADDING                0x00001000
  88 #define TX_CMD_B_PKT_BYTE_LENGTH                0x000007FF
  89
  90 #define RX_STATUS_FIFO          (CONFIG_DRIVER_SMC911X_BASE + 0x40)
  91 #define RX_STS_PKT_LEN                          0x3FFF0000
  92 #define RX_STS_ES                               0x00008000
  93 #define RX_STS_BCST                             0x00002000
  94 #define RX_STS_LEN_ERR                          0x00001000
  95 #define RX_STS_RUNT_ERR                         0x00000800
  96 #define RX_STS_MCAST                            0x00000400
  97 #define RX_STS_TOO_LONG                         0x00000080
  98 #define RX_STS_COLL                             0x00000040
  99 #define RX_STS_ETH_TYPE                         0x00000020
 100 #define RX_STS_WDOG_TMT                         0x00000010
 101 #define RX_STS_MII_ERR                          0x00000008
 102 #define RX_STS_DRIBBLING                        0x00000004
 103 #define RX_STS_CRC_ERR                          0x00000002
 104 #define RX_STATUS_FIFO_PEEK     (CONFIG_DRIVER_SMC911X_BASE + 0x44)
 105 #define TX_STATUS_FIFO          (CONFIG_DRIVER_SMC911X_BASE + 0x48)
 106 #define TX_STS_TAG                              0xFFFF0000
 107 #define TX_STS_ES                               0x00008000
 108 #define TX_STS_LOC                              0x00000800
 109 #define TX_STS_NO_CARR                          0x00000400
 110 #define TX_STS_LATE_COLL                        0x00000200
 111 #define TX_STS_MANY_COLL                        0x00000100
 112 #define TX_STS_COLL_CNT                         0x00000078
 113 #define TX_STS_MANY_DEFER                       0x00000004
 114 #define TX_STS_UNDERRUN                         0x00000002
 115 #define TX_STS_DEFERRED                         0x00000001
 116 #define TX_STATUS_FIFO_PEEK     (CONFIG_DRIVER_SMC911X_BASE + 0x4C)
 117 #define ID_REV                  (CONFIG_DRIVER_SMC911X_BASE + 0x50)
 118 #define ID_REV_CHIP_ID                          0xFFFF0000  /* RO */
 119 #define ID_REV_REV_ID                           0x0000FFFF  /* RO */
 120
 121 #define INT_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0x54)
 122 #define INT_CFG_INT_DEAS                        0xFF000000  /* R/W */
 123 #define INT_CFG_INT_DEAS_CLR                    0x00004000
 124 #define INT_CFG_INT_DEAS_STS                    0x00002000
 125 #define INT_CFG_IRQ_INT                         0x00001000  /* RO */
 126 #define INT_CFG_IRQ_EN                          0x00000100  /* R/W */
 127 #define INT_CFG_IRQ_POL                         0x00000010  /* R/W Not Affected by SW Reset */
 128 #define INT_CFG_IRQ_TYPE                        0x00000001  /* R/W Not Affected by SW Reset */
 129
 130 #define INT_STS                 (CONFIG_DRIVER_SMC911X_BASE + 0x58)
 131 #define INT_STS_SW_INT                          0x80000000  /* R/WC */
 132 #define INT_STS_TXSTOP_INT                      0x02000000  /* R/WC */
 133 #define INT_STS_RXSTOP_INT                      0x01000000  /* R/WC */
 134 #define INT_STS_RXDFH_INT                       0x00800000  /* R/WC */
 135 #define INT_STS_RXDF_INT                        0x00400000  /* R/WC */
 136 #define INT_STS_TX_IOC                          0x00200000  /* R/WC */
 137 #define INT_STS_RXD_INT                         0x00100000  /* R/WC */
 138 #define INT_STS_GPT_INT                         0x00080000  /* R/WC */
 139 #define INT_STS_PHY_INT                         0x00040000  /* RO */
 140 #define INT_STS_PME_INT                         0x00020000  /* R/WC */
 141 #define INT_STS_TXSO                            0x00010000  /* R/WC */
 142 #define INT_STS_RWT                             0x00008000  /* R/WC */
 143 #define INT_STS_RXE                             0x00004000  /* R/WC */
 144 #define INT_STS_TXE                             0x00002000  /* R/WC */
 145 /*#define       INT_STS_ERX             0x00001000*/  /* R/WC */
 146 #define INT_STS_TDFU                            0x00000800  /* R/WC */
 147 #define INT_STS_TDFO                            0x00000400  /* R/WC */
 148 #define INT_STS_TDFA                            0x00000200  /* R/WC */
 149 #define INT_STS_TSFF                            0x00000100  /* R/WC */
 150 #define INT_STS_TSFL                            0x00000080  /* R/WC */
 151 /*#define       INT_STS_RXDF            0x00000040*/  /* R/WC */
 152 #define INT_STS_RDFO                            0x00000040  /* R/WC */
 153 #define INT_STS_RDFL                            0x00000020  /* R/WC */
 154 #define INT_STS_RSFF                            0x00000010  /* R/WC */
 155 #define INT_STS_RSFL                            0x00000008  /* R/WC */
 156 #define INT_STS_GPIO2_INT                       0x00000004  /* R/WC */
 157 #define INT_STS_GPIO1_INT                       0x00000002  /* R/WC */
 158 #define INT_STS_GPIO0_INT                       0x00000001  /* R/WC */
 159 #define INT_EN                  (CONFIG_DRIVER_SMC911X_BASE + 0x5C)
 160 #define INT_EN_SW_INT_EN                        0x80000000  /* R/W */
 161 #define INT_EN_TXSTOP_INT_EN                    0x02000000  /* R/W */
 162 #define INT_EN_RXSTOP_INT_EN                    0x01000000  /* R/W */
 163 #define INT_EN_RXDFH_INT_EN                     0x00800000  /* R/W */
 164 /*#define       INT_EN_RXDF_INT_EN              0x00400000*/  /* R/W */
 165 #define INT_EN_TIOC_INT_EN                      0x00200000  /* R/W */
 166 #define INT_EN_RXD_INT_EN                       0x00100000  /* R/W */
 167 #define INT_EN_GPT_INT_EN                       0x00080000  /* R/W */
 168 #define INT_EN_PHY_INT_EN                       0x00040000  /* R/W */
 169 #define INT_EN_PME_INT_EN                       0x00020000  /* R/W */
 170 #define INT_EN_TXSO_EN                          0x00010000  /* R/W */
 171 #define INT_EN_RWT_EN                           0x00008000  /* R/W */
 172 #define INT_EN_RXE_EN                           0x00004000  /* R/W */
 173 #define INT_EN_TXE_EN                           0x00002000  /* R/W */
 174 /*#define       INT_EN_ERX_EN                   0x00001000*/  /* R/W */
 175 #define INT_EN_TDFU_EN                          0x00000800  /* R/W */
 176 #define INT_EN_TDFO_EN                          0x00000400  /* R/W */
 177 #define INT_EN_TDFA_EN                          0x00000200  /* R/W */
 178 #define INT_EN_TSFF_EN                          0x00000100  /* R/W */
 179 #define INT_EN_TSFL_EN                          0x00000080  /* R/W */
 180 /*#define       INT_EN_RXDF_EN                  0x00000040*/  /* R/W */
 181 #define INT_EN_RDFO_EN                          0x00000040  /* R/W */
 182 #define INT_EN_RDFL_EN                          0x00000020  /* R/W */
 183 #define INT_EN_RSFF_EN                          0x00000010  /* R/W */
 184 #define INT_EN_RSFL_EN                          0x00000008  /* R/W */
 185 #define INT_EN_GPIO2_INT                        0x00000004  /* R/W */
 186 #define INT_EN_GPIO1_INT                        0x00000002  /* R/W */
 187 #define INT_EN_GPIO0_INT                        0x00000001  /* R/W */
 188
 189 #define BYTE_TEST               (CONFIG_DRIVER_SMC911X_BASE + 0x64)
 190 #define FIFO_INT                (CONFIG_DRIVER_SMC911X_BASE + 0x68)
 191 #define FIFO_INT_TX_AVAIL_LEVEL                 0xFF000000  /* R/W */
 192 #define FIFO_INT_TX_STS_LEVEL                   0x00FF0000  /* R/W */
 193 #define FIFO_INT_RX_AVAIL_LEVEL                 0x0000FF00  /* R/W */
 194 #define FIFO_INT_RX_STS_LEVEL                   0x000000FF  /* R/W */
 195
 196 #define RX_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x6C)
 197 #define RX_CFG_RX_END_ALGN                      0xC0000000  /* R/W */
 198 #define         RX_CFG_RX_END_ALGN4             0x00000000  /* R/W */
 199 #define         RX_CFG_RX_END_ALGN16            0x40000000  /* R/W */
 200 #define         RX_CFG_RX_END_ALGN32            0x80000000  /* R/W */
 201 #define RX_CFG_RX_DMA_CNT                       0x0FFF0000  /* R/W */
 202 #define RX_CFG_RX_DUMP                          0x00008000  /* R/W */
 203 #define RX_CFG_RXDOFF                           0x00001F00  /* R/W */
 204 /*#define       RX_CFG_RXBAD                    0x00000001*/  /* R/W */
 205
 206 #define TX_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x70)
 207 /*#define       TX_CFG_TX_DMA_LVL               0xE0000000*/     /* R/W */
 208 /*#define       TX_CFG_TX_DMA_CNT               0x0FFF0000*/     /* R/W Self Clearing */
 209 #define TX_CFG_TXS_DUMP                         0x00008000  /* Self Clearing */
 210 #define TX_CFG_TXD_DUMP                         0x00004000  /* Self Clearing */
 211 #define TX_CFG_TXSAO                            0x00000004  /* R/W */
 212 #define TX_CFG_TX_ON                            0x00000002  /* R/W */
 213 #define TX_CFG_STOP_TX                          0x00000001  /* Self Clearing */
 214
 215 #define HW_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x74)
 216 #define HW_CFG_TTM                              0x00200000  /* R/W */
 217 #define HW_CFG_SF                               0x00100000  /* R/W */
 218 #define HW_CFG_TX_FIF_SZ                        0x000F0000  /* R/W */
 219 #define HW_CFG_TR                               0x00003000  /* R/W */
 220 #define HW_CFG_PHY_CLK_SEL                      0x00000060  /* R/W */
 221 #define HW_CFG_PHY_CLK_SEL_INT_PHY              0x00000000 /* R/W */
 222 #define HW_CFG_PHY_CLK_SEL_EXT_PHY              0x00000020 /* R/W */
 223 #define HW_CFG_PHY_CLK_SEL_CLK_DIS              0x00000040 /* R/W */
 224 #define HW_CFG_SMI_SEL                          0x00000010  /* R/W */
 225 #define HW_CFG_EXT_PHY_DET                      0x00000008  /* RO */
 226 #define HW_CFG_EXT_PHY_EN                       0x00000004  /* R/W */
 227 #define HW_CFG_32_16_BIT_MODE                   0x00000004  /* RO */
 228 #define HW_CFG_SRST_TO                          0x00000002  /* RO */
 229 #define HW_CFG_SRST                             0x00000001  /* Self Clearing */
 230
 231 #define RX_DP_CTRL              (CONFIG_DRIVER_SMC911X_BASE + 0x78)
 232 #define RX_DP_CTRL_RX_FFWD                      0x80000000  /* R/W */
 233 #define RX_DP_CTRL_FFWD_BUSY                    0x80000000  /* RO */
 234
 235 #define RX_FIFO_INF             (CONFIG_DRIVER_SMC911X_BASE + 0x7C)
 236 #define  RX_FIFO_INF_RXSUSED                    0x00FF0000  /* RO */
 237 #define  RX_FIFO_INF_RXDUSED                    0x0000FFFF  /* RO */
 238
 239 #define TX_FIFO_INF             (CONFIG_DRIVER_SMC911X_BASE + 0x80)
 240 #define TX_FIFO_INF_TSUSED                      0x00FF0000  /* RO */
 241 #define TX_FIFO_INF_TDFREE                      0x0000FFFF  /* RO */
 242
 243 #define PMT_CTRL                (CONFIG_DRIVER_SMC911X_BASE + 0x84)
 244 #define PMT_CTRL_PM_MODE                        0x00003000  /* Self Clearing */
 245 #define PMT_CTRL_PHY_RST                        0x00000400  /* Self Clearing */
 246 #define PMT_CTRL_WOL_EN                         0x00000200  /* R/W */
 247 #define PMT_CTRL_ED_EN                          0x00000100  /* R/W */
 248 #define PMT_CTRL_PME_TYPE                       0x00000040  /* R/W Not Affected by SW Reset */
 249 #define PMT_CTRL_WUPS                           0x00000030  /* R/WC */
 250 #define PMT_CTRL_WUPS_NOWAKE                    0x00000000  /* R/WC */
 251 #define PMT_CTRL_WUPS_ED                        0x00000010  /* R/WC */
 252 #define PMT_CTRL_WUPS_WOL                       0x00000020  /* R/WC */
 253 #define PMT_CTRL_WUPS_MULTI                     0x00000030  /* R/WC */
 254 #define PMT_CTRL_PME_IND                        0x00000008  /* R/W */
 255 #define PMT_CTRL_PME_POL                        0x00000004  /* R/W */
 256 #define PMT_CTRL_PME_EN                         0x00000002  /* R/W Not Affected by SW Reset */
 257 #define PMT_CTRL_READY                          0x00000001  /* RO */
 258
 259 #define GPIO_CFG                (CONFIG_DRIVER_SMC911X_BASE + 0x88)
 260 #define GPIO_CFG_LED3_EN                        0x40000000  /* R/W */
 261 #define GPIO_CFG_LED2_EN                        0x20000000  /* R/W */
 262 #define GPIO_CFG_LED1_EN                        0x10000000  /* R/W */
 263 #define GPIO_CFG_GPIO2_INT_POL                  0x04000000  /* R/W */
 264 #define GPIO_CFG_GPIO1_INT_POL                  0x02000000  /* R/W */
 265 #define GPIO_CFG_GPIO0_INT_POL                  0x01000000  /* R/W */
 266 #define GPIO_CFG_EEPR_EN                        0x00700000  /* R/W */
 267 #define GPIO_CFG_GPIOBUF2                       0x00040000  /* R/W */
 268 #define GPIO_CFG_GPIOBUF1                       0x00020000  /* R/W */
 269 #define GPIO_CFG_GPIOBUF0                       0x00010000  /* R/W */
 270 #define GPIO_CFG_GPIODIR2                       0x00000400  /* R/W */
 271 #define GPIO_CFG_GPIODIR1                       0x00000200  /* R/W */
 272 #define GPIO_CFG_GPIODIR0                       0x00000100  /* R/W */
 273 #define GPIO_CFG_GPIOD4                         0x00000010  /* R/W */
 274 #define GPIO_CFG_GPIOD3                         0x00000008  /* R/W */
 275 #define GPIO_CFG_GPIOD2                         0x00000004  /* R/W */
 276 #define GPIO_CFG_GPIOD1                         0x00000002  /* R/W */
 277 #define GPIO_CFG_GPIOD0                         0x00000001  /* R/W */
 278
 279 #define GPT_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0x8C)
 280 #define GPT_CFG_TIMER_EN                        0x20000000  /* R/W */
 281 #define GPT_CFG_GPT_LOAD                        0x0000FFFF  /* R/W */
 282
 283 #define GPT_CNT                 (CONFIG_DRIVER_SMC911X_BASE + 0x90)
 284 #define GPT_CNT_GPT_CNT                         0x0000FFFF  /* RO */
 285
 286 #define ENDIAN                  (CONFIG_DRIVER_SMC911X_BASE + 0x98)
 287 #define FREE_RUN                (CONFIG_DRIVER_SMC911X_BASE + 0x9C)
 288 #define RX_DROP                 (CONFIG_DRIVER_SMC911X_BASE + 0xA0)
 289 #define MAC_CSR_CMD             (CONFIG_DRIVER_SMC911X_BASE + 0xA4)
 290 #define  MAC_CSR_CMD_CSR_BUSY                   0x80000000  /* Self Clearing */
 291 #define  MAC_CSR_CMD_R_NOT_W                    0x40000000  /* R/W */
 292 #define  MAC_CSR_CMD_CSR_ADDR                   0x000000FF  /* R/W */
 293
 294 #define MAC_CSR_DATA            (CONFIG_DRIVER_SMC911X_BASE + 0xA8)
 295 #define AFC_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0xAC)
 296 #define         AFC_CFG_AFC_HI                  0x00FF0000  /* R/W */
 297 #define         AFC_CFG_AFC_LO                  0x0000FF00  /* R/W */
 298 #define         AFC_CFG_BACK_DUR                0x000000F0  /* R/W */
 299 #define         AFC_CFG_FCMULT                  0x00000008  /* R/W */
 300 #define         AFC_CFG_FCBRD                   0x00000004  /* R/W */
 301 #define         AFC_CFG_FCADD                   0x00000002  /* R/W */
 302 #define         AFC_CFG_FCANY                   0x00000001  /* R/W */
 303
 304 #define E2P_CMD                 (CONFIG_DRIVER_SMC911X_BASE + 0xB0)
 305 #define         E2P_CMD_EPC_BUSY                0x80000000  /* Self Clearing */
 306 #define         E2P_CMD_EPC_CMD                 0x70000000  /* R/W */
 307 #define         E2P_CMD_EPC_CMD_READ            0x00000000  /* R/W */
 308 #define         E2P_CMD_EPC_CMD_EWDS            0x10000000  /* R/W */
 309 #define         E2P_CMD_EPC_CMD_EWEN            0x20000000  /* R/W */
 310 #define         E2P_CMD_EPC_CMD_WRITE           0x30000000  /* R/W */
 311 #define         E2P_CMD_EPC_CMD_WRAL            0x40000000  /* R/W */
 312 #define         E2P_CMD_EPC_CMD_ERASE           0x50000000  /* R/W */
 313 #define         E2P_CMD_EPC_CMD_ERAL            0x60000000  /* R/W */
 314 #define         E2P_CMD_EPC_CMD_RELOAD          0x70000000  /* R/W */
 315 #define         E2P_CMD_EPC_TIMEOUT             0x00000200  /* RO */
 316 #define         E2P_CMD_MAC_ADDR_LOADED         0x00000100  /* RO */
 317 #define         E2P_CMD_EPC_ADDR                0x000000FF  /* R/W */
 318
 319 #define E2P_DATA                (CONFIG_DRIVER_SMC911X_BASE + 0xB4)
 320 #define E2P_DATA_EEPROM_DATA                    0x000000FF  /* R/W */
 321 /* end of LAN register offsets and bit definitions */
 322
 323 /* MAC Control and Status registers */
 324 #define MAC_CR                  0x01  /* R/W */
 325
 326 /* MAC_CR - MAC Control Register */
 327 #define MAC_CR_RXALL                    0x80000000
 328 /* TODO: delete this bit? It is not described in the data sheet. */
 329 #define MAC_CR_HBDIS                    0x10000000
 330 #define MAC_CR_RCVOWN                   0x00800000
 331 #define MAC_CR_LOOPBK                   0x00200000
 332 #define MAC_CR_FDPX                     0x00100000
 333 #define MAC_CR_MCPAS                    0x00080000
 334 #define MAC_CR_PRMS                     0x00040000
 335 #define MAC_CR_INVFILT                  0x00020000
 336 #define MAC_CR_PASSBAD                  0x00010000
 337 #define MAC_CR_HFILT                    0x00008000
 338 #define MAC_CR_HPFILT                   0x00002000
 339 #define MAC_CR_LCOLL                    0x00001000
 340 #define MAC_CR_BCAST                    0x00000800
 341 #define MAC_CR_DISRTY                   0x00000400
 342 #define MAC_CR_PADSTR                   0x00000100
 343 #define MAC_CR_BOLMT_MASK               0x000000C0
 344 #define MAC_CR_DFCHK                    0x00000020
 345 #define MAC_CR_TXEN                     0x00000008
 346 #define MAC_CR_RXEN                     0x00000004
 347
 348 #define ADDRH                   0x02      /* R/W mask 0x0000FFFFUL */
 349 #define ADDRL                   0x03      /* R/W mask 0xFFFFFFFFUL */
 350 #define HASHH                   0x04      /* R/W */
 351 #define HASHL                   0x05      /* R/W */
 352
 353 #define MII_ACC                 0x06      /* R/W */
 354 #define MII_ACC_PHY_ADDR                0x0000F800
 355 #define MII_ACC_MIIRINDA                0x000007C0
 356 #define MII_ACC_MII_WRITE               0x00000002
 357 #define MII_ACC_MII_BUSY                0x00000001
 358
 359 #define MII_DATA                0x07      /* R/W mask 0x0000FFFFUL */
 360
 361 #define FLOW                    0x08      /* R/W */
 362 #define FLOW_FCPT                       0xFFFF0000
 363 #define FLOW_FCPASS                     0x00000004
 364 #define FLOW_FCEN                       0x00000002
 365 #define FLOW_FCBSY                      0x00000001
 366
 367 #define VLAN1                   0x09      /* R/W mask 0x0000FFFFUL */
 368 #define VLAN1_VTI1                      0x0000ffff
 369
 370 #define VLAN2                   0x0A      /* R/W mask 0x0000FFFFUL */
 371 #define VLAN2_VTI2                      0x0000ffff
 372
 373 #define WUFF                    0x0B      /* WO */
 374
 375 #define WUCSR                   0x0C      /* R/W */
 376 #define WUCSR_GUE                       0x00000200
 377 #define WUCSR_WUFR                      0x00000040
 378 #define WUCSR_MPR                       0x00000020
 379 #define WUCSR_WAKE_EN                   0x00000004
 380 #define WUCSR_MPEN                      0x00000002
 381
 382 /* Chip ID values */
 383 #define CHIP_9115       0x115
 384 #define CHIP_9116       0x116
 385 #define CHIP_9117       0x117
 386 #define CHIP_9118       0x118
 387 #define CHIP_9211       0x9211
 388 #define CHIP_9215       0x115a
 389 #define CHIP_9216       0x116a
 390 #define CHIP_9217       0x117a
 391 #define CHIP_9218       0x118a
 392
 393 struct chip_id {
 394         u16 id;
 395         char *name;
 396 };
 397
 398 static const struct chip_id chip_ids[] =  {
 399         { CHIP_9115, "LAN9115" },
 400         { CHIP_9116, "LAN9116" },
 401         { CHIP_9117, "LAN9117" },
 402         { CHIP_9118, "LAN9118" },
 403         { CHIP_9211, "LAN9211" },
 404         { CHIP_9215, "LAN9215" },
 405         { CHIP_9216, "LAN9216" },
 406         { CHIP_9217, "LAN9217" },
 407         { CHIP_9218, "LAN9218" },
 408         { 0, NULL },
 409 };
 410
 411 #define DRIVERNAME "smc911x"
 412
 413 u32 smc911x_get_mac_csr(u8 reg)
 414 {
 415         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 416                 ;
 417         smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
 418         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 419                 ;
 420
 421         return smc911x_reg_read(MAC_CSR_DATA);
 422 }
 423
 424 void smc911x_set_mac_csr(u8 reg, u32 data)
 425 {
 426         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 427                 ;
 428         smc911x_reg_write(MAC_CSR_DATA, data);
 429         smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
 430         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 431                 ;
 432 }
 433
 434 static int smx911x_handle_mac_address(bd_t *bd)
 435 {
 436         unsigned long addrh, addrl;
 437         unsigned char *m = bd->bi_enetaddr;
 438
 439         /* if the environment has a valid mac address then use it */
 440         if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) {
 441                 addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24;
 442                 addrh = m[4] | m[5] << 8;
 443                 smc911x_set_mac_csr(ADDRH, addrh);
 444                 smc911x_set_mac_csr(ADDRL, addrl);
 445         } else {
 446                 /* if not, try to get one from the eeprom */
 447                 addrh = smc911x_get_mac_csr(ADDRH);
 448                 addrl = smc911x_get_mac_csr(ADDRL);
 449
 450                 m[0] = (addrl       ) & 0xff;
 451                 m[1] = (addrl >>  8 ) & 0xff;
 452                 m[2] = (addrl >> 16 ) & 0xff;
 453                 m[3] = (addrl >> 24 ) & 0xff;
 454                 m[4] = (addrh       ) & 0xff;
 455                 m[5] = (addrh >>  8 ) & 0xff;
 456
 457                 /* we get 0xff when there is no eeprom connected */
 458                 if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
 459                         printf(DRIVERNAME ": no valid mac address in environment "
 460                                 "and no eeprom found\n");
 461                         return -1;
 462                 }
 463         }
 464
 465         printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
 466                 m[0], m[1], m[2], m[3], m[4], m[5]);
 467
 468         return 0;
 469 }
 470
 471 static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
 472 {
 473         while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
 474                 ;
 475
 476         smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
 477
 478         while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
 479                 ;
 480
 481         *val = smc911x_get_mac_csr(MII_DATA);
 482
 483         return 0;
 484 }
 485
 486 static int smc911x_miiphy_write(u8 phy, u8 reg, u16  val)
 487 {
 488         while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
 489                 ;
 490
 491         smc911x_set_mac_csr(MII_DATA, val);
 492         smc911x_set_mac_csr(MII_ACC,
 493                 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
 494
 495         while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
 496                 ;
 497         return 0;
 498 }
 499
 500 static int smc911x_phy_reset(void)
 501 {
 502         u32 reg;
 503
 504         reg = smc911x_reg_read(PMT_CTRL);
 505         reg &= ~0xfffff030;
 506         reg |= PMT_CTRL_PHY_RST;
 507         smc911x_reg_write(PMT_CTRL, reg);
 508
 509         mdelay(100);
 510
 511         return 0;
 512 }
 513
 514 static void smc911x_phy_configure(void)
 515 {
 516         int timeout;
 517         u16 status;
 518
 519         smc911x_phy_reset();
 520
 521         smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
 522         mdelay(1);
 523         smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
 524         smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 525
 526         timeout = 5000;
 527         do {
 528                 mdelay(1);
 529                 if ((timeout--) == 0)
 530                         goto err_out;
 531
 532                 if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
 533                         goto err_out;
 534         } while (!(status & PHY_BMSR_LS));
 535
 536         printf(DRIVERNAME ": phy initialized\n");
 537
 538         return;
 539
 540 err_out:
 541         printf(DRIVERNAME ": autonegotiation timed out\n");
 542 }
 543
 544 static void smc911x_reset(void)
 545 {
 546         int timeout;
 547
 548         /* Take out of PM setting first */
 549         if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
 550                 /* Write to the bytetest will take out of powerdown */
 551                 smc911x_reg_write(BYTE_TEST, 0x0);
 552
 553                 timeout = 10;
 554
 555                 while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
 556                         udelay(10);
 557                 if (!timeout) {
 558                         printf(DRIVERNAME
 559                                 ": timeout waiting for PM restore\n");
 560                         return;
 561                 }
 562         }
 563
 564         /* Disable interrupts */
 565         smc911x_reg_write(INT_EN, 0);
 566
 567         smc911x_reg_write(HW_CFG, HW_CFG_SRST);
 568
 569         timeout = 1000;
 570         while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
 571                 udelay(10);
 572
 573         if (!timeout) {
 574                 printf(DRIVERNAME ": reset timeout\n");
 575                 return;
 576         }
 577
 578         /* Reset the FIFO level and flow control settings */
 579         smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
 580         smc911x_reg_write(AFC_CFG, 0x0050287F);
 581
 582         /* Set to LED outputs */
 583         smc911x_reg_write(GPIO_CFG, 0x70070000);
 584 }
 585
 586 static void smc911x_enable(void)
 587 {
 588         /* Enable TX */
 589         smc911x_reg_write(HW_CFG, 8 << 16 | HW_CFG_SF);
 590
 591         smc911x_reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000);
 592
 593         smc911x_reg_write(TX_CFG, TX_CFG_TX_ON);
 594
 595         /* no padding to start of packets */
 596         smc911x_reg_write(RX_CFG, 0);
 597
 598         smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
 599
 600 }
 601
 602 int eth_init(bd_t *bd)
 603 {
 604         unsigned long val, i;
 605
 606         printf(DRIVERNAME ": initializing\n");
 607
 608         val = smc911x_reg_read(BYTE_TEST);
 609         if (val != 0x87654321) {
 610                 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
 611                 goto err_out;
 612         }
 613
 614         val = smc911x_reg_read(ID_REV) >> 16;
 615         for (i = 0; chip_ids[i].id != 0; i++) {
 616                 if (chip_ids[i].id == val) break;
 617         }
 618         if (!chip_ids[i].id) {
 619                 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
 620                 goto err_out;
 621         }
 622
 623         printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
 624
 625         smc911x_reset();
 626
 627         /* Configure the PHY, initialize the link state */
 628         smc911x_phy_configure();
 629
 630         if (smx911x_handle_mac_address(bd))
 631                 goto err_out;
 632
 633         /* Turn on Tx + Rx */
 634         smc911x_enable();
 635
 636         return 0;
 637
 638 err_out:
 639         return -1;
 640 }
 641
 642 int eth_send(volatile void *packet, int length)
 643 {
 644         u32 *data = (u32*)packet;
 645         u32 tmplen;
 646         u32 status;
 647
 648         smc911x_reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
 649         smc911x_reg_write(TX_DATA_FIFO, length);
 650
 651         tmplen = (length + 3) / 4;
 652
 653         while (tmplen--)
 654                 pkt_data_push(TX_DATA_FIFO, *data++);
 655
 656         /* wait for transmission */
 657         while (!((smc911x_reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
 658
 659         /* get status. Ignore 'no carrier' error, it has no meaning for
 660          * full duplex operation
 661          */
 662         status = smc911x_reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL |
 663                 TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
 664
 665         if (!status)
 666                 return 0;
 667
 668         printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
 669                 status & TX_STS_LOC ? "TX_STS_LOC " : "",
 670                 status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
 671                 status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
 672                 status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
 673                 status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
 674
 675         return -1;
 676 }
 677
 678 void eth_halt(void)
 679 {
 680         smc911x_reset();
 681 }
 682
 683 int eth_rx(void)
 684 {
 685         u32 *data = (u32 *)NetRxPackets[0];
 686         u32 pktlen, tmplen;
 687         u32 status;
 688
 689         if ((smc911x_reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
 690                 status = smc911x_reg_read(RX_STATUS_FIFO);
 691                 pktlen = (status & RX_STS_PKT_LEN) >> 16;
 692
 693                 smc911x_reg_write(RX_CFG, 0);
 694
 695                 tmplen = (pktlen + 2+ 3) / 4;
 696                 while (tmplen--)
 697                         *data++ = pkt_data_pull(RX_DATA_FIFO);
 698
 699                 if (status & RX_STS_ES)
 700                         printf(DRIVERNAME
 701                                 ": dropped bad packet. Status: 0x%08x\n",
 702                                 status);
 703                 else
 704                         NetReceive(NetRxPackets[0], pktlen);
 705         }
 706
 707         return 0;
 708 }