cosmetic changes to bcm570x driver
[karo-tx-uboot.git] / drivers / tigon3.c
1 /******************************************************************************/
2 /*                                                                            */
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom         */
4 /* Corporation.                                                               */
5 /* All rights reserved.                                                       */
6 /*                                                                            */
7 /* This program is free software; you can redistribute it and/or modify       */
8 /* it under the terms of the GNU General Public License as published by       */
9 /* the Free Software Foundation, located in the file LICENSE.                 */
10 /*                                                                            */
11 /* History:                                                                   */
12 /******************************************************************************/
13 #include <common.h>
14 #include <asm/types.h>
15 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \
16         defined(CONFIG_TIGON3)
17 #ifdef CONFIG_BMW
18 #include <mpc824x.h>
19 #endif
20 #include <malloc.h>
21 #include <linux/byteorder/big_endian.h>
22 #include "bcm570x_mm.h"
23
24 #define EMBEDDED 1
25 /******************************************************************************/
26 /* Local functions. */
27 /******************************************************************************/
28
29 LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
30 LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
31
32 static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
33                                                  RequestedMediaType,
34                                                  PLM_MEDIA_TYPE pMediaType,
35                                                  PLM_LINE_SPEED pLineSpeed,
36                                                  PLM_DUPLEX_MODE pDuplexMode);
37
38 static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
39
40 __inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
41 __inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
42
43 static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
44                                             LM_REQUESTED_MEDIA_TYPE
45                                             RequestedMediaType);
46 static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
47                                   LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
48 static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
49 STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
50                                     LM_UINT32 LocalPhyAd,
51                                     LM_UINT32 RemotePhyAd);
52 #if INCLUDE_TBI_SUPPORT
53 STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
54 STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);
55 #endif
56 STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
57 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
58                                                  LM_UINT16 Ssid);
59 STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
60                              LM_PHYSICAL_ADDRESS BufferPhy,
61                              LM_UINT32 BufferSize);
62 STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
63 STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
64 STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
65                                     PLM_PACKET pPacket, PT3_SND_BD pSendBd);
66
67 /******************************************************************************/
68 /* External functions. */
69 /******************************************************************************/
70
71 LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);
72
73 /******************************************************************************/
74 /* Description:                                                               */
75 /*                                                                            */
76 /* Return:                                                                    */
77 /******************************************************************************/
78 LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
79 {
80         LM_UINT32 Value32;
81
82 #if PCIX_TARGET_WORKAROUND
83         MM_ACQUIRE_UNDI_LOCK (pDevice);
84 #endif
85         MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
86         MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);
87 #if PCIX_TARGET_WORKAROUND
88         MM_RELEASE_UNDI_LOCK (pDevice);
89 #endif
90
91         return Value32;
92 }                               /* LM_RegRdInd */
93
94 /******************************************************************************/
95 /* Description:                                                               */
96 /*                                                                            */
97 /* Return:                                                                    */
98 /******************************************************************************/
99 LM_VOID
100 LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
101 {
102
103 #if PCIX_TARGET_WORKAROUND
104         MM_ACQUIRE_UNDI_LOCK (pDevice);
105 #endif
106         MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
107         MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);
108 #if PCIX_TARGET_WORKAROUND
109         MM_RELEASE_UNDI_LOCK (pDevice);
110 #endif
111 }                               /* LM_RegWrInd */
112
113 /******************************************************************************/
114 /* Description:                                                               */
115 /*                                                                            */
116 /* Return:                                                                    */
117 /******************************************************************************/
118 LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
119 {
120         LM_UINT32 Value32;
121
122         MM_ACQUIRE_UNDI_LOCK (pDevice);
123 #ifdef BIG_ENDIAN_HOST
124         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
125         Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
126         /*    Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
127 #else
128         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
129         MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
130 #endif
131         MM_RELEASE_UNDI_LOCK (pDevice);
132
133         return Value32;
134 }                               /* LM_MemRdInd */
135
136 /******************************************************************************/
137 /* Description:                                                               */
138 /*                                                                            */
139 /* Return:                                                                    */
140 /******************************************************************************/
141 LM_VOID
142 LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
143 {
144         MM_ACQUIRE_UNDI_LOCK (pDevice);
145 #ifdef BIG_ENDIAN_HOST
146         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
147         REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);
148 #else
149         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
150         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
151 #endif
152         MM_RELEASE_UNDI_LOCK (pDevice);
153 }                               /* LM_MemWrInd */
154
155 /******************************************************************************/
156 /* Description:                                                               */
157 /*                                                                            */
158 /* Return:                                                                    */
159 /******************************************************************************/
160 LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
161 {
162         LM_STATUS Lmstatus;
163         PLM_PACKET pPacket;
164         PT3_RCV_BD pRcvBd;
165         LM_UINT32 StdBdAdded = 0;
166 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
167         LM_UINT32 JumboBdAdded = 0;
168 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
169
170         Lmstatus = LM_STATUS_SUCCESS;
171
172         pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
173         while (pPacket) {
174                 switch (pPacket->u.Rx.RcvProdRing) {
175 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
176                 case T3_JUMBO_RCV_PROD_RING:    /* Jumbo Receive Ring. */
177                         /* Initialize the buffer descriptor. */
178                         pRcvBd =
179                             &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
180                         pRcvBd->Flags =
181                             RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
182                         pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
183
184                         /* Initialize the receive buffer pointer */
185 #if 0                           /* Jimmy, deleted in new */
186                         pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
187                         pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
188 #endif
189                         MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
190
191                         /* The opaque field may point to an offset from a fix addr. */
192                         pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
193                                                       MM_UINT_PTR (pDevice->
194                                                                    pPacketDescBase));
195
196                         /* Update the producer index. */
197                         pDevice->RxJumboProdIdx =
198                             (pDevice->RxJumboProdIdx +
199                              1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
200
201                         JumboBdAdded++;
202                         break;
203 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
204
205                 case T3_STD_RCV_PROD_RING:      /* Standard Receive Ring. */
206                         /* Initialize the buffer descriptor. */
207                         pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
208                         pRcvBd->Flags = RCV_BD_FLAG_END;
209                         pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
210
211                         /* Initialize the receive buffer pointer */
212 #if 0                           /* Jimmy, deleted in new replaced with MM_MapRxDma */
213                         pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
214                         pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
215 #endif
216                         MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
217
218                         /* The opaque field may point to an offset from a fix addr. */
219                         pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
220                                                       MM_UINT_PTR (pDevice->
221                                                                    pPacketDescBase));
222
223                         /* Update the producer index. */
224                         pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
225                             T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
226
227                         StdBdAdded++;
228                         break;
229
230                 case T3_UNKNOWN_RCV_PROD_RING:
231                 default:
232                         Lmstatus = LM_STATUS_FAILURE;
233                         break;
234                 }               /* switch */
235
236                 /* Bail out if there is any error. */
237                 if (Lmstatus != LM_STATUS_SUCCESS) {
238                         break;
239                 }
240
241                 pPacket =
242                     (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
243         }                       /* while */
244
245         wmb ();
246         /* Update the procedure index. */
247         if (StdBdAdded) {
248                 MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
249                            pDevice->RxStdProdIdx);
250         }
251 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
252         if (JumboBdAdded) {
253                 MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
254                            pDevice->RxJumboProdIdx);
255         }
256 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
257
258         return Lmstatus;
259 }                               /* LM_QueueRxPackets */
260
261 /******************************************************************************/
262 /* Description:                                                               */
263 /*                                                                            */
264 /* Return:                                                                    */
265 /******************************************************************************/
266 STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)
267 {
268         LM_UINT32 Value32;
269         LM_UINT32 j;
270
271         /* Intialize clock period and state machine. */
272         Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
273             SEEPROM_ADDR_FSM_RESET;
274         REG_WR (pDevice, Grc.EepromAddr, Value32);
275
276         for (j = 0; j < 100; j++) {
277                 MM_Wait (10);
278         }
279
280         /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
281         Value32 = REG_RD (pDevice, Grc.LocalCtrl);
282         REG_WR (pDevice, Grc.LocalCtrl,
283                 Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
284
285         /* Set the 5701 compatibility mode if we are using EEPROM. */
286         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
287             T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
288                 Value32 = REG_RD (pDevice, Nvram.Config1);
289                 if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
290                         /* Use the new interface to read EEPROM. */
291                         Value32 &= ~FLASH_COMPAT_BYPASS;
292
293                         REG_WR (pDevice, Nvram.Config1, Value32);
294                 }
295         }
296 }                               /* LM_NvRamInit */
297
298 /******************************************************************************/
299 /* Description:                                                               */
300 /*                                                                            */
301 /* Return:                                                                    */
302 /******************************************************************************/
303 STATIC LM_STATUS
304 LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
305 {
306         LM_UINT32 Value32;
307         LM_UINT32 Addr;
308         LM_UINT32 Dev;
309         LM_UINT32 j;
310
311         if (Offset > SEEPROM_CHIP_SIZE) {
312                 return LM_STATUS_FAILURE;
313         }
314
315         Dev = Offset / SEEPROM_CHIP_SIZE;
316         Addr = Offset % SEEPROM_CHIP_SIZE;
317
318         Value32 = REG_RD (pDevice, Grc.EepromAddr);
319         Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
320                      SEEPROM_ADDR_RW_MASK);
321         REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
322                 SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
323                 SEEPROM_ADDR_READ);
324
325         for (j = 0; j < 1000; j++) {
326                 Value32 = REG_RD (pDevice, Grc.EepromAddr);
327                 if (Value32 & SEEPROM_ADDR_COMPLETE) {
328                         break;
329                 }
330                 MM_Wait (10);
331         }
332
333         if (Value32 & SEEPROM_ADDR_COMPLETE) {
334                 Value32 = REG_RD (pDevice, Grc.EepromData);
335                 *pData = Value32;
336
337                 return LM_STATUS_SUCCESS;
338         }
339
340         return LM_STATUS_FAILURE;
341 }                               /* LM_EepromRead */
342
343 /******************************************************************************/
344 /* Description:                                                               */
345 /*                                                                            */
346 /* Return:                                                                    */
347 /******************************************************************************/
348 STATIC LM_STATUS
349 LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
350 {
351         LM_UINT32 Value32;
352         LM_STATUS Status;
353         LM_UINT32 j;
354
355         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
356             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
357                 Status = LM_EepromRead (pDevice, Offset, pData);
358         } else {
359                 /* Determine if we have flash or EEPROM. */
360                 Value32 = REG_RD (pDevice, Nvram.Config1);
361                 if (Value32 & FLASH_INTERFACE_ENABLE) {
362                         if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
363                                 Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
364                                           BUFFERED_FLASH_PAGE_POS) +
365                                     (Offset % BUFFERED_FLASH_PAGE_SIZE);
366                         }
367                 }
368
369                 REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
370                 for (j = 0; j < 1000; j++) {
371                         if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
372                                 break;
373                         }
374                         MM_Wait (20);
375                 }
376                 if (j == 1000) {
377                         return LM_STATUS_FAILURE;
378                 }
379
380                 /* Read from flash or EEPROM with the new 5703/02 interface. */
381                 REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
382
383                 REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
384                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
385
386                 /* Wait for the done bit to clear. */
387                 for (j = 0; j < 500; j++) {
388                         MM_Wait (10);
389
390                         Value32 = REG_RD (pDevice, Nvram.Cmd);
391                         if (!(Value32 & NVRAM_CMD_DONE)) {
392                                 break;
393                         }
394                 }
395
396                 /* Wait for the done bit. */
397                 if (!(Value32 & NVRAM_CMD_DONE)) {
398                         for (j = 0; j < 500; j++) {
399                                 MM_Wait (10);
400
401                                 Value32 = REG_RD (pDevice, Nvram.Cmd);
402                                 if (Value32 & NVRAM_CMD_DONE) {
403                                         MM_Wait (10);
404
405                                         *pData =
406                                             REG_RD (pDevice, Nvram.ReadData);
407
408                                         /* Change the endianess. */
409                                         *pData =
410                                             ((*pData & 0xff) << 24) |
411                                             ((*pData & 0xff00) << 8) |
412                                             ((*pData & 0xff0000) >> 8) |
413                                             ((*pData >> 24) & 0xff);
414
415                                         break;
416                                 }
417                         }
418                 }
419
420                 REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
421                 if (Value32 & NVRAM_CMD_DONE) {
422                         Status = LM_STATUS_SUCCESS;
423                 } else {
424                         Status = LM_STATUS_FAILURE;
425                 }
426         }
427
428         return Status;
429 }                               /* LM_NvramRead */
430
431 STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)
432 {
433         LM_UINT32 Vpd_arr[256 / 4];
434         LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
435         LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
436         LM_UINT32 Value32;
437         unsigned int j;
438
439         /* Read PN from VPD */
440         for (j = 0; j < 256; j += 4, Vpd_dptr++) {
441                 if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
442                     LM_STATUS_SUCCESS) {
443                         printf ("BCM570x: LM_ReadVPD: VPD read failed"
444                                 " (no EEPROM onboard)\n");
445                         return;
446                 }
447                 *Vpd_dptr = cpu_to_le32 (Value32);
448         }
449         for (j = 0; j < 256;) {
450                 unsigned int Vpd_r_len;
451                 unsigned int Vpd_r_end;
452
453                 if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
454                         j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
455                 } else if (Vpd[j] == 0x90) {
456                         Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
457                         j += 3;
458                         Vpd_r_end = Vpd_r_len + j;
459                         while (j < Vpd_r_end) {
460                                 if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
461                                         unsigned int len = Vpd[j + 2];
462
463                                         if (len <= 24) {
464                                                 memcpy (pDevice->PartNo,
465                                                         &Vpd[j + 3], len);
466                                         }
467                                         break;
468                                 } else {
469                                         if (Vpd[j + 2] == 0) {
470                                                 break;
471                                         }
472                                         j = j + Vpd[j + 2];
473                                 }
474                         }
475                         break;
476                 } else {
477                         break;
478                 }
479         }
480 }
481
482 STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)
483 {
484         LM_UINT32 Value32, offset, ver_offset;
485         int i;
486
487         if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
488                 return;
489         if (Value32 != 0xaa559966)
490                 return;
491         if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
492                 return;
493
494         offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
495             ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
496         if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
497                 return;
498         if ((Value32 == 0x0300000e) &&
499             (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
500             && (Value32 == 0)) {
501
502                 if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
503                     LM_STATUS_SUCCESS)
504                         return;
505                 ver_offset = ((ver_offset & 0xff0000) >> 8) |
506                     ((ver_offset >> 24) & 0xff);
507                 for (i = 0; i < 16; i += 4) {
508                         if (LM_NvramRead
509                             (pDevice, offset + ver_offset + i,
510                              &Value32) != LM_STATUS_SUCCESS) {
511                                 return;
512                         }
513                         *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
514                             cpu_to_le32 (Value32);
515                 }
516         } else {
517                 char c;
518
519                 if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
520                         return;
521
522                 i = 0;
523                 c = ((Value32 & 0xff0000) >> 16);
524
525                 if (c < 10) {
526                         pDevice->BootCodeVer[i++] = c + '0';
527                 } else {
528                         pDevice->BootCodeVer[i++] = (c / 10) + '0';
529                         pDevice->BootCodeVer[i++] = (c % 10) + '0';
530                 }
531                 pDevice->BootCodeVer[i++] = '.';
532                 c = (Value32 & 0xff000000) >> 24;
533                 if (c < 10) {
534                         pDevice->BootCodeVer[i++] = c + '0';
535                 } else {
536                         pDevice->BootCodeVer[i++] = (c / 10) + '0';
537                         pDevice->BootCodeVer[i++] = (c % 10) + '0';
538                 }
539                 pDevice->BootCodeVer[i] = 0;
540         }
541 }
542
543 STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)
544 {
545         LM_UINT32 PciState = pDevice->PciState;
546         LM_UINT32 ClockCtrl;
547         char *SpeedStr = "";
548
549         if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
550                 strcpy (pDevice->BusSpeedStr, "32-bit ");
551         } else {
552                 strcpy (pDevice->BusSpeedStr, "64-bit ");
553         }
554         if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
555                 strcat (pDevice->BusSpeedStr, "PCI ");
556                 if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
557                         SpeedStr = "66MHz";
558                 } else {
559                         SpeedStr = "33MHz";
560                 }
561         } else {
562                 strcat (pDevice->BusSpeedStr, "PCIX ");
563                 if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
564                         SpeedStr = "133MHz";
565                 } else {
566                         ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
567                         switch (ClockCtrl) {
568                         case 0:
569                                 SpeedStr = "33MHz";
570                                 break;
571
572                         case 2:
573                                 SpeedStr = "50MHz";
574                                 break;
575
576                         case 4:
577                                 SpeedStr = "66MHz";
578                                 break;
579
580                         case 6:
581                                 SpeedStr = "100MHz";
582                                 break;
583
584                         case 7:
585                                 SpeedStr = "133MHz";
586                                 break;
587                         }
588                 }
589         }
590         strcat (pDevice->BusSpeedStr, SpeedStr);
591 }
592
593 /******************************************************************************/
594 /* Description:                                                               */
595 /*    This routine initializes default parameters and reads the PCI           */
596 /*    configurations.                                                         */
597 /*                                                                            */
598 /* Return:                                                                    */
599 /*    LM_STATUS_SUCCESS                                                       */
600 /******************************************************************************/
601 LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)
602 {
603         PLM_ADAPTER_INFO pAdapterInfo;
604         LM_UINT32 Value32;
605         LM_STATUS Status;
606         LM_UINT32 j;
607         LM_UINT32 EeSigFound;
608         LM_UINT32 EePhyTypeSerdes = 0;
609         LM_UINT32 EePhyLedMode = 0;
610         LM_UINT32 EePhyId = 0;
611
612         /* Get Device Id and Vendor Id */
613         Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
614         if (Status != LM_STATUS_SUCCESS) {
615                 return Status;
616         }
617         pDevice->PciVendorId = (LM_UINT16) Value32;
618         pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
619
620         /* If we are not getting the write adapter, exit. */
621         if ((Value32 != T3_PCI_ID_BCM5700) &&
622             (Value32 != T3_PCI_ID_BCM5701) &&
623             (Value32 != T3_PCI_ID_BCM5702) &&
624             (Value32 != T3_PCI_ID_BCM5702x) &&
625             (Value32 != T3_PCI_ID_BCM5702FE) &&
626             (Value32 != T3_PCI_ID_BCM5703) &&
627             (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
628                 return LM_STATUS_FAILURE;
629         }
630
631         Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
632         if (Status != LM_STATUS_SUCCESS) {
633                 return Status;
634         }
635         pDevice->PciRevId = (LM_UINT8) Value32;
636
637         /* Get IRQ. */
638         Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
639         if (Status != LM_STATUS_SUCCESS) {
640                 return Status;
641         }
642         pDevice->Irq = (LM_UINT8) Value32;
643
644         /* Get interrupt pin. */
645         pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
646
647         /* Get chip revision id. */
648         Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
649         pDevice->ChipRevId = Value32 >> 16;
650
651         /* Get subsystem vendor. */
652         Status =
653             MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
654         if (Status != LM_STATUS_SUCCESS) {
655                 return Status;
656         }
657         pDevice->SubsystemVendorId = (LM_UINT16) Value32;
658
659         /* Get PCI subsystem id. */
660         pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
661
662         /* Get the cache line size. */
663         MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
664         pDevice->CacheLineSize = (LM_UINT8) Value32;
665         pDevice->SavedCacheLineReg = Value32;
666
667         if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
668             pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
669             pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
670                 pDevice->UndiFix = FALSE;
671         }
672 #if !PCIX_TARGET_WORKAROUND
673         pDevice->UndiFix = FALSE;
674 #endif
675         /* Map the memory base to system address space. */
676         if (!pDevice->UndiFix) {
677                 Status = MM_MapMemBase (pDevice);
678                 if (Status != LM_STATUS_SUCCESS) {
679                         return Status;
680                 }
681                 /* Initialize the memory view pointer. */
682                 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
683         }
684 #if PCIX_TARGET_WORKAROUND
685         /* store whether we are in PCI are PCI-X mode */
686         pDevice->EnablePciXFix = FALSE;
687
688         MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
689         if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
690                 /* Enable PCI-X workaround only if we are running on 5700 BX. */
691                 if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
692                         pDevice->EnablePciXFix = TRUE;
693                 }
694         }
695         if (pDevice->UndiFix) {
696                 pDevice->EnablePciXFix = TRUE;
697         }
698 #endif
699         /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
700         /* management register may be clobbered which may cause the */
701         /* BCM5700 to go into D3 state.  While in this state, we will */
702         /* not have memory mapped register access.  As a workaround, we */
703         /* need to restore the device to D0 state. */
704         MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
705         Value32 |= T3_PM_PME_ASSERTED;
706         Value32 &= ~T3_PM_POWER_STATE_MASK;
707         Value32 |= T3_PM_POWER_STATE_D0;
708         MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
709
710         /* read the current PCI command word */
711         MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
712
713         /* Make sure bus-mastering is enabled. */
714         Value32 |= PCI_BUSMASTER_ENABLE;
715
716 #if PCIX_TARGET_WORKAROUND
717         /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
718            are enabled */
719         if (pDevice->EnablePciXFix == TRUE) {
720                 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
721                             PCI_PARITY_ERROR_ENABLE);
722         }
723         if (pDevice->UndiFix) {
724                 Value32 &= ~PCI_MEM_SPACE_ENABLE;
725         }
726 #endif
727
728         if (pDevice->EnableMWI) {
729                 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
730         } else {
731                 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
732         }
733
734         /* Error out if mem-mapping is NOT enabled for PCI systems */
735         if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
736                 return LM_STATUS_FAILURE;
737         }
738
739         /* save the value we are going to write into the PCI command word */
740         pDevice->PciCommandStatusWords = Value32;
741
742         Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
743         if (Status != LM_STATUS_SUCCESS) {
744                 return Status;
745         }
746
747         /* Set power state to D0. */
748         LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
749
750 #ifdef BIG_ENDIAN_PCI
751         pDevice->MiscHostCtrl =
752             MISC_HOST_CTRL_MASK_PCI_INT |
753             MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
754             MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
755             MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
756 #else                           /* No CPU Swap modes for PCI IO */
757
758         /* Setup the mode registers. */
759         pDevice->MiscHostCtrl =
760             MISC_HOST_CTRL_MASK_PCI_INT |
761             MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
762 #ifdef BIG_ENDIAN_HOST
763             MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
764 #endif                          /* BIG_ENDIAN_HOST */
765             MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
766             MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
767 #endif                          /* !BIG_ENDIAN_PCI */
768
769         /* write to PCI misc host ctr first in order to enable indirect accesses */
770         MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
771                           pDevice->MiscHostCtrl);
772
773         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
774
775 #ifdef BIG_ENDIAN_PCI
776         Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
777 #else
778 /* No CPU Swap modes for PCI IO */
779 #ifdef BIG_ENDIAN_HOST
780         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
781             GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
782 #else
783         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
784 #endif
785 #endif                          /* !BIG_ENDIAN_PCI */
786
787         REG_WR (pDevice, Grc.Mode, Value32);
788
789         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
790                 REG_WR (pDevice, Grc.LocalCtrl,
791                         GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
792                         GRC_MISC_LOCAL_CTRL_GPIO_OE1);
793         }
794         MM_Wait (40);
795
796         /* Enable indirect memory access */
797         REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
798
799         if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
800                 REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
801                         T3_PCI_SELECT_ALTERNATE_CLOCK);
802                 REG_WR (pDevice, PciCfg.ClockCtrl,
803                         T3_PCI_SELECT_ALTERNATE_CLOCK);
804                 MM_Wait (40);   /* required delay is 27usec */
805         }
806         REG_WR (pDevice, PciCfg.ClockCtrl, 0);
807         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
808
809 #if PCIX_TARGET_WORKAROUND
810         MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
811         if ((pDevice->EnablePciXFix == FALSE) &&
812             ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
813                 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
814                     pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
815                     pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
816                     pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
817                         __raw_writel (0,
818                                       &(pDevice->pMemView->uIntMem.
819                                         MemBlock32K[0x300]));
820                         __raw_writel (0,
821                                       &(pDevice->pMemView->uIntMem.
822                                         MemBlock32K[0x301]));
823                         __raw_writel (0xffffffff,
824                                       &(pDevice->pMemView->uIntMem.
825                                         MemBlock32K[0x301]));
826                         if (__raw_readl
827                             (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
828                         {
829                                 pDevice->EnablePciXFix = TRUE;
830                         }
831                 }
832         }
833 #endif
834 #if 1
835         /*
836          *  This code was at the beginning of else block below, but that's
837          *  a bug if node address in shared memory.
838          */
839         MM_Wait (50);
840         LM_NvramInit (pDevice);
841 #endif
842         /* Get the node address.  First try to get in from the shared memory. */
843         /* If the signature is not present, then get it from the NVRAM. */
844         Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
845         if ((Value32 >> 16) == 0x484b) {
846
847                 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
848                 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
849
850                 Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
851
852                 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
853                 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
854                 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
855                 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
856
857                 Status = LM_STATUS_SUCCESS;
858         } else {
859                 Status = LM_NvramRead (pDevice, 0x7c, &Value32);
860                 if (Status == LM_STATUS_SUCCESS) {
861                         pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
862                         pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
863
864                         Status = LM_NvramRead (pDevice, 0x80, &Value32);
865
866                         pDevice->NodeAddress[2] = (LM_UINT8) Value32;
867                         pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
868                         pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
869                         pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
870                 }
871         }
872
873         /* Assign a default address. */
874         if (Status != LM_STATUS_SUCCESS) {
875 #ifndef EMBEDDED
876                 printk (KERN_ERR
877                         "Cannot get MAC addr from NVRAM. Using default.\n");
878 #endif
879                 pDevice->NodeAddress[0] = 0x00;
880                 pDevice->NodeAddress[1] = 0x10;
881                 pDevice->NodeAddress[2] = 0x18;
882                 pDevice->NodeAddress[3] = 0x68;
883                 pDevice->NodeAddress[4] = 0x61;
884                 pDevice->NodeAddress[5] = 0x76;
885         }
886
887         pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
888         pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
889         pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
890         pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
891         pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
892         pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
893
894         /* Initialize the default values. */
895         pDevice->NoTxPseudoHdrChksum = FALSE;
896         pDevice->NoRxPseudoHdrChksum = FALSE;
897         pDevice->NicSendBd = FALSE;
898         pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
899         pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
900         pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
901         pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
902         pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
903         pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
904         pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
905         pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
906         pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
907         pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
908         pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
909         pDevice->EnableMWI = FALSE;
910         pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
911         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
912         pDevice->DisableAutoNeg = FALSE;
913         pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
914         pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
915         pDevice->LedMode = LED_MODE_AUTO;
916         pDevice->ResetPhyOnInit = TRUE;
917         pDevice->DelayPciGrant = TRUE;
918         pDevice->UseTaggedStatus = FALSE;
919         pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
920
921         pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
922         pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
923         pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
924
925         pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
926         pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
927         pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
928         pDevice->EnableTbi = FALSE;
929 #if INCLUDE_TBI_SUPPORT
930         pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
931 #endif
932
933         switch (T3_ASIC_REV (pDevice->ChipRevId)) {
934         case T3_ASIC_REV_5704:
935                 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
936                 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
937                 break;
938         default:
939                 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
940                 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
941                 break;
942         }
943
944         pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
945         pDevice->QueueRxPackets = TRUE;
946
947         pDevice->EnableWireSpeed = TRUE;
948
949 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
950         pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
951 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
952
953         /* Make this is a known adapter. */
954         pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
955                                                 pDevice->SubsystemId);
956
957         pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
958         if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
959             pDevice->BondId != GRC_MISC_BD_ID_5701 &&
960             pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
961             pDevice->BondId != GRC_MISC_BD_ID_5703 &&
962             pDevice->BondId != GRC_MISC_BD_ID_5703S &&
963             pDevice->BondId != GRC_MISC_BD_ID_5704 &&
964             pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
965                 return LM_STATUS_UNKNOWN_ADAPTER;
966         }
967
968         pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
969         if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
970             (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
971                 pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
972                 pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
973         }
974
975         /* Get Eeprom info. */
976         Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
977         if (Value32 == T3_NIC_DATA_SIG) {
978                 EeSigFound = TRUE;
979                 Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
980
981                 /* Determine PHY type. */
982                 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
983                 case T3_NIC_CFG_PHY_TYPE_COPPER:
984                         EePhyTypeSerdes = FALSE;
985                         break;
986
987                 case T3_NIC_CFG_PHY_TYPE_FIBER:
988                         EePhyTypeSerdes = TRUE;
989                         break;
990
991                 default:
992                         EePhyTypeSerdes = FALSE;
993                         break;
994                 }
995
996                 /* Determine PHY led mode. */
997                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
998                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
999                         switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
1000                         case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
1001                                 EePhyLedMode = LED_MODE_THREE_LINK;
1002                                 break;
1003
1004                         case T3_NIC_CFG_LED_MODE_LINK_SPEED:
1005                                 EePhyLedMode = LED_MODE_LINK10;
1006                                 break;
1007
1008                         default:
1009                                 EePhyLedMode = LED_MODE_AUTO;
1010                                 break;
1011                         }
1012                 } else {
1013                         switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
1014                         case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
1015                                 EePhyLedMode = LED_MODE_OPEN_DRAIN;
1016                                 break;
1017
1018                         case T3_NIC_CFG_LED_MODE_OUTPUT:
1019                                 EePhyLedMode = LED_MODE_OUTPUT;
1020                                 break;
1021
1022                         default:
1023                                 EePhyLedMode = LED_MODE_AUTO;
1024                                 break;
1025                         }
1026                 }
1027                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
1028                     pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
1029                         /* Enable EEPROM write protection. */
1030                         if (Value32 & T3_NIC_EEPROM_WP) {
1031                                 pDevice->EepromWp = TRUE;
1032                         }
1033                 }
1034
1035                 /* Get the PHY Id. */
1036                 Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
1037                 if (Value32) {
1038                         EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
1039                                    PHY_ID1_OUI_MASK) << 10;
1040
1041                         Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
1042
1043                         EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
1044                             (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
1045                                                               PHY_ID2_REV_MASK);
1046                 } else {
1047                         EePhyId = 0;
1048                 }
1049         } else {
1050                 EeSigFound = FALSE;
1051         }
1052
1053         /* Set the PHY address. */
1054         pDevice->PhyAddr = PHY_DEVICE_ID;
1055
1056         /* Disable auto polling. */
1057         pDevice->MiMode = 0xc0000;
1058         REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
1059         MM_Wait (40);
1060
1061         /* Get the PHY id. */
1062         LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
1063         pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
1064
1065         LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
1066         pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
1067             (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
1068
1069         /* Set the EnableTbi flag to false if we have a copper PHY. */
1070         switch (pDevice->PhyId & PHY_ID_MASK) {
1071         case PHY_BCM5400_PHY_ID:
1072                 pDevice->EnableTbi = FALSE;
1073                 break;
1074
1075         case PHY_BCM5401_PHY_ID:
1076                 pDevice->EnableTbi = FALSE;
1077                 break;
1078
1079         case PHY_BCM5411_PHY_ID:
1080                 pDevice->EnableTbi = FALSE;
1081                 break;
1082
1083         case PHY_BCM5701_PHY_ID:
1084                 pDevice->EnableTbi = FALSE;
1085                 break;
1086
1087         case PHY_BCM5703_PHY_ID:
1088                 pDevice->EnableTbi = FALSE;
1089                 break;
1090
1091         case PHY_BCM5704_PHY_ID:
1092                 pDevice->EnableTbi = FALSE;
1093                 break;
1094
1095         case PHY_BCM8002_PHY_ID:
1096                 pDevice->EnableTbi = TRUE;
1097                 break;
1098
1099         default:
1100
1101                 if (pAdapterInfo) {
1102                         pDevice->PhyId = pAdapterInfo->PhyId;
1103                         pDevice->EnableTbi = pAdapterInfo->Serdes;
1104                 } else if (EeSigFound) {
1105                         pDevice->PhyId = EePhyId;
1106                         pDevice->EnableTbi = EePhyTypeSerdes;
1107                 }
1108                 break;
1109         }
1110
1111         /* Bail out if we don't know the copper PHY id. */
1112         if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
1113                 return LM_STATUS_FAILURE;
1114         }
1115
1116         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
1117                 if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
1118                         pDevice->SavedCacheLineReg &= 0xffff00ff;
1119                         pDevice->SavedCacheLineReg |= 0x4000;
1120                 }
1121         }
1122         /* Change driver parameters. */
1123         Status = MM_GetConfig (pDevice);
1124         if (Status != LM_STATUS_SUCCESS) {
1125                 return Status;
1126         }
1127 #if INCLUDE_5701_AX_FIX
1128         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1129             pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
1130                 pDevice->ResetPhyOnInit = TRUE;
1131         }
1132 #endif
1133
1134         /* Save the current phy link status. */
1135         if (!pDevice->EnableTbi) {
1136                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
1137                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
1138
1139                 /* If we don't have link reset the PHY. */
1140                 if (!(Value32 & PHY_STATUS_LINK_PASS)
1141                     || pDevice->ResetPhyOnInit) {
1142
1143                         LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
1144
1145                         for (j = 0; j < 100; j++) {
1146                                 MM_Wait (10);
1147
1148                                 LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
1149                                 if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
1150                                         MM_Wait (40);
1151                                         break;
1152                                 }
1153                         }
1154
1155 #if INCLUDE_5701_AX_FIX
1156                         /* 5701_AX_BX bug:  only advertises 10mb speed. */
1157                         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1158                             pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
1159
1160                                 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
1161                                     PHY_AN_AD_10BASET_HALF |
1162                                     PHY_AN_AD_10BASET_FULL |
1163                                     PHY_AN_AD_100BASETX_FULL |
1164                                     PHY_AN_AD_100BASETX_HALF;
1165                                 Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
1166                                 LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
1167                                 pDevice->advertising = Value32;
1168
1169                                 Value32 = BCM540X_AN_AD_1000BASET_HALF |
1170                                     BCM540X_AN_AD_1000BASET_FULL |
1171                                     BCM540X_CONFIG_AS_MASTER |
1172                                     BCM540X_ENABLE_CONFIG_AS_MASTER;
1173                                 LM_WritePhy (pDevice,
1174                                              BCM540X_1000BASET_CTRL_REG,
1175                                              Value32);
1176                                 pDevice->advertising1000 = Value32;
1177
1178                                 LM_WritePhy (pDevice, PHY_CTRL_REG,
1179                                              PHY_CTRL_AUTO_NEG_ENABLE |
1180                                              PHY_CTRL_RESTART_AUTO_NEG);
1181                         }
1182 #endif
1183                         if (T3_ASIC_REV (pDevice->ChipRevId) ==
1184                             T3_ASIC_REV_5703) {
1185                                 LM_WritePhy (pDevice, 0x18, 0x0c00);
1186                                 LM_WritePhy (pDevice, 0x17, 0x201f);
1187                                 LM_WritePhy (pDevice, 0x15, 0x2aaa);
1188                         }
1189                         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
1190                                 LM_WritePhy (pDevice, 0x1c, 0x8d68);
1191                                 LM_WritePhy (pDevice, 0x1c, 0x8d68);
1192                         }
1193                         /* Enable Ethernet@WireSpeed. */
1194                         if (pDevice->EnableWireSpeed) {
1195                                 LM_WritePhy (pDevice, 0x18, 0x7007);
1196                                 LM_ReadPhy (pDevice, 0x18, &Value32);
1197                                 LM_WritePhy (pDevice, 0x18,
1198                                              Value32 | BIT_15 | BIT_4);
1199                         }
1200                 }
1201         }
1202
1203         /* Turn off tap power management. */
1204         if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
1205                 LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
1206                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
1207                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
1208                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
1209                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
1210                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
1211                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
1212                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
1213                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
1214                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
1215                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
1216
1217                 MM_Wait (40);
1218         }
1219 #if INCLUDE_TBI_SUPPORT
1220         pDevice->IgnoreTbiLinkChange = FALSE;
1221
1222         if (pDevice->EnableTbi) {
1223                 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
1224                 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
1225                 if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
1226                     pDevice->DisableAutoNeg) {
1227                         pDevice->PollTbiLink = FALSE;
1228                 }
1229         } else {
1230                 pDevice->PollTbiLink = FALSE;
1231         }
1232 #endif                          /* INCLUDE_TBI_SUPPORT */
1233
1234         /* UseTaggedStatus is only valid for 5701 and later. */
1235         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1236                 pDevice->UseTaggedStatus = FALSE;
1237
1238                 pDevice->CoalesceMode = 0;
1239         } else {
1240                 pDevice->CoalesceMode =
1241                     HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
1242                     HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
1243         }
1244
1245         /* Set the status block size. */
1246         if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
1247             T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
1248                 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
1249         }
1250
1251         /* Check the DURING_INT coalescing ticks parameters. */
1252         if (pDevice->UseTaggedStatus) {
1253                 if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1254                         pDevice->RxCoalescingTicksDuringInt =
1255                             DEFAULT_RX_COALESCING_TICKS_DURING_INT;
1256                 }
1257
1258                 if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1259                         pDevice->TxCoalescingTicksDuringInt =
1260                             DEFAULT_TX_COALESCING_TICKS_DURING_INT;
1261                 }
1262
1263                 if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1264                         pDevice->RxMaxCoalescedFramesDuringInt =
1265                             DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
1266                 }
1267
1268                 if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1269                         pDevice->TxMaxCoalescedFramesDuringInt =
1270                             DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
1271                 }
1272         } else {
1273                 if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1274                         pDevice->RxCoalescingTicksDuringInt = 0;
1275                 }
1276
1277                 if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1278                         pDevice->TxCoalescingTicksDuringInt = 0;
1279                 }
1280
1281                 if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1282                         pDevice->RxMaxCoalescedFramesDuringInt = 0;
1283                 }
1284
1285                 if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1286                         pDevice->TxMaxCoalescedFramesDuringInt = 0;
1287                 }
1288         }
1289
1290 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1291         if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
1292                 pDevice->RxJumboDescCnt = 0;
1293                 if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
1294                         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1295                 }
1296         } else {
1297                 pDevice->RxJumboBufferSize =
1298                     (pDevice->RxMtu + 8 /* CRC + VLAN */  +
1299                      COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
1300
1301                 if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
1302                         pDevice->RxJumboBufferSize =
1303                             DEFAULT_JUMBO_RCV_BUFFER_SIZE;
1304                         pDevice->RxMtu =
1305                             pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
1306                 }
1307                 pDevice->TxMtu = pDevice->RxMtu;
1308
1309         }
1310 #else
1311         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1312 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1313
1314         pDevice->RxPacketDescCnt =
1315 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1316             pDevice->RxJumboDescCnt +
1317 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1318             pDevice->RxStdDescCnt;
1319
1320         if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
1321                 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1322         }
1323
1324         if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
1325                 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
1326         }
1327
1328         /* Configure the proper ways to get link change interrupt. */
1329         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
1330                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1331                         pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
1332                 } else {
1333                         pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
1334                 }
1335         } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
1336                 /* Auto-polling does not work on 5700_AX and 5700_BX. */
1337                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1338                         pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
1339                 }
1340         }
1341
1342         /* Determine the method to get link change status. */
1343         if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
1344                 /* The link status bit in the status block does not work on 5700_AX */
1345                 /* and 5700_BX chips. */
1346                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1347                         pDevice->LinkChngMode =
1348                             T3_LINK_CHNG_MODE_USE_STATUS_REG;
1349                 } else {
1350                         pDevice->LinkChngMode =
1351                             T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
1352                 }
1353         }
1354
1355         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
1356             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1357                 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
1358         }
1359
1360         /* Configure PHY led mode. */
1361         if (pDevice->LedMode == LED_MODE_AUTO) {
1362                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1363                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
1364                         if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
1365                                 pDevice->LedMode = LED_MODE_LINK10;
1366                         } else {
1367                                 pDevice->LedMode = LED_MODE_THREE_LINK;
1368
1369                                 if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
1370                                         pDevice->LedMode = EePhyLedMode;
1371                                 }
1372                         }
1373
1374                         /* bug? 5701 in LINK10 mode does not seem to work when */
1375                         /* PhyIntMode is LINK_READY. */
1376                         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
1377                             &&
1378 #if INCLUDE_TBI_SUPPORT
1379                             pDevice->EnableTbi == FALSE &&
1380 #endif
1381                             pDevice->LedMode == LED_MODE_LINK10) {
1382                                 pDevice->PhyIntMode =
1383                                     T3_PHY_INT_MODE_MI_INTERRUPT;
1384                                 pDevice->LinkChngMode =
1385                                     T3_LINK_CHNG_MODE_USE_STATUS_REG;
1386                         }
1387
1388                         if (pDevice->EnableTbi) {
1389                                 pDevice->LedMode = LED_MODE_THREE_LINK;
1390                         }
1391                 } else {
1392                         if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
1393                                 pDevice->LedMode = EePhyLedMode;
1394                         } else {
1395                                 pDevice->LedMode = LED_MODE_OPEN_DRAIN;
1396                         }
1397                 }
1398         }
1399
1400         /* Enable OneDmaAtOnce. */
1401         if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
1402                 pDevice->OneDmaAtOnce = FALSE;
1403         }
1404
1405         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1406             pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1407             pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
1408             pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
1409                 pDevice->WolSpeed = WOL_SPEED_10MB;
1410         } else {
1411                 pDevice->WolSpeed = WOL_SPEED_100MB;
1412         }
1413
1414         /* Offloadings. */
1415         pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
1416
1417         /* Turn off task offloading on Ax. */
1418         if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
1419                 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
1420                                              LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
1421         }
1422         pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
1423         LM_ReadVPD (pDevice);
1424         LM_ReadBootCodeVersion (pDevice);
1425         LM_GetBusSpeed (pDevice);
1426
1427         return LM_STATUS_SUCCESS;
1428 }                               /* LM_GetAdapterInfo */
1429
1430 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)
1431 {
1432         static LM_ADAPTER_INFO AdapterArr[] = {
1433                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
1434                  PHY_BCM5401_PHY_ID, 0},
1435                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
1436                  PHY_BCM5701_PHY_ID, 0},
1437                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
1438                  PHY_BCM8002_PHY_ID, 1},
1439                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
1440                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
1441                  PHY_BCM5701_PHY_ID, 0},
1442                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
1443                  PHY_BCM5701_PHY_ID, 0},
1444                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
1445                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
1446                  PHY_BCM5701_PHY_ID, 0},
1447                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
1448                  PHY_BCM5701_PHY_ID, 0},
1449                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
1450                  PHY_BCM5701_PHY_ID, 0},
1451                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
1452                  PHY_BCM5701_PHY_ID, 0},
1453
1454                 {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
1455                 {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
1456                 {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
1457                 {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
1458                 {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
1459
1460                 {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
1461                 {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
1462                 {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
1463                 {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
1464
1465                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
1466                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
1467                  0},
1468                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
1469                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
1470                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
1471                  0},
1472
1473         };
1474         LM_UINT32 j;
1475
1476         for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
1477                 if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
1478                         return &AdapterArr[j];
1479                 }
1480         }
1481
1482         return NULL;
1483 }
1484
1485 /******************************************************************************/
1486 /* Description:                                                               */
1487 /*    This routine sets up receive/transmit buffer descriptions queues.       */
1488 /*                                                                            */
1489 /* Return:                                                                    */
1490 /*    LM_STATUS_SUCCESS                                                       */
1491 /******************************************************************************/
1492 LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)
1493 {
1494         LM_PHYSICAL_ADDRESS MemPhy;
1495         PLM_UINT8 pMemVirt;
1496         PLM_PACKET pPacket;
1497         LM_STATUS Status;
1498         LM_UINT32 Size;
1499         LM_UINT32 j;
1500
1501         /* Set power state to D0. */
1502         LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
1503
1504         /* Intialize the queues. */
1505         QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
1506                       MAX_RX_PACKET_DESC_COUNT);
1507         QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
1508                       MAX_RX_PACKET_DESC_COUNT);
1509
1510         QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
1511                       MAX_TX_PACKET_DESC_COUNT);
1512         QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
1513                       MAX_TX_PACKET_DESC_COUNT);
1514         QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
1515                       MAX_TX_PACKET_DESC_COUNT);
1516
1517         /* Allocate shared memory for: status block, the buffers for receive */
1518         /* rings -- standard, mini, jumbo, and return rings. */
1519         Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
1520             T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
1521 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1522             T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
1523 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1524             T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1525
1526         /* Memory for host based Send BD. */
1527         if (pDevice->NicSendBd == FALSE) {
1528                 Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
1529         }
1530
1531         /* Allocate the memory block. */
1532         Status =
1533             MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
1534                                      &MemPhy, FALSE);
1535         if (Status != LM_STATUS_SUCCESS) {
1536                 return Status;
1537         }
1538
1539         /* Program DMA Read/Write */
1540         if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
1541                 pDevice->DmaReadWriteCtrl = 0x763f000f;
1542         } else {
1543                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
1544                         pDevice->DmaReadWriteCtrl = 0x761f0000;
1545                 } else {
1546                         pDevice->DmaReadWriteCtrl = 0x761b000f;
1547                 }
1548                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
1549                     pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
1550                         pDevice->OneDmaAtOnce = TRUE;
1551                 }
1552         }
1553         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
1554                 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
1555         }
1556
1557         if (pDevice->OneDmaAtOnce) {
1558                 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
1559         }
1560         REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
1561
1562         if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
1563                 return LM_STATUS_FAILURE;
1564         }
1565
1566         /* Status block. */
1567         pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
1568         pDevice->StatusBlkPhy = MemPhy;
1569         pMemVirt += T3_STATUS_BLOCK_SIZE;
1570         LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);
1571
1572         /* Statistics block. */
1573         pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
1574         pDevice->StatsBlkPhy = MemPhy;
1575         pMemVirt += sizeof (T3_STATS_BLOCK);
1576         LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));
1577
1578         /* Receive standard BD buffer. */
1579         pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
1580         pDevice->RxStdBdPhy = MemPhy;
1581
1582         pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1583         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1584                                  T3_STD_RCV_RCB_ENTRY_COUNT *
1585                                  sizeof (T3_RCV_BD));
1586
1587 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1588         /* Receive jumbo BD buffer. */
1589         pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
1590         pDevice->RxJumboBdPhy = MemPhy;
1591
1592         pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1593         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1594                                  T3_JUMBO_RCV_RCB_ENTRY_COUNT *
1595                                  sizeof (T3_RCV_BD));
1596 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1597
1598         /* Receive return BD buffer. */
1599         pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
1600         pDevice->RcvRetBdPhy = MemPhy;
1601
1602         pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1603         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1604                                  T3_RCV_RETURN_RCB_ENTRY_COUNT *
1605                                  sizeof (T3_RCV_BD));
1606
1607         /* Set up Send BD. */
1608         if (pDevice->NicSendBd == FALSE) {
1609                 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
1610                 pDevice->SendBdPhy = MemPhy;
1611
1612                 pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
1613                 LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1614                                          sizeof (T3_SND_BD) *
1615                                          T3_SEND_RCB_ENTRY_COUNT);
1616         } else {
1617                 pDevice->pSendBdVirt = (PT3_SND_BD)
1618                     pDevice->pMemView->uIntMem.First32k.BufferDesc;
1619                 pDevice->SendBdPhy.High = 0;
1620                 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
1621         }
1622
1623         /* Allocate memory for packet descriptors. */
1624         Size = (pDevice->RxPacketDescCnt +
1625                 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
1626         Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
1627         if (Status != LM_STATUS_SUCCESS) {
1628                 return Status;
1629         }
1630         pDevice->pPacketDescBase = (PLM_VOID) pPacket;
1631
1632         /* Create transmit packet descriptors from the memory block and add them */
1633         /* to the TxPacketFreeQ for each send ring. */
1634         for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
1635                 /* Ring index. */
1636                 pPacket->Flags = 0;
1637
1638                 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
1639                 QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
1640
1641                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1642                 /* is the total size of the packet descriptor including the */
1643                 /* os-specific extensions in the UM_PACKET structure. */
1644                 pPacket =
1645                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1646         }                       /* for(j.. */
1647
1648         /* Create receive packet descriptors from the memory block and add them */
1649         /* to the RxPacketFreeQ.  Create the Standard packet descriptors. */
1650         for (j = 0; j < pDevice->RxStdDescCnt; j++) {
1651                 /* Receive producer ring. */
1652                 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
1653
1654                 /* Receive buffer size. */
1655                 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
1656
1657                 /* Add the descriptor to RxPacketFreeQ. */
1658                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
1659
1660                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1661                 /* is the total size of the packet descriptor including the */
1662                 /* os-specific extensions in the UM_PACKET structure. */
1663                 pPacket =
1664                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1665         }                       /* for */
1666
1667 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1668         /* Create the Jumbo packet descriptors. */
1669         for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
1670                 /* Receive producer ring. */
1671                 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
1672
1673                 /* Receive buffer size. */
1674                 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
1675
1676                 /* Add the descriptor to RxPacketFreeQ. */
1677                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
1678
1679                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1680                 /* is the total size of the packet descriptor including the */
1681                 /* os-specific extensions in the UM_PACKET structure. */
1682                 pPacket =
1683                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1684         }                       /* for */
1685 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1686
1687         /* Initialize the rest of the packet descriptors. */
1688         Status = MM_InitializeUmPackets (pDevice);
1689         if (Status != LM_STATUS_SUCCESS) {
1690                 return Status;
1691         }
1692
1693         /* if */
1694         /* Default receive mask. */
1695         pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
1696             LM_ACCEPT_UNICAST;
1697
1698         /* Make sure we are in the first 32k memory window or NicSendBd. */
1699         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
1700
1701         /* Initialize the hardware. */
1702         Status = LM_ResetAdapter (pDevice);
1703         if (Status != LM_STATUS_SUCCESS) {
1704                 return Status;
1705         }
1706
1707         /* We are done with initialization. */
1708         pDevice->InitDone = TRUE;
1709
1710         return LM_STATUS_SUCCESS;
1711 }                               /* LM_InitializeAdapter */
1712
1713 /******************************************************************************/
1714 /* Description:                                                               */
1715 /*    This function Enables/Disables a given block.                          */
1716 /*                                                                            */
1717 /* Return:                                                                    */
1718 /*    LM_STATUS_SUCCESS                                                       */
1719 /******************************************************************************/
1720 LM_STATUS
1721 LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)
1722 {
1723         LM_UINT32 j, i, data;
1724         LM_UINT32 MaxWaitCnt;
1725
1726         MaxWaitCnt = 2;
1727         j = 0;
1728
1729         for (i = 0; i < 32; i++) {
1730                 if (!(mask & (1 << i)))
1731                         continue;
1732
1733                 switch (1 << i) {
1734                 case T3_BLOCK_DMA_RD:
1735                         data = REG_RD (pDevice, DmaRead.Mode);
1736                         if (cntrl == LM_DISABLE) {
1737                                 data &= ~DMA_READ_MODE_ENABLE;
1738                                 REG_WR (pDevice, DmaRead.Mode, data);
1739                                 for (j = 0; j < MaxWaitCnt; j++) {
1740                                         if (!
1741                                             (REG_RD (pDevice, DmaRead.Mode) &
1742                                              DMA_READ_MODE_ENABLE))
1743                                                 break;
1744                                         MM_Wait (10);
1745                                 }
1746                         } else
1747                                 REG_WR (pDevice, DmaRead.Mode,
1748                                         data | DMA_READ_MODE_ENABLE);
1749                         break;
1750
1751                 case T3_BLOCK_DMA_COMP:
1752                         data = REG_RD (pDevice, DmaComp.Mode);
1753                         if (cntrl == LM_DISABLE) {
1754                                 data &= ~DMA_COMP_MODE_ENABLE;
1755                                 REG_WR (pDevice, DmaComp.Mode, data);
1756                                 for (j = 0; j < MaxWaitCnt; j++) {
1757                                         if (!
1758                                             (REG_RD (pDevice, DmaComp.Mode) &
1759                                              DMA_COMP_MODE_ENABLE))
1760                                                 break;
1761                                         MM_Wait (10);
1762                                 }
1763                         } else
1764                                 REG_WR (pDevice, DmaComp.Mode,
1765                                         data | DMA_COMP_MODE_ENABLE);
1766                         break;
1767
1768                 case T3_BLOCK_RX_BD_INITIATOR:
1769                         data = REG_RD (pDevice, RcvBdIn.Mode);
1770                         if (cntrl == LM_DISABLE) {
1771                                 data &= ~RCV_BD_IN_MODE_ENABLE;
1772                                 REG_WR (pDevice, RcvBdIn.Mode, data);
1773                                 for (j = 0; j < MaxWaitCnt; j++) {
1774                                         if (!
1775                                             (REG_RD (pDevice, RcvBdIn.Mode) &
1776                                              RCV_BD_IN_MODE_ENABLE))
1777                                                 break;
1778                                         MM_Wait (10);
1779                                 }
1780                         } else
1781                                 REG_WR (pDevice, RcvBdIn.Mode,
1782                                         data | RCV_BD_IN_MODE_ENABLE);
1783                         break;
1784
1785                 case T3_BLOCK_RX_BD_COMP:
1786                         data = REG_RD (pDevice, RcvBdComp.Mode);
1787                         if (cntrl == LM_DISABLE) {
1788                                 data &= ~RCV_BD_COMP_MODE_ENABLE;
1789                                 REG_WR (pDevice, RcvBdComp.Mode, data);
1790                                 for (j = 0; j < MaxWaitCnt; j++) {
1791                                         if (!
1792                                             (REG_RD (pDevice, RcvBdComp.Mode) &
1793                                              RCV_BD_COMP_MODE_ENABLE))
1794                                                 break;
1795                                         MM_Wait (10);
1796                                 }
1797                         } else
1798                                 REG_WR (pDevice, RcvBdComp.Mode,
1799                                         data | RCV_BD_COMP_MODE_ENABLE);
1800                         break;
1801
1802                 case T3_BLOCK_DMA_WR:
1803                         data = REG_RD (pDevice, DmaWrite.Mode);
1804                         if (cntrl == LM_DISABLE) {
1805                                 data &= ~DMA_WRITE_MODE_ENABLE;
1806                                 REG_WR (pDevice, DmaWrite.Mode, data);
1807
1808                                 for (j = 0; j < MaxWaitCnt; j++) {
1809                                         if (!
1810                                             (REG_RD (pDevice, DmaWrite.Mode) &
1811                                              DMA_WRITE_MODE_ENABLE))
1812                                                 break;
1813                                         MM_Wait (10);
1814                                 }
1815                         } else
1816                                 REG_WR (pDevice, DmaWrite.Mode,
1817                                         data | DMA_WRITE_MODE_ENABLE);
1818                         break;
1819
1820                 case T3_BLOCK_MSI_HANDLER:
1821                         data = REG_RD (pDevice, Msi.Mode);
1822                         if (cntrl == LM_DISABLE) {
1823                                 data &= ~MSI_MODE_ENABLE;
1824                                 REG_WR (pDevice, Msi.Mode, data);
1825                                 for (j = 0; j < MaxWaitCnt; j++) {
1826                                         if (!
1827                                             (REG_RD (pDevice, Msi.Mode) &
1828                                              MSI_MODE_ENABLE))
1829                                                 break;
1830                                         MM_Wait (10);
1831                                 }
1832                         } else
1833                                 REG_WR (pDevice, Msi.Mode,
1834                                         data | MSI_MODE_ENABLE);
1835                         break;
1836
1837                 case T3_BLOCK_RX_LIST_PLMT:
1838                         data = REG_RD (pDevice, RcvListPlmt.Mode);
1839                         if (cntrl == LM_DISABLE) {
1840                                 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
1841                                 REG_WR (pDevice, RcvListPlmt.Mode, data);
1842                                 for (j = 0; j < MaxWaitCnt; j++) {
1843                                         if (!
1844                                             (REG_RD (pDevice, RcvListPlmt.Mode)
1845                                              & RCV_LIST_PLMT_MODE_ENABLE))
1846                                                 break;
1847                                         MM_Wait (10);
1848                                 }
1849                         } else
1850                                 REG_WR (pDevice, RcvListPlmt.Mode,
1851                                         data | RCV_LIST_PLMT_MODE_ENABLE);
1852                         break;
1853
1854                 case T3_BLOCK_RX_LIST_SELECTOR:
1855                         data = REG_RD (pDevice, RcvListSel.Mode);
1856                         if (cntrl == LM_DISABLE) {
1857                                 data &= ~RCV_LIST_SEL_MODE_ENABLE;
1858                                 REG_WR (pDevice, RcvListSel.Mode, data);
1859                                 for (j = 0; j < MaxWaitCnt; j++) {
1860                                         if (!
1861                                             (REG_RD (pDevice, RcvListSel.Mode) &
1862                                              RCV_LIST_SEL_MODE_ENABLE))
1863                                                 break;
1864                                         MM_Wait (10);
1865                                 }
1866                         } else
1867                                 REG_WR (pDevice, RcvListSel.Mode,
1868                                         data | RCV_LIST_SEL_MODE_ENABLE);
1869                         break;
1870
1871                 case T3_BLOCK_RX_DATA_INITIATOR:
1872                         data = REG_RD (pDevice, RcvDataBdIn.Mode);
1873                         if (cntrl == LM_DISABLE) {
1874                                 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
1875                                 REG_WR (pDevice, RcvDataBdIn.Mode, data);
1876                                 for (j = 0; j < MaxWaitCnt; j++) {
1877                                         if (!
1878                                             (REG_RD (pDevice, RcvDataBdIn.Mode)
1879                                              & RCV_DATA_BD_IN_MODE_ENABLE))
1880                                                 break;
1881                                         MM_Wait (10);
1882                                 }
1883                         } else
1884                                 REG_WR (pDevice, RcvDataBdIn.Mode,
1885                                         data | RCV_DATA_BD_IN_MODE_ENABLE);
1886                         break;
1887
1888                 case T3_BLOCK_RX_DATA_COMP:
1889                         data = REG_RD (pDevice, RcvDataComp.Mode);
1890                         if (cntrl == LM_DISABLE) {
1891                                 data &= ~RCV_DATA_COMP_MODE_ENABLE;
1892                                 REG_WR (pDevice, RcvDataComp.Mode, data);
1893                                 for (j = 0; j < MaxWaitCnt; j++) {
1894                                         if (!
1895                                             (REG_RD (pDevice, RcvDataBdIn.Mode)
1896                                              & RCV_DATA_COMP_MODE_ENABLE))
1897                                                 break;
1898                                         MM_Wait (10);
1899                                 }
1900                         } else
1901                                 REG_WR (pDevice, RcvDataComp.Mode,
1902                                         data | RCV_DATA_COMP_MODE_ENABLE);
1903                         break;
1904
1905                 case T3_BLOCK_HOST_COALESING:
1906                         data = REG_RD (pDevice, HostCoalesce.Mode);
1907                         if (cntrl == LM_DISABLE) {
1908                                 data &= ~HOST_COALESCE_ENABLE;
1909                                 REG_WR (pDevice, HostCoalesce.Mode, data);
1910                                 for (j = 0; j < MaxWaitCnt; j++) {
1911                                         if (!
1912                                             (REG_RD (pDevice, SndBdIn.Mode) &
1913                                              HOST_COALESCE_ENABLE))
1914                                                 break;
1915                                         MM_Wait (10);
1916                                 }
1917                         } else
1918                                 REG_WR (pDevice, HostCoalesce.Mode,
1919                                         data | HOST_COALESCE_ENABLE);
1920                         break;
1921
1922                 case T3_BLOCK_MAC_RX_ENGINE:
1923                         if (cntrl == LM_DISABLE) {
1924                                 pDevice->RxMode &= ~RX_MODE_ENABLE;
1925                                 REG_WR (pDevice, MacCtrl.RxMode,
1926                                         pDevice->RxMode);
1927                                 for (j = 0; j < MaxWaitCnt; j++) {
1928                                         if (!
1929                                             (REG_RD (pDevice, MacCtrl.RxMode) &
1930                                              RX_MODE_ENABLE)) {
1931                                                 break;
1932                                         }
1933                                         MM_Wait (10);
1934                                 }
1935                         } else {
1936                                 pDevice->RxMode |= RX_MODE_ENABLE;
1937                                 REG_WR (pDevice, MacCtrl.RxMode,
1938                                         pDevice->RxMode);
1939                         }
1940                         break;
1941
1942                 case T3_BLOCK_MBUF_CLUSTER_FREE:
1943                         data = REG_RD (pDevice, MbufClusterFree.Mode);
1944                         if (cntrl == LM_DISABLE) {
1945                                 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
1946                                 REG_WR (pDevice, MbufClusterFree.Mode, data);
1947                                 for (j = 0; j < MaxWaitCnt; j++) {
1948                                         if (!
1949                                             (REG_RD
1950                                              (pDevice,
1951                                               MbufClusterFree.
1952                                               Mode) &
1953                                              MBUF_CLUSTER_FREE_MODE_ENABLE))
1954                                                 break;
1955                                         MM_Wait (10);
1956                                 }
1957                         } else
1958                                 REG_WR (pDevice, MbufClusterFree.Mode,
1959                                         data | MBUF_CLUSTER_FREE_MODE_ENABLE);
1960                         break;
1961
1962                 case T3_BLOCK_SEND_BD_INITIATOR:
1963                         data = REG_RD (pDevice, SndBdIn.Mode);
1964                         if (cntrl == LM_DISABLE) {
1965                                 data &= ~SND_BD_IN_MODE_ENABLE;
1966                                 REG_WR (pDevice, SndBdIn.Mode, data);
1967                                 for (j = 0; j < MaxWaitCnt; j++) {
1968                                         if (!
1969                                             (REG_RD (pDevice, SndBdIn.Mode) &
1970                                              SND_BD_IN_MODE_ENABLE))
1971                                                 break;
1972                                         MM_Wait (10);
1973                                 }
1974                         } else
1975                                 REG_WR (pDevice, SndBdIn.Mode,
1976                                         data | SND_BD_IN_MODE_ENABLE);
1977                         break;
1978
1979                 case T3_BLOCK_SEND_BD_COMP:
1980                         data = REG_RD (pDevice, SndBdComp.Mode);
1981                         if (cntrl == LM_DISABLE) {
1982                                 data &= ~SND_BD_COMP_MODE_ENABLE;
1983                                 REG_WR (pDevice, SndBdComp.Mode, data);
1984                                 for (j = 0; j < MaxWaitCnt; j++) {
1985                                         if (!
1986                                             (REG_RD (pDevice, SndBdComp.Mode) &
1987                                              SND_BD_COMP_MODE_ENABLE))
1988                                                 break;
1989                                         MM_Wait (10);
1990                                 }
1991                         } else
1992                                 REG_WR (pDevice, SndBdComp.Mode,
1993                                         data | SND_BD_COMP_MODE_ENABLE);
1994                         break;
1995
1996                 case T3_BLOCK_SEND_BD_SELECTOR:
1997                         data = REG_RD (pDevice, SndBdSel.Mode);
1998                         if (cntrl == LM_DISABLE) {
1999                                 data &= ~SND_BD_SEL_MODE_ENABLE;
2000                                 REG_WR (pDevice, SndBdSel.Mode, data);
2001                                 for (j = 0; j < MaxWaitCnt; j++) {
2002                                         if (!
2003                                             (REG_RD (pDevice, SndBdSel.Mode) &
2004                                              SND_BD_SEL_MODE_ENABLE))
2005                                                 break;
2006                                         MM_Wait (10);
2007                                 }
2008                         } else
2009                                 REG_WR (pDevice, SndBdSel.Mode,
2010                                         data | SND_BD_SEL_MODE_ENABLE);
2011                         break;
2012
2013                 case T3_BLOCK_SEND_DATA_INITIATOR:
2014                         data = REG_RD (pDevice, SndDataIn.Mode);
2015                         if (cntrl == LM_DISABLE) {
2016                                 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
2017                                 REG_WR (pDevice, SndDataIn.Mode, data);
2018                                 for (j = 0; j < MaxWaitCnt; j++) {
2019                                         if (!
2020                                             (REG_RD (pDevice, SndDataIn.Mode) &
2021                                              T3_SND_DATA_IN_MODE_ENABLE))
2022                                                 break;
2023                                         MM_Wait (10);
2024                                 }
2025                         } else
2026                                 REG_WR (pDevice, SndDataIn.Mode,
2027                                         data | T3_SND_DATA_IN_MODE_ENABLE);
2028                         break;
2029
2030                 case T3_BLOCK_SEND_DATA_COMP:
2031                         data = REG_RD (pDevice, SndDataComp.Mode);
2032                         if (cntrl == LM_DISABLE) {
2033                                 data &= ~SND_DATA_COMP_MODE_ENABLE;
2034                                 REG_WR (pDevice, SndDataComp.Mode, data);
2035                                 for (j = 0; j < MaxWaitCnt; j++) {
2036                                         if (!
2037                                             (REG_RD (pDevice, SndDataComp.Mode)
2038                                              & SND_DATA_COMP_MODE_ENABLE))
2039                                                 break;
2040                                         MM_Wait (10);
2041                                 }
2042                         } else
2043                                 REG_WR (pDevice, SndDataComp.Mode,
2044                                         data | SND_DATA_COMP_MODE_ENABLE);
2045                         break;
2046
2047                 case T3_BLOCK_MAC_TX_ENGINE:
2048                         if (cntrl == LM_DISABLE) {
2049                                 pDevice->TxMode &= ~TX_MODE_ENABLE;
2050                                 REG_WR (pDevice, MacCtrl.TxMode,
2051                                         pDevice->TxMode);
2052                                 for (j = 0; j < MaxWaitCnt; j++) {
2053                                         if (!
2054                                             (REG_RD (pDevice, MacCtrl.TxMode) &
2055                                              TX_MODE_ENABLE))
2056                                                 break;
2057                                         MM_Wait (10);
2058                                 }
2059                         } else {
2060                                 pDevice->TxMode |= TX_MODE_ENABLE;
2061                                 REG_WR (pDevice, MacCtrl.TxMode,
2062                                         pDevice->TxMode);
2063                         }
2064                         break;
2065
2066                 case T3_BLOCK_MEM_ARBITOR:
2067                         data = REG_RD (pDevice, MemArbiter.Mode);
2068                         if (cntrl == LM_DISABLE) {
2069                                 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
2070                                 REG_WR (pDevice, MemArbiter.Mode, data);
2071                                 for (j = 0; j < MaxWaitCnt; j++) {
2072                                         if (!
2073                                             (REG_RD (pDevice, MemArbiter.Mode) &
2074                                              T3_MEM_ARBITER_MODE_ENABLE))
2075                                                 break;
2076                                         MM_Wait (10);
2077                                 }
2078                         } else
2079                                 REG_WR (pDevice, MemArbiter.Mode,
2080                                         data | T3_MEM_ARBITER_MODE_ENABLE);
2081                         break;
2082
2083                 case T3_BLOCK_MBUF_MANAGER:
2084                         data = REG_RD (pDevice, BufMgr.Mode);
2085                         if (cntrl == LM_DISABLE) {
2086                                 data &= ~BUFMGR_MODE_ENABLE;
2087                                 REG_WR (pDevice, BufMgr.Mode, data);
2088                                 for (j = 0; j < MaxWaitCnt; j++) {
2089                                         if (!
2090                                             (REG_RD (pDevice, BufMgr.Mode) &
2091                                              BUFMGR_MODE_ENABLE))
2092                                                 break;
2093                                         MM_Wait (10);
2094                                 }
2095                         } else
2096                                 REG_WR (pDevice, BufMgr.Mode,
2097                                         data | BUFMGR_MODE_ENABLE);
2098                         break;
2099
2100                 case T3_BLOCK_MAC_GLOBAL:
2101                         if (cntrl == LM_DISABLE) {
2102                                 pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
2103                                                       MAC_MODE_ENABLE_RDE |
2104                                                       MAC_MODE_ENABLE_FHDE);
2105                         } else {
2106                                 pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
2107                                                      MAC_MODE_ENABLE_RDE |
2108                                                      MAC_MODE_ENABLE_FHDE);
2109                         }
2110                         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
2111                         break;
2112
2113                 default:
2114                         return LM_STATUS_FAILURE;
2115                 }               /* switch */
2116
2117                 if (j >= MaxWaitCnt) {
2118                         return LM_STATUS_FAILURE;
2119                 }
2120         }
2121
2122         return LM_STATUS_SUCCESS;
2123 }
2124
2125 /******************************************************************************/
2126 /* Description:                                                               */
2127 /*    This function reinitializes the adapter.                                */
2128 /*                                                                            */
2129 /* Return:                                                                    */
2130 /*    LM_STATUS_SUCCESS                                                       */
2131 /******************************************************************************/
2132 LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
2133 {
2134         LM_UINT32 Value32;
2135         LM_UINT16 Value16;
2136         LM_UINT32 j, k;
2137
2138         /* Disable interrupt. */
2139         LM_DisableInterrupt (pDevice);
2140
2141         /* May get a spurious interrupt */
2142         pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
2143
2144         /* Disable transmit and receive DMA engines.  Abort all pending requests. */
2145         if (pDevice->InitDone) {
2146                 LM_Abort (pDevice);
2147         }
2148
2149         pDevice->ShuttingDown = FALSE;
2150
2151         LM_ResetChip (pDevice);
2152
2153         /* Bug: Athlon fix for B3 silicon only.  This bit does not do anything */
2154         /* in other chip revisions. */
2155         if (pDevice->DelayPciGrant) {
2156                 Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
2157                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
2158         }
2159
2160         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
2161                 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
2162                         Value32 = REG_RD (pDevice, PciCfg.PciState);
2163                         Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
2164                         REG_WR (pDevice, PciCfg.PciState, Value32);
2165                 }
2166         }
2167
2168         /* Enable TaggedStatus mode. */
2169         if (pDevice->UseTaggedStatus) {
2170                 pDevice->MiscHostCtrl |=
2171                     MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
2172         }
2173
2174         /* Restore PCI configuration registers. */
2175         MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
2176                           pDevice->SavedCacheLineReg);
2177         MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
2178                           (pDevice->SubsystemId << 16) | pDevice->
2179                           SubsystemVendorId);
2180
2181         /* Clear the statistics block. */
2182         for (j = 0x0300; j < 0x0b00; j++) {
2183                 MEM_WR_OFFSET (pDevice, j, 0);
2184         }
2185
2186         /* Initialize the statistis Block */
2187         pDevice->pStatusBlkVirt->Status = 0;
2188         pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
2189         pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
2190         pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
2191
2192         for (j = 0; j < 16; j++) {
2193                 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
2194                 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
2195         }
2196
2197         for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
2198                 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
2199                 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
2200         }
2201
2202 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2203         /* Receive jumbo BD buffer. */
2204         for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
2205                 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
2206                 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
2207         }
2208 #endif
2209
2210         REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
2211
2212         /* GRC mode control register. */
2213 #ifdef BIG_ENDIAN_PCI           /* Jimmy, this ifdef block deleted in new code! */
2214         Value32 =
2215             GRC_MODE_WORD_SWAP_DATA |
2216             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2217             GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
2218 #else
2219         /* No CPU Swap modes for PCI IO */
2220         Value32 =
2221 #ifdef BIG_ENDIAN_HOST
2222             GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2223             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2224             GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
2225 #else
2226             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2227             GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
2228 #endif
2229             GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
2230 #endif                          /* !BIG_ENDIAN_PCI */
2231
2232         /* Configure send BD mode. */
2233         if (pDevice->NicSendBd == FALSE) {
2234                 Value32 |= GRC_MODE_HOST_SEND_BDS;
2235         } else {
2236                 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
2237         }
2238
2239         /* Configure pseudo checksum mode. */
2240         if (pDevice->NoTxPseudoHdrChksum) {
2241                 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
2242         }
2243
2244         if (pDevice->NoRxPseudoHdrChksum) {
2245                 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
2246         }
2247
2248         REG_WR (pDevice, Grc.Mode, Value32);
2249
2250         /* Setup the timer prescalar register. */
2251         REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
2252
2253         /* Set up the MBUF pool base address and size. */
2254         REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
2255         REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
2256
2257         /* Set up the DMA descriptor pool base address and size. */
2258         REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
2259         REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
2260
2261         /* Configure MBUF and Threshold watermarks */
2262         /* Configure the DMA read MBUF low water mark. */
2263         if (pDevice->DmaMbufLowMark) {
2264                 REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2265                         pDevice->DmaMbufLowMark);
2266         } else {
2267                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2268                         REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2269                                 T3_DEF_DMA_MBUF_LOW_WMARK);
2270                 } else {
2271                         REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2272                                 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
2273                 }
2274         }
2275
2276         /* Configure the MAC Rx MBUF low water mark. */
2277         if (pDevice->RxMacMbufLowMark) {
2278                 REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2279                         pDevice->RxMacMbufLowMark);
2280         } else {
2281                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2282                         REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2283                                 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
2284                 } else {
2285                         REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2286                                 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
2287                 }
2288         }
2289
2290         /* Configure the MBUF high water mark. */
2291         if (pDevice->MbufHighMark) {
2292                 REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2293                         pDevice->MbufHighMark);
2294         } else {
2295                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2296                         REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2297                                 T3_DEF_MBUF_HIGH_WMARK);
2298                 } else {
2299                         REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2300                                 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
2301                 }
2302         }
2303
2304         REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
2305         REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
2306
2307         /* Enable buffer manager. */
2308         REG_WR (pDevice, BufMgr.Mode,
2309                 BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
2310
2311         for (j = 0; j < 2000; j++) {
2312                 if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
2313                         break;
2314                 MM_Wait (10);
2315         }
2316
2317         if (j >= 2000) {
2318                 return LM_STATUS_FAILURE;
2319         }
2320
2321         /* Enable the FTQs. */
2322         REG_WR (pDevice, Ftq.Reset, 0xffffffff);
2323         REG_WR (pDevice, Ftq.Reset, 0);
2324
2325         /* Wait until FTQ is ready */
2326         for (j = 0; j < 2000; j++) {
2327                 if (REG_RD (pDevice, Ftq.Reset) == 0)
2328                         break;
2329                 MM_Wait (10);
2330         }
2331
2332         if (j >= 2000) {
2333                 return LM_STATUS_FAILURE;
2334         }
2335
2336         /* Initialize the Standard Receive RCB. */
2337         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
2338                 pDevice->RxStdBdPhy.High);
2339         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
2340                 pDevice->RxStdBdPhy.Low);
2341         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
2342                 MAX_STD_RCV_BUFFER_SIZE << 16);
2343
2344         /* Initialize the Jumbo Receive RCB. */
2345         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
2346                 T3_RCB_FLAG_RING_DISABLED);
2347 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2348         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
2349                 pDevice->RxJumboBdPhy.High);
2350         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
2351                 pDevice->RxJumboBdPhy.Low);
2352
2353         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
2354
2355 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2356
2357         /* Initialize the Mini Receive RCB. */
2358         REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
2359                 T3_RCB_FLAG_RING_DISABLED);
2360
2361         {
2362                 REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
2363                         (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
2364                 REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
2365                         (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
2366         }
2367
2368         /* Receive BD Ring replenish threshold. */
2369         REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
2370 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2371         REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
2372                 pDevice->RxJumboDescCnt / 8);
2373 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2374
2375         /* Disable all the unused rings. */
2376         for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
2377                 MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
2378                         T3_RCB_FLAG_RING_DISABLED);
2379         }                       /* for */
2380
2381         /* Initialize the indices. */
2382         pDevice->SendProdIdx = 0;
2383         pDevice->SendConIdx = 0;
2384
2385         MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
2386         MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
2387
2388         /* Set up host or NIC based send RCB. */
2389         if (pDevice->NicSendBd == FALSE) {
2390                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
2391                         pDevice->SendBdPhy.High);
2392                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
2393                         pDevice->SendBdPhy.Low);
2394
2395                 /* Set up the NIC ring address in the RCB. */
2396                 MEM_WR (pDevice, SendRcb[0].NicRingAddr,
2397                         T3_NIC_SND_BUFFER_DESC_ADDR);
2398
2399                 /* Setup the RCB. */
2400                 MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
2401                         T3_SEND_RCB_ENTRY_COUNT << 16);
2402
2403                 for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
2404                         pDevice->pSendBdVirt[k].HostAddr.High = 0;
2405                         pDevice->pSendBdVirt[k].HostAddr.Low = 0;
2406                 }
2407         } else {
2408                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
2409                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
2410                 MEM_WR (pDevice, SendRcb[0].NicRingAddr,
2411                         pDevice->SendBdPhy.Low);
2412
2413                 for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
2414                         __raw_writel (0,
2415                                       &(pDevice->pSendBdVirt[k].HostAddr.High));
2416                         __raw_writel (0,
2417                                       &(pDevice->pSendBdVirt[k].HostAddr.Low));
2418                         __raw_writel (0,
2419                                       &(pDevice->pSendBdVirt[k].u1.Len_Flags));
2420                         pDevice->ShadowSendBd[k].HostAddr.High = 0;
2421                         pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
2422                 }
2423         }
2424         atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
2425
2426         /* Configure the receive return rings. */
2427         for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
2428                 MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
2429                         T3_RCB_FLAG_RING_DISABLED);
2430         }
2431
2432         pDevice->RcvRetConIdx = 0;
2433
2434         MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
2435                 pDevice->RcvRetBdPhy.High);
2436         MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
2437                 pDevice->RcvRetBdPhy.Low);
2438
2439         /* Set up the NIC ring address in the RCB. */
2440         /* Not very clear from the spec.  I am guessing that for Receive */
2441         /* Return Ring, NicRingAddr is not used. */
2442         MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);
2443
2444         /* Setup the RCB. */
2445         MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
2446                 T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
2447
2448         /* Reinitialize RX ring producer index */
2449         MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
2450         MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
2451         MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
2452
2453 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2454         pDevice->RxJumboProdIdx = 0;
2455         pDevice->RxJumboQueuedCnt = 0;
2456 #endif
2457
2458         /* Reinitialize our copy of the indices. */
2459         pDevice->RxStdProdIdx = 0;
2460         pDevice->RxStdQueuedCnt = 0;
2461
2462 #if T3_JUMBO_RCV_ENTRY_COUNT
2463         pDevice->RxJumboProdIdx = 0;
2464 #endif                          /* T3_JUMBO_RCV_ENTRY_COUNT */
2465
2466         /* Configure the MAC address. */
2467         LM_SetMacAddress (pDevice, pDevice->NodeAddress);
2468
2469         /* Initialize the transmit random backoff seed. */
2470         Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
2471                    pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
2472                    pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
2473             MAC_TX_BACKOFF_SEED_MASK;
2474         REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
2475
2476         /* Receive MTU.  Frames larger than the MTU is marked as oversized. */
2477         REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8);  /* CRC + VLAN. */
2478
2479         /* Configure Time slot/IPG per 802.3 */
2480         REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
2481
2482         /*
2483          * Configure Receive Rules so that packets don't match
2484          * Programmble rule will be queued to Return Ring 1
2485          */
2486         REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
2487
2488         /*
2489          * Configure to have 16 Classes of Services (COS) and one
2490          * queue per class.  Bad frames are queued to RRR#1.
2491          * And frames don't match rules are also queued to COS#1.
2492          */
2493         REG_WR (pDevice, RcvListPlmt.Config, 0x181);
2494
2495         /* Enable Receive Placement Statistics */
2496         REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
2497         REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
2498
2499         /* Enable Send Data Initator Statistics */
2500         REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
2501         REG_WR (pDevice, SndDataIn.StatsCtrl,
2502                 T3_SND_DATA_IN_STATS_CTRL_ENABLE |
2503                 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
2504
2505         /* Disable the host coalescing state machine before configuring it's */
2506         /* parameters. */
2507         REG_WR (pDevice, HostCoalesce.Mode, 0);
2508         for (j = 0; j < 2000; j++) {
2509                 Value32 = REG_RD (pDevice, HostCoalesce.Mode);
2510                 if (!(Value32 & HOST_COALESCE_ENABLE)) {
2511                         break;
2512                 }
2513                 MM_Wait (10);
2514         }
2515
2516         /* Host coalescing configurations. */
2517         REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
2518                 pDevice->RxCoalescingTicks);
2519         REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
2520                 pDevice->TxCoalescingTicks);
2521         REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
2522                 pDevice->RxMaxCoalescedFrames);
2523         REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
2524                 pDevice->TxMaxCoalescedFrames);
2525         REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
2526                 pDevice->RxCoalescingTicksDuringInt);
2527         REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
2528                 pDevice->TxCoalescingTicksDuringInt);
2529         REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
2530                 pDevice->RxMaxCoalescedFramesDuringInt);
2531         REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
2532                 pDevice->TxMaxCoalescedFramesDuringInt);
2533
2534         /* Initialize the address of the status block.  The NIC will DMA */
2535         /* the status block to this memory which resides on the host. */
2536         REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
2537                 pDevice->StatusBlkPhy.High);
2538         REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
2539                 pDevice->StatusBlkPhy.Low);
2540
2541         /* Initialize the address of the statistics block.  The NIC will DMA */
2542         /* the statistics to this block of memory. */
2543         REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
2544                 pDevice->StatsBlkPhy.High);
2545         REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
2546                 pDevice->StatsBlkPhy.Low);
2547
2548         REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
2549                 pDevice->StatsCoalescingTicks);
2550
2551         REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
2552         REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
2553
2554         /* Enable Host Coalesing state machine */
2555         REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
2556                 pDevice->CoalesceMode);
2557
2558         /* Enable the Receive BD Completion state machine. */
2559         REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
2560                 RCV_BD_COMP_MODE_ATTN_ENABLE);
2561
2562         /* Enable the Receive List Placement state machine. */
2563         REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
2564
2565         /* Enable the Receive List Selector state machine. */
2566         REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
2567                 RCV_LIST_SEL_MODE_ATTN_ENABLE);
2568
2569         /* Enable transmit DMA, clear statistics. */
2570         pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
2571             MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
2572             MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
2573         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
2574                 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
2575
2576         /* GRC miscellaneous local control register. */
2577         pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
2578             GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
2579
2580         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2581                 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
2582                     GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
2583         }
2584
2585         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
2586         MM_Wait (40);
2587
2588         /* Reset RX counters. */
2589         for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
2590                 ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
2591         }
2592
2593         /* Reset TX counters. */
2594         for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
2595                 ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
2596         }
2597
2598         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
2599
2600         /* Enable the DMA Completion state machine. */
2601         REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
2602
2603         /* Enable the DMA Write state machine. */
2604         Value32 = DMA_WRITE_MODE_ENABLE |
2605             DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
2606             DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
2607             DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
2608             DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
2609             DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
2610             DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
2611             DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
2612             DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
2613         REG_WR (pDevice, DmaWrite.Mode, Value32);
2614
2615         if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
2616                 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
2617                         Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
2618                         Value16 &=
2619                             ~(PCIX_CMD_MAX_SPLIT_MASK |
2620                               PCIX_CMD_MAX_BURST_MASK);
2621                         Value16 |=
2622                             ((PCIX_CMD_MAX_BURST_CPIOB <<
2623                               PCIX_CMD_MAX_BURST_SHL) &
2624                              PCIX_CMD_MAX_BURST_MASK);
2625                         if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
2626                                 Value16 |=
2627                                     (pDevice->
2628                                      SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
2629                                     & PCIX_CMD_MAX_SPLIT_MASK;
2630                         }
2631                         REG_WR (pDevice, PciCfg.PciXCommand, Value16);
2632                 }
2633         }
2634
2635         /* Enable the Read DMA state machine. */
2636         Value32 = DMA_READ_MODE_ENABLE |
2637             DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
2638             DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
2639             DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
2640             DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
2641             DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
2642             DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
2643             DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
2644             DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
2645
2646         if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
2647                 Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
2648         }
2649         REG_WR (pDevice, DmaRead.Mode, Value32);
2650
2651         /* Enable the Receive Data Completion state machine. */
2652         REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
2653                 RCV_DATA_COMP_MODE_ATTN_ENABLE);
2654
2655         /* Enable the Mbuf Cluster Free state machine. */
2656         REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
2657
2658         /* Enable the Send Data Completion state machine. */
2659         REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
2660
2661         /* Enable the Send BD Completion state machine. */
2662         REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
2663                 SND_BD_COMP_MODE_ATTN_ENABLE);
2664
2665         /* Enable the Receive BD Initiator state machine. */
2666         REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
2667                 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
2668
2669         /* Enable the Receive Data and Receive BD Initiator state machine. */
2670         REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
2671                 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
2672
2673         /* Enable the Send Data Initiator state machine. */
2674         REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
2675
2676         /* Enable the Send BD Initiator state machine. */
2677         REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
2678                 SND_BD_IN_MODE_ATTN_ENABLE);
2679
2680         /* Enable the Send BD Selector state machine. */
2681         REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
2682                 SND_BD_SEL_MODE_ATTN_ENABLE);
2683
2684 #if INCLUDE_5701_AX_FIX
2685         /* Load the firmware for the 5701_A0 workaround. */
2686         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
2687                 LM_LoadRlsFirmware (pDevice);
2688         }
2689 #endif
2690
2691         /* Enable the transmitter. */
2692         pDevice->TxMode = TX_MODE_ENABLE;
2693         REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
2694
2695         /* Enable the receiver. */
2696         pDevice->RxMode = RX_MODE_ENABLE;
2697         REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
2698
2699         if (pDevice->RestoreOnWakeUp) {
2700                 pDevice->RestoreOnWakeUp = FALSE;
2701                 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
2702                 pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
2703         }
2704
2705         /* Disable auto polling. */
2706         pDevice->MiMode = 0xc0000;
2707         REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
2708
2709         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2710             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
2711                 Value32 = LED_CTRL_PHY_MODE_1;
2712         } else {
2713                 if (pDevice->LedMode == LED_MODE_OUTPUT) {
2714                         Value32 = LED_CTRL_PHY_MODE_2;
2715                 } else {
2716                         Value32 = LED_CTRL_PHY_MODE_1;
2717                 }
2718         }
2719         REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
2720
2721         /* Activate Link to enable MAC state machine */
2722         REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
2723
2724         if (pDevice->EnableTbi) {
2725                 REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
2726                 MM_Wait (10);
2727                 REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
2728                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
2729                         REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
2730                 }
2731         }
2732         /* Setup the phy chip. */
2733         LM_SetupPhy (pDevice);
2734
2735         if (!pDevice->EnableTbi) {
2736                 /* Clear CRC stats */
2737                 LM_ReadPhy (pDevice, 0x1e, &Value32);
2738                 LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
2739                 LM_ReadPhy (pDevice, 0x14, &Value32);
2740         }
2741
2742         /* Set up the receive mask. */
2743         LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);
2744
2745         /* Queue Rx packet buffers. */
2746         if (pDevice->QueueRxPackets) {
2747                 LM_QueueRxPackets (pDevice);
2748         }
2749
2750         /* Enable interrupt to the host. */
2751         if (pDevice->InitDone) {
2752                 LM_EnableInterrupt (pDevice);
2753         }
2754
2755         return LM_STATUS_SUCCESS;
2756 }                               /* LM_ResetAdapter */
2757
2758 /******************************************************************************/
2759 /* Description:                                                               */
2760 /*    This routine disables the adapter from generating interrupts.           */
2761 /*                                                                            */
2762 /* Return:                                                                    */
2763 /*    LM_STATUS_SUCCESS                                                       */
2764 /******************************************************************************/
2765 LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)
2766 {
2767         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
2768                 MISC_HOST_CTRL_MASK_PCI_INT);
2769         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
2770
2771         return LM_STATUS_SUCCESS;
2772 }
2773
2774 /******************************************************************************/
2775 /* Description:                                                               */
2776 /*    This routine enables the adapter to generate interrupts.                */
2777 /*                                                                            */
2778 /* Return:                                                                    */
2779 /*    LM_STATUS_SUCCESS                                                       */
2780 /******************************************************************************/
2781 LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)
2782 {
2783         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
2784                 ~MISC_HOST_CTRL_MASK_PCI_INT);
2785         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
2786
2787         if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
2788                 REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
2789                         GRC_MISC_LOCAL_CTRL_SET_INT);
2790         }
2791
2792         return LM_STATUS_SUCCESS;
2793 }
2794
2795 /******************************************************************************/
2796 /* Description:                                                               */
2797 /*    This routine puts a packet on the wire if there is a transmit DMA       */
2798 /*    descriptor available; otherwise the packet is queued for later          */
2799 /*    transmission.  If the second argue is NULL, this routine will put       */
2800 /*    the queued packet on the wire if possible.                              */
2801 /*                                                                            */
2802 /* Return:                                                                    */
2803 /*    LM_STATUS_SUCCESS                                                       */
2804 /******************************************************************************/
2805 #if 0
2806 LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
2807 {
2808         LM_UINT32 FragCount;
2809         PT3_SND_BD pSendBd;
2810         PT3_SND_BD pShadowSendBd;
2811         LM_UINT32 Value32, Len;
2812         LM_UINT32 Idx;
2813
2814         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2815                 return LM_5700SendPacket (pDevice, pPacket);
2816         }
2817
2818         /* Update the SendBdLeft count. */
2819         atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
2820
2821         /* Initalize the send buffer descriptors. */
2822         Idx = pDevice->SendProdIdx;
2823
2824         pSendBd = &pDevice->pSendBdVirt[Idx];
2825
2826         /* Next producer index. */
2827         if (pDevice->NicSendBd == TRUE) {
2828                 T3_64BIT_HOST_ADDR paddr;
2829
2830                 pShadowSendBd = &pDevice->ShadowSendBd[Idx];
2831                 for (FragCount = 0;;) {
2832                         MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
2833                         /* Initialize the pointer to the send buffer fragment. */
2834                         if (paddr.High != pShadowSendBd->HostAddr.High) {
2835                                 __raw_writel (paddr.High,
2836                                               &(pSendBd->HostAddr.High));
2837                                 pShadowSendBd->HostAddr.High = paddr.High;
2838                         }
2839                         __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
2840
2841                         /* Setup the control flags and send buffer size. */
2842                         Value32 = (Len << 16) | pPacket->Flags;
2843
2844                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2845
2846                         FragCount++;
2847                         if (FragCount >= pPacket->u.Tx.FragCount) {
2848                                 Value32 |= SND_BD_FLAG_END;
2849                                 if (Value32 != pShadowSendBd->u1.Len_Flags) {
2850                                         __raw_writel (Value32,
2851                                                       &(pSendBd->u1.Len_Flags));
2852                                         pShadowSendBd->u1.Len_Flags = Value32;
2853                                 }
2854                                 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
2855                                         __raw_writel (pPacket->VlanTag,
2856                                                       &(pSendBd->u2.VlanTag));
2857                                 }
2858                                 break;
2859                         } else {
2860                                 if (Value32 != pShadowSendBd->u1.Len_Flags) {
2861                                         __raw_writel (Value32,
2862                                                       &(pSendBd->u1.Len_Flags));
2863                                         pShadowSendBd->u1.Len_Flags = Value32;
2864                                 }
2865                                 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
2866                                         __raw_writel (pPacket->VlanTag,
2867                                                       &(pSendBd->u2.VlanTag));
2868                                 }
2869                         }
2870
2871                         pSendBd++;
2872                         pShadowSendBd++;
2873                         if (Idx == 0) {
2874                                 pSendBd = &pDevice->pSendBdVirt[0];
2875                                 pShadowSendBd = &pDevice->ShadowSendBd[0];
2876                         }
2877                 }               /* for */
2878
2879                 /* Put the packet descriptor in the ActiveQ. */
2880                 QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2881
2882                 wmb ();
2883                 MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
2884
2885         } else {
2886                 for (FragCount = 0;;) {
2887                         /* Initialize the pointer to the send buffer fragment. */
2888                         MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
2889                                      FragCount);
2890
2891                         pSendBd->u2.VlanTag = pPacket->VlanTag;
2892
2893                         /* Setup the control flags and send buffer size. */
2894                         Value32 = (Len << 16) | pPacket->Flags;
2895
2896                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2897
2898                         FragCount++;
2899                         if (FragCount >= pPacket->u.Tx.FragCount) {
2900                                 pSendBd->u1.Len_Flags =
2901                                     Value32 | SND_BD_FLAG_END;
2902                                 break;
2903                         } else {
2904                                 pSendBd->u1.Len_Flags = Value32;
2905                         }
2906                         pSendBd++;
2907                         if (Idx == 0) {
2908                                 pSendBd = &pDevice->pSendBdVirt[0];
2909                         }
2910                 }               /* for */
2911
2912                 /* Put the packet descriptor in the ActiveQ. */
2913                 QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2914
2915                 wmb ();
2916                 MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
2917
2918         }
2919
2920         /* Update the producer index. */
2921         pDevice->SendProdIdx = Idx;
2922
2923         return LM_STATUS_SUCCESS;
2924 }
2925 #endif
2926
2927 LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
2928 {
2929         LM_UINT32 FragCount;
2930         PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
2931         T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
2932         LM_UINT32 StartIdx, Idx;
2933
2934         while (1) {
2935                 /* Initalize the send buffer descriptors. */
2936                 StartIdx = Idx = pDevice->SendProdIdx;
2937
2938                 if (pDevice->NicSendBd) {
2939                         pTmpSendBd = pSendBd = &NicSendBdArr[0];
2940                 } else {
2941                         pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
2942                 }
2943
2944                 /* Next producer index. */
2945                 for (FragCount = 0;;) {
2946                         LM_UINT32 Value32, Len;
2947
2948                         /* Initialize the pointer to the send buffer fragment. */
2949                         MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
2950                                      FragCount);
2951
2952                         pSendBd->u2.VlanTag = pPacket->VlanTag;
2953
2954                         /* Setup the control flags and send buffer size. */
2955                         Value32 = (Len << 16) | pPacket->Flags;
2956
2957                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2958
2959                         FragCount++;
2960                         if (FragCount >= pPacket->u.Tx.FragCount) {
2961                                 pSendBd->u1.Len_Flags =
2962                                     Value32 | SND_BD_FLAG_END;
2963                                 break;
2964                         } else {
2965                                 pSendBd->u1.Len_Flags = Value32;
2966                         }
2967                         pSendBd++;
2968                         if ((Idx == 0) && !pDevice->NicSendBd) {
2969                                 pSendBd = &pDevice->pSendBdVirt[0];
2970                         }
2971                 }               /* for */
2972                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2973                         if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
2974                             LM_STATUS_SUCCESS) {
2975                                 if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
2976                                     LM_STATUS_SUCCESS) {
2977                                         QQ_PushHead (&pDevice->TxPacketFreeQ.
2978                                                      Container, pPacket);
2979                                         return LM_STATUS_FAILURE;
2980                                 }
2981                                 continue;
2982                         }
2983                 }
2984                 break;
2985         }
2986         /* Put the packet descriptor in the ActiveQ. */
2987         QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2988
2989         if (pDevice->NicSendBd) {
2990                 pSendBd = &pDevice->pSendBdVirt[StartIdx];
2991                 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
2992
2993                 while (StartIdx != Idx) {
2994                         LM_UINT32 Value32;
2995
2996                         if ((Value32 = pTmpSendBd->HostAddr.High) !=
2997                             pShadowSendBd->HostAddr.High) {
2998                                 __raw_writel (Value32,
2999                                               &(pSendBd->HostAddr.High));
3000                                 pShadowSendBd->HostAddr.High = Value32;
3001                         }
3002
3003                         __raw_writel (pTmpSendBd->HostAddr.Low,
3004                                       &(pSendBd->HostAddr.Low));
3005
3006                         if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
3007                             pShadowSendBd->u1.Len_Flags) {
3008                                 __raw_writel (Value32,
3009                                               &(pSendBd->u1.Len_Flags));
3010                                 pShadowSendBd->u1.Len_Flags = Value32;
3011                         }
3012
3013                         if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
3014                                 __raw_writel (pTmpSendBd->u2.VlanTag,
3015                                               &(pSendBd->u2.VlanTag));
3016                         }
3017
3018                         StartIdx =
3019                             (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
3020                         if (StartIdx == 0)
3021                                 pSendBd = &pDevice->pSendBdVirt[0];
3022                         else
3023                                 pSendBd++;
3024                         pTmpSendBd++;
3025                 }
3026                 wmb ();
3027                 MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
3028
3029                 if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
3030                         MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
3031                 }