drivers/usb/gadget/s3c_udc_otg_xfer_dma.c

   1 /*
   2  * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
   3  * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
   4  *
   5  * Copyright (C) 2009 for Samsung Electronics
   6  *
   7  * BSP Support for Samsung's UDC driver
   8  * available at:
   9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10  *
  11  * State machine bugfixes:
  12  * Marek Szyprowski <m.szyprowski@samsung.com>
  13  *
  14  * Ported to u-boot:
  15  * Marek Szyprowski <m.szyprowski@samsung.com>
  16  * Lukasz Majewski <l.majewski@samsumg.com>
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  */
  33
  34 static u8 clear_feature_num;
  35 int clear_feature_flag;
  36
  37 /* Bulk-Only Mass Storage Reset (class-specific request) */
  38 #define GET_MAX_LUN_REQUEST     0xFE
  39 #define BOT_RESET_REQUEST       0xFF
  40
  41 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
  42 {
  43         u32 ep_ctrl;
  44
  45         flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
  46                            (unsigned long) usb_ctrl_dma_addr
  47                            + DMA_BUFFER_SIZE);
  48
  49         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
  50         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  51
  52         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  53         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  54                &reg->in_endp[EP0_CON].diepctl);
  55
  56         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  57                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  58         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  59 }
  60
  61 void s3c_udc_pre_setup(void)
  62 {
  63         u32 ep_ctrl;
  64
  65         debug_cond(DEBUG_IN_EP,
  66                    "%s : Prepare Setup packets.\n", __func__);
  67
  68         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  69                                 (unsigned long) usb_ctrl_dma_addr
  70                                 + DMA_BUFFER_SIZE);
  71
  72         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  73                &reg->out_endp[EP0_CON].doeptsiz);
  74         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  75
  76         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  77         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  78
  79         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  80                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  81         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  82                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  83
  84 }
  85
  86 static inline void s3c_ep0_complete_out(void)
  87 {
  88         u32 ep_ctrl;
  89
  90         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  91                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  92         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  93                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  94
  95         debug_cond(DEBUG_IN_EP,
  96                 "%s : Prepare Complete Out packet.\n", __func__);
  97
  98         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  99                                 (unsigned long) usb_ctrl_dma_addr
 100                                 + DMA_BUFFER_SIZE);
 101
 102         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
 103                &reg->out_endp[EP0_CON].doeptsiz);
 104         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
 105
 106         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
 107         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 108                &reg->out_endp[EP0_CON].doepctl);
 109
 110         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 111                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
 112         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 113                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
 114
 115 }
 116
 117
 118 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
 119 {
 120         u32 *buf, ctrl;
 121         u32 length, pktcnt;
 122         u32 ep_num = ep_index(ep);
 123
 124         buf = req->req.buf + req->req.actual;
 125
 126         length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
 127
 128         ep->len = length;
 129         ep->dma_buf = buf;
 130
 131         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
 132                                 (unsigned long) ep->dev->dma_buf[ep_num]
 133                                 + DMA_BUFFER_SIZE);
 134
 135         if (length == 0)
 136                 pktcnt = 1;
 137         else
 138                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 139
 140         pktcnt = 1;
 141         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 142
 143         writel(the_controller->dma_addr[ep_index(ep)+1],
 144                &reg->out_endp[ep_num].doepdma);
 145         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 146                &reg->out_endp[ep_num].doeptsiz);
 147         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 148
 149         debug_cond(DEBUG_OUT_EP != 0,
 150                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 151                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 152                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 153                    __func__, ep_num,
 154                    readl(&reg->out_endp[ep_num].doepdma),
 155                    readl(&reg->out_endp[ep_num].doeptsiz),
 156                    readl(&reg->out_endp[ep_num].doepctl),
 157                    buf, pktcnt, length);
 158         return 0;
 159
 160 }
 161
 162 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 163 {
 164         u32 *buf, ctrl = 0;
 165         u32 length, pktcnt;
 166         u32 ep_num = ep_index(ep);
 167         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 168
 169         buf = req->req.buf + req->req.actual;
 170         length = req->req.length - req->req.actual;
 171
 172         if (ep_num == EP0_CON)
 173                 length = min(length, (u32)ep_maxpacket(ep));
 174
 175         ep->len = length;
 176         ep->dma_buf = buf;
 177         memcpy(p, ep->dma_buf, length);
 178
 179         flush_dcache_range((unsigned long) p ,
 180                            (unsigned long) p + DMA_BUFFER_SIZE);
 181
 182         if (length == 0)
 183                 pktcnt = 1;
 184         else
 185                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 186
 187         /* Flush the endpoint's Tx FIFO */
 188         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 189         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 190         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 191                 ;
 192
 193         writel(the_controller->dma_addr[ep_index(ep)+1],
 194                &reg->in_endp[ep_num].diepdma);
 195         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 196                &reg->in_endp[ep_num].dieptsiz);
 197
 198         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 199
 200         /* Write the FIFO number to be used for this endpoint */
 201         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 202         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 203
 204         /* Clear reserved (Next EP) bits */
 205         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 206
 207         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 208
 209         debug_cond(DEBUG_IN_EP,
 210                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 211                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 212                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 213                 __func__, ep_num,
 214                 readl(&reg->in_endp[ep_num].diepdma),
 215                 readl(&reg->in_endp[ep_num].dieptsiz),
 216                 readl(&reg->in_endp[ep_num].diepctl),
 217                 buf, pktcnt, length);
 218
 219         return length;
 220 }
 221
 222 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 223 {
 224         struct s3c_ep *ep = &dev->ep[ep_num];
 225         struct s3c_request *req = NULL;
 226         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 227         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 228
 229         if (list_empty(&ep->queue)) {
 230                 debug_cond(DEBUG_OUT_EP != 0,
 231                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 232                            __func__, ep_num);
 233                 return;
 234
 235         }
 236
 237         req = list_entry(ep->queue.next, struct s3c_request, queue);
 238         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 239
 240         if (ep_num == EP0_CON)
 241                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 242         else
 243                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 244
 245         xfer_size = ep->len - xfer_size;
 246
 247         invalidate_dcache_range((unsigned long) p,
 248                                 (unsigned long) p + DMA_BUFFER_SIZE);
 249
 250         memcpy(ep->dma_buf, p, ep->len);
 251
 252         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 253         is_short = (xfer_size < ep->ep.maxpacket);
 254
 255         debug_cond(DEBUG_OUT_EP != 0,
 256                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 257                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 258                    __func__, ep_num, req->req.actual, req->req.length,
 259                    is_short, ep_tsr, xfer_size);
 260
 261         if (is_short || req->req.actual == req->req.length) {
 262                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 263                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 264                         s3c_udc_ep0_zlp(dev);
 265                         /* packet will be completed in complete_tx() */
 266                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 267                 } else {
 268                         done(ep, req, 0);
 269
 270                         if (!list_empty(&ep->queue)) {
 271                                 req = list_entry(ep->queue.next,
 272                                         struct s3c_request, queue);
 273                                 debug_cond(DEBUG_OUT_EP != 0,
 274                                            "%s: Next Rx request start...\n",
 275                                            __func__);
 276                                 setdma_rx(ep, req);
 277                         }
 278                 }
 279         } else
 280                 setdma_rx(ep, req);
 281 }
 282
 283 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
 284 {
 285         struct s3c_ep *ep = &dev->ep[ep_num];
 286         struct s3c_request *req;
 287         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 288         u32 last;
 289
 290         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 291                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 292                 s3c_ep0_complete_out();
 293                 return;
 294         }
 295
 296         if (list_empty(&ep->queue)) {
 297                 debug_cond(DEBUG_IN_EP,
 298                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 299                         __func__, ep_num);
 300                 return;
 301
 302         }
 303
 304         req = list_entry(ep->queue.next, struct s3c_request, queue);
 305
 306         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 307
 308         xfer_size = ep->len;
 309         is_short = (xfer_size < ep->ep.maxpacket);
 310         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 311
 312         debug_cond(DEBUG_IN_EP,
 313                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 314                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 315                 __func__, ep_num, req->req.actual, req->req.length,
 316                 is_short, ep_tsr, xfer_size);
 317
 318         if (ep_num == 0) {
 319                 if (dev->ep0state == DATA_STATE_XMIT) {
 320                         debug_cond(DEBUG_IN_EP,
 321                                 "%s: ep_num = %d, ep0stat =="
 322                                 "DATA_STATE_XMIT\n",
 323                                 __func__, ep_num);
 324                         last = write_fifo_ep0(ep, req);
 325                         if (last)
 326                                 dev->ep0state = WAIT_FOR_COMPLETE;
 327                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 328                         debug_cond(DEBUG_IN_EP,
 329                                 "%s: ep_num = %d, completing request\n",
 330                                 __func__, ep_num);
 331                         done(ep, req, 0);
 332                         dev->ep0state = WAIT_FOR_SETUP;
 333                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 334                         debug_cond(DEBUG_IN_EP,
 335                                 "%s: ep_num = %d, completing request\n",
 336                                 __func__, ep_num);
 337                         done(ep, req, 0);
 338                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 339                         s3c_ep0_complete_out();
 340                 } else {
 341                         debug_cond(DEBUG_IN_EP,
 342                                 "%s: ep_num = %d, invalid ep state\n",
 343                                 __func__, ep_num);
 344                 }
 345                 return;
 346         }
 347
 348         if (req->req.actual == req->req.length)
 349                 done(ep, req, 0);
 350
 351         if (!list_empty(&ep->queue)) {
 352                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 353                 debug_cond(DEBUG_IN_EP,
 354                         "%s: Next Tx request start...\n", __func__);
 355                 setdma_tx(ep, req);
 356         }
 357 }
 358
 359 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
 360 {
 361         struct s3c_ep *ep = &dev->ep[ep_num];
 362         struct s3c_request *req;
 363
 364         debug_cond(DEBUG_IN_EP,
 365                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 366
 367         if (!list_empty(&ep->queue)) {
 368                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 369                 debug_cond(DEBUG_IN_EP,
 370                         "%s: Next Tx request(0x%p) start...\n",
 371                         __func__, req);
 372
 373                 if (ep_is_in(ep))
 374                         setdma_tx(ep, req);
 375                 else
 376                         setdma_rx(ep, req);
 377         } else {
 378                 debug_cond(DEBUG_IN_EP,
 379                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 380
 381                 return;
 382         }
 383
 384 }
 385
 386 static void process_ep_in_intr(struct s3c_udc *dev)
 387 {
 388         u32 ep_intr, ep_intr_status;
 389         u8 ep_num = 0;
 390
 391         ep_intr = readl(&reg->daint);
 392         debug_cond(DEBUG_IN_EP,
 393                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 394
 395         ep_intr &= DAINT_MASK;
 396
 397         while (ep_intr) {
 398                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 399                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 400                         debug_cond(DEBUG_IN_EP,
 401                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 402                                    ep_num, ep_intr_status);
 403
 404                         /* Interrupt Clear */
 405                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 406
 407                         if (ep_intr_status & TRANSFER_DONE) {
 408                                 complete_tx(dev, ep_num);
 409
 410                                 if (ep_num == 0) {
 411                                         if (dev->ep0state ==
 412                                             WAIT_FOR_IN_COMPLETE)
 413                                                 dev->ep0state = WAIT_FOR_SETUP;
 414
 415                                         if (dev->ep0state == WAIT_FOR_SETUP)
 416                                                 s3c_udc_pre_setup();
 417
 418                                         /* continue transfer after
 419                                            set_clear_halt for DMA mode */
 420                                         if (clear_feature_flag == 1) {
 421                                                 s3c_udc_check_tx_queue(dev,
 422                                                         clear_feature_num);
 423                                                 clear_feature_flag = 0;
 424                                         }
 425                                 }
 426                         }
 427                 }
 428                 ep_num++;
 429                 ep_intr >>= 1;
 430         }
 431 }
 432
 433 static void process_ep_out_intr(struct s3c_udc *dev)
 434 {
 435         u32 ep_intr, ep_intr_status;
 436         u8 ep_num = 0;
 437
 438         ep_intr = readl(&reg->daint);
 439         debug_cond(DEBUG_OUT_EP != 0,
 440                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 441                    __func__, ep_intr);
 442
 443         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 444
 445         while (ep_intr) {
 446                 if (ep_intr & 0x1) {
 447                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 448                         debug_cond(DEBUG_OUT_EP != 0,
 449                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 450                                    ep_num, ep_intr_status);
 451
 452                         /* Interrupt Clear */
 453                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 454
 455                         if (ep_num == 0) {
 456                                 if (ep_intr_status & TRANSFER_DONE) {
 457                                         if (dev->ep0state !=
 458                                             WAIT_FOR_OUT_COMPLETE)
 459                                                 complete_rx(dev, ep_num);
 460                                         else {
 461                                                 dev->ep0state = WAIT_FOR_SETUP;
 462                                                 s3c_udc_pre_setup();
 463                                         }
 464                                 }
 465
 466                                 if (ep_intr_status &
 467                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 468                                         debug_cond(DEBUG_OUT_EP != 0,
 469                                                    "SETUP packet arrived\n");
 470                                         s3c_handle_ep0(dev);
 471                                 }
 472                         } else {
 473                                 if (ep_intr_status & TRANSFER_DONE)
 474                                         complete_rx(dev, ep_num);
 475                         }
 476                 }
 477                 ep_num++;
 478                 ep_intr >>= 1;
 479         }
 480 }
 481
 482 /*
 483  *      usb client interrupt handler.
 484  */
 485 static int s3c_udc_irq(int irq, void *_dev)
 486 {
 487         struct s3c_udc *dev = _dev;
 488         u32 intr_status;
 489         u32 usb_status, gintmsk;
 490         unsigned long flags;
 491
 492         spin_lock_irqsave(&dev->lock, flags);
 493
 494         intr_status = readl(&reg->gintsts);
 495         gintmsk = readl(&reg->gintmsk);
 496
 497         debug_cond(DEBUG_ISR,
 498                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 499                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 500                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 501                   readl(&reg->daint), readl(&reg->daintmsk));
 502
 503         if (!intr_status) {
 504                 spin_unlock_irqrestore(&dev->lock, flags);
 505                 return IRQ_HANDLED;
 506         }
 507
 508         if (intr_status & INT_ENUMDONE) {
 509                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 510
 511                 writel(INT_ENUMDONE, &reg->gintsts);
 512                 usb_status = (readl(&reg->dsts) & 0x6);
 513
 514                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 515                         debug_cond(DEBUG_ISR,
 516                                    "\t\tFull Speed Detection\n");
 517                         set_max_pktsize(dev, USB_SPEED_FULL);
 518
 519                 } else {
 520                         debug_cond(DEBUG_ISR,
 521                                 "\t\tHigh Speed Detection : 0x%x\n",
 522                                 usb_status);
 523                         set_max_pktsize(dev, USB_SPEED_HIGH);
 524                 }
 525         }
 526
 527         if (intr_status & INT_EARLY_SUSPEND) {
 528                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 529                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 530         }
 531
 532         if (intr_status & INT_SUSPEND) {
 533                 usb_status = readl(&reg->dsts);
 534                 debug_cond(DEBUG_ISR,
 535                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 536                 writel(INT_SUSPEND, &reg->gintsts);
 537
 538                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 539                     && dev->driver) {
 540                         if (dev->driver->suspend)
 541                                 dev->driver->suspend(&dev->gadget);
 542
 543                         /* HACK to let gadget detect disconnected state */
 544                         if (dev->driver->disconnect) {
 545                                 spin_unlock_irqrestore(&dev->lock, flags);
 546                                 dev->driver->disconnect(&dev->gadget);
 547                                 spin_lock_irqsave(&dev->lock, flags);
 548                         }
 549                 }
 550         }
 551
 552         if (intr_status & INT_RESUME) {
 553                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 554                 writel(INT_RESUME, &reg->gintsts);
 555
 556                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 557                     && dev->driver
 558                     && dev->driver->resume) {
 559
 560                         dev->driver->resume(&dev->gadget);
 561                 }
 562         }
 563
 564         if (intr_status & INT_RESET) {
 565                 usb_status = readl(&reg->gotgctl);
 566                 debug_cond(DEBUG_ISR,
 567                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 568                 writel(INT_RESET, &reg->gintsts);
 569
 570                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 571                         if (reset_available) {
 572                                 debug_cond(DEBUG_ISR,
 573                                         "\t\tOTG core got reset (%d)!!\n",
 574                                         reset_available);
 575                                 reconfig_usbd();
 576                                 dev->ep0state = WAIT_FOR_SETUP;
 577                                 reset_available = 0;
 578                                 s3c_udc_pre_setup();
 579                         } else
 580                                 reset_available = 1;
 581
 582                 } else {
 583                         reset_available = 1;
 584                         debug_cond(DEBUG_ISR,
 585                                    "\t\tRESET handling skipped\n");
 586                 }
 587         }
 588
 589         if (intr_status & INT_IN_EP)
 590                 process_ep_in_intr(dev);
 591
 592         if (intr_status & INT_OUT_EP)
 593                 process_ep_out_intr(dev);
 594
 595         spin_unlock_irqrestore(&dev->lock, flags);
 596
 597         return IRQ_HANDLED;
 598 }
 599
 600 /** Queue one request
 601  *  Kickstart transfer if needed
 602  */
 603 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 604                          gfp_t gfp_flags)
 605 {
 606         struct s3c_request *req;
 607         struct s3c_ep *ep;
 608         struct s3c_udc *dev;
 609         unsigned long flags;
 610         u32 ep_num, gintsts;
 611
 612         req = container_of(_req, struct s3c_request, req);
 613         if (unlikely(!_req || !_req->complete || !_req->buf
 614                      || !list_empty(&req->queue))) {
 615
 616                 debug("%s: bad params\n", __func__);
 617                 return -EINVAL;
 618         }
 619
 620         ep = container_of(_ep, struct s3c_ep, ep);
 621
 622         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 623
 624                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 625                       ep->ep.name, !ep->desc, _ep);
 626                 return -EINVAL;
 627         }
 628
 629         ep_num = ep_index(ep);
 630         dev = ep->dev;
 631         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 632
 633                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 634                 return -ESHUTDOWN;
 635         }
 636
 637         spin_lock_irqsave(&dev->lock, flags);
 638
 639         _req->status = -EINPROGRESS;
 640         _req->actual = 0;
 641
 642         /* kickstart this i/o queue? */
 643         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 644                 "Q empty = %d, stopped = %d\n",
 645                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 646                 _req, _req->length, _req->buf,
 647                 list_empty(&ep->queue), ep->stopped);
 648
 649 #ifdef DEBUG
 650         {
 651                 int i, len = _req->length;
 652
 653                 printf("pkt = ");
 654                 if (len > 64)
 655                         len = 64;
 656                 for (i = 0; i < len; i++) {
 657                         printf("%02x", ((u8 *)_req->buf)[i]);
 658                         if ((i & 7) == 7)
 659                                 printf(" ");
 660                 }
 661                 printf("\n");
 662         }
 663 #endif
 664
 665         if (list_empty(&ep->queue) && !ep->stopped) {
 666
 667                 if (ep_num == 0) {
 668                         /* EP0 */
 669                         list_add_tail(&req->queue, &ep->queue);
 670                         s3c_ep0_kick(dev, ep);
 671                         req = 0;
 672
 673                 } else if (ep_is_in(ep)) {
 674                         gintsts = readl(&reg->gintsts);
 675                         debug_cond(DEBUG_IN_EP,
 676                                    "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
 677                                    __func__, gintsts);
 678
 679                         setdma_tx(ep, req);
 680                 } else {
 681                         gintsts = readl(&reg->gintsts);
 682                         debug_cond(DEBUG_OUT_EP != 0,
 683                                    "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
 684                                    __func__, gintsts);
 685
 686                         setdma_rx(ep, req);
 687                 }
 688         }
 689
 690         /* pio or dma irq handler advances the queue. */
 691         if (likely(req != 0))
 692                 list_add_tail(&req->queue, &ep->queue);
 693
 694         spin_unlock_irqrestore(&dev->lock, flags);
 695
 696         return 0;
 697 }
 698
 699 /****************************************************************/
 700 /* End Point 0 related functions                                */
 701 /****************************************************************/
 702
 703 /* return:  0 = still running, 1 = completed, negative = errno */
 704 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 705 {
 706         u32 max;
 707         unsigned count;
 708         int is_last;
 709
 710         max = ep_maxpacket(ep);
 711
 712         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 713
 714         count = setdma_tx(ep, req);
 715
 716         /* last packet is usually short (or a zlp) */
 717         if (likely(count != max))
 718                 is_last = 1;
 719         else {
 720                 if (likely(req->req.length != req->req.actual + count)
 721                     || req->req.zero)
 722                         is_last = 0;
 723                 else
 724                         is_last = 1;
 725         }
 726
 727         debug_cond(DEBUG_EP0 != 0,
 728                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 729                    ep->ep.name, count,
 730                    is_last ? "/L" : "",
 731                    req->req.length - req->req.actual - count, req);
 732
 733         /* requests complete when all IN data is in the FIFO */
 734         if (is_last) {
 735                 ep->dev->ep0state = WAIT_FOR_SETUP;
 736                 return 1;
 737         }
 738
 739         return 0;
 740 }
 741
 742 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 743 {
 744         u32 bytes;
 745
 746         bytes = sizeof(struct usb_ctrlrequest);
 747
 748         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
 749                                 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
 750                                 + DMA_BUFFER_SIZE);
 751
 752         debug_cond(DEBUG_EP0 != 0,
 753                    "%s: bytes=%d, ep_index=%d %p\n", __func__,
 754                    bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
 755
 756         return bytes;
 757 }
 758
 759 /**
 760  * udc_set_address - set the USB address for this device
 761  * @address:
 762  *
 763  * Called from control endpoint function
 764  * after it decodes a set address setup packet.
 765  */
 766 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
 767 {
 768         u32 ctrl = readl(&reg->dcfg);
 769         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 770
 771         s3c_udc_ep0_zlp(dev);
 772
 773         debug_cond(DEBUG_EP0 != 0,
 774                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 775                    __func__, address, readl(&reg->dcfg));
 776
 777         dev->usb_address = address;
 778 }
 779
 780 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
 781 {
 782         struct s3c_udc *dev;
 783         u32             ep_ctrl = 0;
 784
 785         dev = ep->dev;
 786         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 787
 788         /* set the disable and stall bits */
 789         if (ep_ctrl & DEPCTL_EPENA)
 790                 ep_ctrl |= DEPCTL_EPDIS;
 791
 792         ep_ctrl |= DEPCTL_STALL;
 793
 794         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 795
 796         debug_cond(DEBUG_EP0 != 0,
 797                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 798                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 799         /*
 800          * The application can only set this bit, and the core clears it,
 801          * when a SETUP token is received for this endpoint
 802          */
 803         dev->ep0state = WAIT_FOR_SETUP;
 804
 805         s3c_udc_pre_setup();
 806 }
 807
 808 static void s3c_ep0_read(struct s3c_udc *dev)
 809 {
 810         struct s3c_request *req;
 811         struct s3c_ep *ep = &dev->ep[0];
 812
 813         if (!list_empty(&ep->queue)) {
 814                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 815
 816         } else {
 817                 debug("%s: ---> BUG\n", __func__);
 818                 BUG();
 819                 return;
 820         }
 821
 822         debug_cond(DEBUG_EP0 != 0,
 823                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 824                    __func__, req, req->req.length, req->req.actual);
 825
 826         if (req->req.length == 0) {
 827                 /* zlp for Set_configuration, Set_interface,
 828                  * or Bulk-Only mass storge reset */
 829
 830                 ep->len = 0;
 831                 s3c_udc_ep0_zlp(dev);
 832
 833                 debug_cond(DEBUG_EP0 != 0,
 834                            "%s: req.length = 0, bRequest = %d\n",
 835                            __func__, usb_ctrl->bRequest);
 836                 return;
 837         }
 838
 839         setdma_rx(ep, req);
 840 }
 841
 842 /*
 843  * DATA_STATE_XMIT
 844  */
 845 static int s3c_ep0_write(struct s3c_udc *dev)
 846 {
 847         struct s3c_request *req;
 848         struct s3c_ep *ep = &dev->ep[0];
 849         int ret, need_zlp = 0;
 850
 851         if (list_empty(&ep->queue))
 852                 req = 0;
 853         else
 854                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 855
 856         if (!req) {
 857                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 858                 return 0;
 859         }
 860
 861         debug_cond(DEBUG_EP0 != 0,
 862                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 863                    __func__, req, req->req.length, req->req.actual);
 864
 865         if (req->req.length - req->req.actual == ep0_fifo_size) {
 866                 /* Next write will end with the packet size, */
 867                 /* so we need Zero-length-packet */
 868                 need_zlp = 1;
 869         }
 870
 871         ret = write_fifo_ep0(ep, req);
 872
 873         if ((ret == 1) && !need_zlp) {
 874                 /* Last packet */
 875                 dev->ep0state = WAIT_FOR_COMPLETE;
 876                 debug_cond(DEBUG_EP0 != 0,
 877                            "%s: finished, waiting for status\n", __func__);
 878
 879         } else {
 880                 dev->ep0state = DATA_STATE_XMIT;
 881                 debug_cond(DEBUG_EP0 != 0,
 882                            "%s: not finished\n", __func__);
 883         }
 884
 885         return 1;
 886 }
 887
 888 u16     g_status;
 889
 890 int s3c_udc_get_status(struct s3c_udc *dev,
 891                 struct usb_ctrlrequest *crq)
 892 {
 893         u8 ep_num = crq->wIndex & 0x7F;
 894         u32 ep_ctrl;
 895         u32 *p = the_controller->dma_buf[1];
 896
 897         debug_cond(DEBUG_SETUP != 0,
 898                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 899         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 900         switch (crq->bRequestType & USB_RECIP_MASK) {
 901         case USB_RECIP_INTERFACE:
 902                 g_status = 0;
 903                 debug_cond(DEBUG_SETUP != 0,
 904                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 905                            g_status);
 906                 break;
 907
 908         case USB_RECIP_DEVICE:
 909                 g_status = 0x1; /* Self powered */
 910                 debug_cond(DEBUG_SETUP != 0,
 911                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 912                            g_status);
 913                 break;
 914
 915         case USB_RECIP_ENDPOINT:
 916                 if (crq->wLength > 2) {
 917                         debug_cond(DEBUG_SETUP != 0,
 918                                    "\tGET_STATUS:Not support EP or wLength\n");
 919                         return 1;
 920                 }
 921
 922                 g_status = dev->ep[ep_num].stopped;
 923                 debug_cond(DEBUG_SETUP != 0,
 924                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 925                            g_status);
 926
 927                 break;
 928
 929         default:
 930                 return 1;
 931         }
 932
 933         memcpy(p, &g_status, sizeof(g_status));
 934
 935         flush_dcache_range((unsigned long) p,
 936                            (unsigned long) p + DMA_BUFFER_SIZE);
 937
 938         writel(the_controller->dma_addr[1], &reg->in_endp[EP0_CON].diepdma);
 939         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 940                &reg->in_endp[EP0_CON].dieptsiz);
 941
 942         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 943         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 944                &reg->in_endp[EP0_CON].diepctl);
 945         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 946
 947         return 0;
 948 }
 949
 950 static void s3c_udc_set_nak(struct s3c_ep *ep)
 951 {
 952         u8              ep_num;
 953         u32             ep_ctrl = 0;
 954
 955         ep_num = ep_index(ep);
 956         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 957
 958         if (ep_is_in(ep)) {
 959                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 960                 ep_ctrl |= DEPCTL_SNAK;
 961                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 962                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 963                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 964         } else {
 965                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 966                 ep_ctrl |= DEPCTL_SNAK;
 967                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 968                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 969                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 970         }
 971
 972         return;
 973 }
 974
 975
 976 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
 977 {
 978         u8              ep_num;
 979         u32             ep_ctrl = 0;
 980
 981         ep_num = ep_index(ep);
 982         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 983
 984         if (ep_is_in(ep)) {
 985                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 986
 987                 /* set the disable and stall bits */
 988                 if (ep_ctrl & DEPCTL_EPENA)
 989                         ep_ctrl |= DEPCTL_EPDIS;
 990
 991                 ep_ctrl |= DEPCTL_STALL;
 992
 993                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 994                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 995                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 996
 997         } else {
 998                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 999
1000                 /* set the stall bit */
1001                 ep_ctrl |= DEPCTL_STALL;
1002
1003                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1004                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
1005                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1006         }
1007
1008         return;
1009 }
1010
1011 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
1012 {
1013         u8              ep_num;
1014         u32             ep_ctrl = 0;
1015
1016         ep_num = ep_index(ep);
1017         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1018
1019         if (ep_is_in(ep)) {
1020                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1021
1022                 /* clear stall bit */
1023                 ep_ctrl &= ~DEPCTL_STALL;
1024
1025                 /*
1026                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1027                  * of whether an endpoint has the Halt feature set, a
1028                  * ClearFeature(ENDPOINT_HALT) request always results in the
1029                  * data toggle being reinitialized to DATA0.
1030                  */
1031                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1032                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1033                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1034                 }
1035
1036                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1037                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1038                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1039
1040         } else {
1041                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1042
1043                 /* clear stall bit */
1044                 ep_ctrl &= ~DEPCTL_STALL;
1045
1046                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1047                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1048                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1049                 }
1050
1051                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1052                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1053                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1054         }
1055
1056         return;
1057 }
1058
1059 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1060 {
1061         struct s3c_ep   *ep;
1062         struct s3c_udc  *dev;
1063         unsigned long   flags;
1064         u8              ep_num;
1065
1066         ep = container_of(_ep, struct s3c_ep, ep);
1067         ep_num = ep_index(ep);
1068
1069         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1070                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1071                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1072                 return -EINVAL;
1073         }
1074
1075         /* Attempt to halt IN ep will fail if any transfer requests
1076          * are still queue */
1077         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1078                 debug("%s: %s queue not empty, req = %p\n",
1079                         __func__, ep->ep.name,
1080                         list_entry(ep->queue.next, struct s3c_request, queue));
1081
1082                 return -EAGAIN;
1083         }
1084
1085         dev = ep->dev;
1086         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1087
1088         spin_lock_irqsave(&dev->lock, flags);
1089
1090         if (value == 0) {
1091                 ep->stopped = 0;
1092                 s3c_udc_ep_clear_stall(ep);
1093         } else {
1094                 if (ep_num == 0)
1095                         dev->ep0state = WAIT_FOR_SETUP;
1096
1097                 ep->stopped = 1;
1098                 s3c_udc_ep_set_stall(ep);
1099         }
1100
1101         spin_unlock_irqrestore(&dev->lock, flags);
1102
1103         return 0;
1104 }
1105
1106 void s3c_udc_ep_activate(struct s3c_ep *ep)
1107 {
1108         u8 ep_num;
1109         u32 ep_ctrl = 0, daintmsk = 0;
1110
1111         ep_num = ep_index(ep);
1112
1113         /* Read DEPCTLn register */
1114         if (ep_is_in(ep)) {
1115                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1116                 daintmsk = 1 << ep_num;
1117         } else {
1118                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1119                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1120         }
1121
1122         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1123                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1124
1125         /* If the EP is already active don't change the EP Control
1126          * register. */
1127         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1128                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1129                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1130                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1131                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1132                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1133
1134                 if (ep_is_in(ep)) {
1135                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1136                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1137                               __func__, ep_num, ep_num,
1138                               readl(&reg->in_endp[ep_num].diepctl));
1139                 } else {
1140                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1141                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1142                               __func__, ep_num, ep_num,
1143                               readl(&reg->out_endp[ep_num].doepctl));
1144                 }
1145         }
1146
1147         /* Unmask EP Interrtupt */
1148         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1149         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1150
1151 }
1152
1153 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1154 {
1155         struct s3c_udc  *dev;
1156         struct s3c_ep   *ep;
1157         u8              ep_num;
1158
1159         ep = container_of(_ep, struct s3c_ep, ep);
1160         ep_num = ep_index(ep);
1161
1162         dev = ep->dev;
1163         debug_cond(DEBUG_SETUP != 0,
1164                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1165                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1166
1167         if (usb_ctrl->wLength != 0) {
1168                 debug_cond(DEBUG_SETUP != 0,
1169                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1170                 return 1;
1171         }
1172
1173         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1174         case USB_RECIP_DEVICE:
1175                 switch (usb_ctrl->wValue) {
1176                 case USB_DEVICE_REMOTE_WAKEUP:
1177                         debug_cond(DEBUG_SETUP != 0,
1178                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1179                         break;
1180
1181                 case USB_DEVICE_TEST_MODE:
1182                         debug_cond(DEBUG_SETUP != 0,
1183                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1184                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1185                         break;
1186                 }
1187
1188                 s3c_udc_ep0_zlp(dev);
1189                 break;
1190
1191         case USB_RECIP_ENDPOINT:
1192                 debug_cond(DEBUG_SETUP != 0,
1193                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1194                            usb_ctrl->wValue);
1195
1196                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1197                         if (ep_num == 0) {
1198                                 s3c_udc_ep0_set_stall(ep);
1199                                 return 0;
1200                         }
1201
1202                         s3c_udc_ep0_zlp(dev);
1203
1204                         s3c_udc_ep_clear_stall(ep);
1205                         s3c_udc_ep_activate(ep);
1206                         ep->stopped = 0;
1207
1208                         clear_feature_num = ep_num;
1209                         clear_feature_flag = 1;
1210                 }
1211                 break;
1212         }
1213
1214         return 0;
1215 }
1216
1217 static int s3c_udc_set_feature(struct usb_ep *_ep)
1218 {
1219         struct s3c_udc  *dev;
1220         struct s3c_ep   *ep;
1221         u8              ep_num;
1222
1223         ep = container_of(_ep, struct s3c_ep, ep);
1224         ep_num = ep_index(ep);
1225         dev = ep->dev;
1226
1227         debug_cond(DEBUG_SETUP != 0,
1228                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1229                     __func__, ep_num);
1230
1231         if (usb_ctrl->wLength != 0) {
1232                 debug_cond(DEBUG_SETUP != 0,
1233                            "\tSET_FEATURE: wLength is not zero.....\n");
1234                 return 1;
1235         }
1236
1237         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1238         case USB_RECIP_DEVICE:
1239                 switch (usb_ctrl->wValue) {
1240                 case USB_DEVICE_REMOTE_WAKEUP:
1241                         debug_cond(DEBUG_SETUP != 0,
1242                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1243                         break;
1244                 case USB_DEVICE_B_HNP_ENABLE:
1245                         debug_cond(DEBUG_SETUP != 0,
1246                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1247                         break;
1248
1249                 case USB_DEVICE_A_HNP_SUPPORT:
1250                         /* RH port supports HNP */
1251                         debug_cond(DEBUG_SETUP != 0,
1252                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1253                         break;
1254
1255                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1256                         /* other RH port does */
1257                         debug_cond(DEBUG_SETUP != 0,
1258                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1259                         break;
1260                 }
1261
1262                 s3c_udc_ep0_zlp(dev);
1263                 return 0;
1264
1265         case USB_RECIP_INTERFACE:
1266                 debug_cond(DEBUG_SETUP != 0,
1267                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1268                 break;
1269
1270         case USB_RECIP_ENDPOINT:
1271                 debug_cond(DEBUG_SETUP != 0,
1272                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1273                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1274                         if (ep_num == 0) {
1275                                 s3c_udc_ep0_set_stall(ep);
1276                                 return 0;
1277                         }
1278                         ep->stopped = 1;
1279                         s3c_udc_ep_set_stall(ep);
1280                 }
1281
1282                 s3c_udc_ep0_zlp(dev);
1283                 return 0;
1284         }
1285
1286         return 1;
1287 }
1288
1289 /*
1290  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1291  */
1292 void s3c_ep0_setup(struct s3c_udc *dev)
1293 {
1294         struct s3c_ep *ep = &dev->ep[0];
1295         int i;
1296         u8 ep_num;
1297
1298         /* Nuke all previous transfers */
1299         nuke(ep, -EPROTO);
1300
1301         /* read control req from fifo (8 bytes) */
1302         s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1303
1304         debug_cond(DEBUG_SETUP != 0,
1305                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1306                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1307                    __func__, usb_ctrl->bRequestType,
1308                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1309                    usb_ctrl->bRequest,
1310                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1311
1312 #ifdef DEBUG
1313         {
1314                 int i, len = sizeof(*usb_ctrl);
1315                 char *p = (char *)usb_ctrl;
1316
1317                 printf("pkt = ");
1318                 for (i = 0; i < len; i++) {
1319                         printf("%02x", ((u8 *)p)[i]);
1320                         if ((i & 7) == 7)
1321                                 printf(" ");
1322                 }
1323                 printf("\n");
1324         }
1325 #endif
1326
1327         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1328             usb_ctrl->wLength != 1) {
1329                 debug_cond(DEBUG_SETUP != 0,
1330                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1331                            __func__);
1332                 debug_cond(DEBUG_SETUP != 0,
1333                            "wLength = %d, setup returned\n",
1334                            usb_ctrl->wLength);
1335
1336                 s3c_udc_ep0_set_stall(ep);
1337                 dev->ep0state = WAIT_FOR_SETUP;
1338
1339                 return;
1340         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1341                  usb_ctrl->wLength != 0) {
1342                 /* Bulk-Only *mass storge reset of class-specific request */
1343                 debug_cond(DEBUG_SETUP != 0,
1344                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1345                            __func__, usb_ctrl->wLength);
1346
1347                 s3c_udc_ep0_set_stall(ep);
1348                 dev->ep0state = WAIT_FOR_SETUP;
1349
1350                 return;
1351         }
1352
1353         /* Set direction of EP0 */
1354         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1355                 ep->bEndpointAddress |= USB_DIR_IN;
1356         } else {
1357                 ep->bEndpointAddress &= ~USB_DIR_IN;
1358         }
1359         /* cope with automagic for some standard requests. */
1360         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1361                 == USB_TYPE_STANDARD;
1362
1363         dev->req_pending = 1;
1364
1365         /* Handle some SETUP packets ourselves */
1366         if (dev->req_std) {
1367                 switch (usb_ctrl->bRequest) {
1368                 case USB_REQ_SET_ADDRESS:
1369                 debug_cond(DEBUG_SETUP != 0,
1370                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1371                            __func__, usb_ctrl->wValue);
1372                         if (usb_ctrl->bRequestType
1373                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1374                                 break;
1375
1376                         udc_set_address(dev, usb_ctrl->wValue);
1377                         return;
1378
1379                 case USB_REQ_SET_CONFIGURATION:
1380                         debug_cond(DEBUG_SETUP != 0,
1381                                    "=====================================\n");
1382                         debug_cond(DEBUG_SETUP != 0,
1383                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1384                                    __func__, usb_ctrl->wValue);
1385
1386                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1387                                 reset_available = 1;
1388
1389                         break;
1390
1391                 case USB_REQ_GET_DESCRIPTOR:
1392                         debug_cond(DEBUG_SETUP != 0,
1393                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1394                                    __func__);
1395                         break;
1396
1397                 case USB_REQ_SET_INTERFACE:
1398                         debug_cond(DEBUG_SETUP != 0,
1399                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1400                                    __func__, usb_ctrl->wValue);
1401
1402                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1403                                 reset_available = 1;
1404
1405                         break;
1406
1407                 case USB_REQ_GET_CONFIGURATION:
1408                         debug_cond(DEBUG_SETUP != 0,
1409                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1410                                    __func__);
1411                         break;
1412
1413                 case USB_REQ_GET_STATUS:
1414                         if (!s3c_udc_get_status(dev, usb_ctrl))
1415                                 return;
1416
1417                         break;
1418
1419                 case USB_REQ_CLEAR_FEATURE:
1420                         ep_num = usb_ctrl->wIndex & 0x7f;
1421
1422                         if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1423                                 return;
1424
1425                         break;
1426
1427                 case USB_REQ_SET_FEATURE:
1428                         ep_num = usb_ctrl->wIndex & 0x7f;
1429
1430                         if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1431                                 return;
1432
1433                         break;
1434
1435                 default:
1436                         debug_cond(DEBUG_SETUP != 0,
1437                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1438                                    "happened.\n", __func__, usb_ctrl->bRequest);
1439                         break;
1440                 }
1441         }
1442
1443
1444         if (likely(dev->driver)) {
1445                 /* device-2-host (IN) or no data setup command,
1446                  * process immediately */
1447                 debug_cond(DEBUG_SETUP != 0,
1448                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1449                             __func__);
1450
1451                 spin_unlock(&dev->lock);
1452                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1453                 spin_lock(&dev->lock);
1454
1455                 if (i < 0) {
1456                         /* setup processing failed, force stall */
1457                         s3c_udc_ep0_set_stall(ep);
1458                         dev->ep0state = WAIT_FOR_SETUP;
1459
1460                         debug_cond(DEBUG_SETUP != 0,
1461                                    "\tdev->driver->setup failed (%d),"
1462                                     " bRequest = %d\n",
1463                                 i, usb_ctrl->bRequest);
1464
1465
1466                 } else if (dev->req_pending) {
1467                         dev->req_pending = 0;
1468                         debug_cond(DEBUG_SETUP != 0,
1469                                    "\tdev->req_pending...\n");
1470                 }
1471
1472                 debug_cond(DEBUG_SETUP != 0,
1473                            "\tep0state = %s\n", state_names[dev->ep0state]);
1474
1475         }
1476 }
1477
1478 /*
1479  * handle ep0 interrupt
1480  */
1481 static void s3c_handle_ep0(struct s3c_udc *dev)
1482 {
1483         if (dev->ep0state == WAIT_FOR_SETUP) {
1484                 debug_cond(DEBUG_OUT_EP != 0,
1485                            "%s: WAIT_FOR_SETUP\n", __func__);
1486                 s3c_ep0_setup(dev);
1487
1488         } else {
1489                 debug_cond(DEBUG_OUT_EP != 0,
1490                            "%s: strange state!!(state = %s)\n",
1491                         __func__, state_names[dev->ep0state]);
1492         }
1493 }
1494
1495 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1496 {
1497         debug_cond(DEBUG_EP0 != 0,
1498                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1499         if (ep_is_in(ep)) {
1500                 dev->ep0state = DATA_STATE_XMIT;
1501                 s3c_ep0_write(dev);
1502
1503         } else {
1504                 dev->ep0state = DATA_STATE_RECV;
1505                 s3c_ep0_read(dev);
1506         }
1507 }