ush: ehci: initialize altnext pointers in QH
[karo-tx-uboot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
3  * Copyright (c) 2008, Excito Elektronik i Sk√•ne AB
4  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5  *
6  * All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2 of
11  * the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 #include <common.h>
24 #include <errno.h>
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
27 #include <usb.h>
28 #include <asm/io.h>
29 #include <malloc.h>
30 #include <watchdog.h>
31 #include <linux/compiler.h>
32
33 #include "ehci.h"
34
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
37 #endif
38
39 /*
40  * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
41  * Let's time out after 8 to have a little safety margin on top of that.
42  */
43 #define HCHALT_TIMEOUT (8 * 1000)
44
45 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
46
47 #define ALIGN_END_ADDR(type, ptr, size)                 \
48         ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
49
50 static struct descriptor {
51         struct usb_hub_descriptor hub;
52         struct usb_device_descriptor device;
53         struct usb_linux_config_descriptor config;
54         struct usb_linux_interface_descriptor interface;
55         struct usb_endpoint_descriptor endpoint;
56 }  __attribute__ ((packed)) descriptor = {
57         {
58                 0x8,            /* bDescLength */
59                 0x29,           /* bDescriptorType: hub descriptor */
60                 2,              /* bNrPorts -- runtime modified */
61                 0,              /* wHubCharacteristics */
62                 10,             /* bPwrOn2PwrGood */
63                 0,              /* bHubCntrCurrent */
64                 {},             /* Device removable */
65                 {}              /* at most 7 ports! XXX */
66         },
67         {
68                 0x12,           /* bLength */
69                 1,              /* bDescriptorType: UDESC_DEVICE */
70                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
71                 9,              /* bDeviceClass: UDCLASS_HUB */
72                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
73                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
74                 64,             /* bMaxPacketSize: 64 bytes */
75                 0x0000,         /* idVendor */
76                 0x0000,         /* idProduct */
77                 cpu_to_le16(0x0100), /* bcdDevice */
78                 1,              /* iManufacturer */
79                 2,              /* iProduct */
80                 0,              /* iSerialNumber */
81                 1               /* bNumConfigurations: 1 */
82         },
83         {
84                 0x9,
85                 2,              /* bDescriptorType: UDESC_CONFIG */
86                 cpu_to_le16(0x19),
87                 1,              /* bNumInterface */
88                 1,              /* bConfigurationValue */
89                 0,              /* iConfiguration */
90                 0x40,           /* bmAttributes: UC_SELF_POWER */
91                 0               /* bMaxPower */
92         },
93         {
94                 0x9,            /* bLength */
95                 4,              /* bDescriptorType: UDESC_INTERFACE */
96                 0,              /* bInterfaceNumber */
97                 0,              /* bAlternateSetting */
98                 1,              /* bNumEndpoints */
99                 9,              /* bInterfaceClass: UICLASS_HUB */
100                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
101                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
102                 0               /* iInterface */
103         },
104         {
105                 0x7,            /* bLength */
106                 5,              /* bDescriptorType: UDESC_ENDPOINT */
107                 0x81,           /* bEndpointAddress:
108                                  * UE_DIR_IN | EHCI_INTR_ENDPT
109                                  */
110                 3,              /* bmAttributes: UE_INTERRUPT */
111                 8,              /* wMaxPacketSize */
112                 255             /* bInterval */
113         },
114 };
115
116 #if defined(CONFIG_EHCI_IS_TDI)
117 #define ehci_is_TDI()   (1)
118 #else
119 #define ehci_is_TDI()   (0)
120 #endif
121
122 int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
123 {
124         return PORTSC_PSPD(reg);
125 }
126
127 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
128         __attribute__((weak, alias("__ehci_get_port_speed")));
129
130 void __ehci_set_usbmode(int index)
131 {
132         uint32_t tmp;
133         uint32_t *reg_ptr;
134
135         reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE);
136         tmp = ehci_readl(reg_ptr);
137         tmp |= USBMODE_CM_HC;
138 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
139         tmp |= USBMODE_BE;
140 #endif
141         ehci_writel(reg_ptr, tmp);
142 }
143
144 void ehci_set_usbmode(int index)
145         __attribute__((weak, alias("__ehci_set_usbmode")));
146
147 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
148 {
149         mdelay(50);
150 }
151
152 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
153         __attribute__((weak, alias("__ehci_powerup_fixup")));
154
155 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
156 {
157         uint32_t result;
158         do {
159                 result = ehci_readl(ptr);
160                 udelay(5);
161                 if (result == ~(uint32_t)0)
162                         return -1;
163                 result &= mask;
164                 if (result == done)
165                         return 0;
166                 usec--;
167         } while (usec > 0);
168         return -1;
169 }
170
171 static int ehci_reset(int index)
172 {
173         uint32_t cmd;
174         int ret = 0;
175
176         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
177         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
178         ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
179         ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
180                         CMD_RESET, 0, 250 * 1000);
181         if (ret < 0) {
182                 printf("EHCI fail to reset\n");
183                 goto out;
184         }
185
186         if (ehci_is_TDI())
187                 ehci_set_usbmode(index);
188
189 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
190         cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
191         cmd &= ~TXFIFO_THRESH_MASK;
192         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
193         ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
194 #endif
195 out:
196         return ret;
197 }
198
199 static int ehci_shutdown(struct ehci_ctrl *ctrl)
200 {
201         int i, ret = 0;
202         uint32_t cmd, reg;
203
204         if (!ctrl || !ctrl->hcor)
205                 return -EINVAL;
206
207         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
208         cmd &= ~(CMD_PSE | CMD_ASE);
209         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
210         ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
211                 100 * 1000);
212
213         if (!ret) {
214                 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
215                         reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
216                         reg |= EHCI_PS_SUSP;
217                         ehci_writel(&ctrl->hcor->or_portsc[i], reg);
218                 }
219
220                 cmd &= ~CMD_RUN;
221                 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
222                 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
223                         HCHALT_TIMEOUT);
224         }
225
226         if (ret)
227                 puts("EHCI failed to shut down host controller.\n");
228
229         return ret;
230 }
231
232 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
233 {
234         uint32_t delta, next;
235         uint32_t addr = (uint32_t)buf;
236         int idx;
237
238         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
239                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
240
241         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
242
243         idx = 0;
244         while (idx < QT_BUFFER_CNT) {
245                 td->qt_buffer[idx] = cpu_to_hc32(addr);
246                 td->qt_buffer_hi[idx] = 0;
247                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
248                 delta = next - addr;
249                 if (delta >= sz)
250                         break;
251                 sz -= delta;
252                 addr = next;
253                 idx++;
254         }
255
256         if (idx == QT_BUFFER_CNT) {
257                 printf("out of buffer pointers (%u bytes left)\n", sz);
258                 return -1;
259         }
260
261         return 0;
262 }
263
264 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
265 {
266         #define QH_HIGH_SPEED   2
267         #define QH_FULL_SPEED   0
268         #define QH_LOW_SPEED    1
269         if (speed == USB_SPEED_HIGH)
270                 return QH_HIGH_SPEED;
271         if (speed == USB_SPEED_LOW)
272                 return QH_LOW_SPEED;
273         return QH_FULL_SPEED;
274 }
275
276 static int
277 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
278                    int length, struct devrequest *req)
279 {
280         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
281         struct qTD *qtd;
282         int qtd_count = 0;
283         int qtd_counter = 0;
284         volatile struct qTD *vtd;
285         unsigned long ts;
286         uint32_t *tdp;
287         uint32_t endpt, maxpacket, token, usbsts;
288         uint32_t c, toggle;
289         uint32_t cmd;
290         int timeout;
291         int ret = 0;
292         struct ehci_ctrl *ctrl = dev->controller;
293
294         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
295               buffer, length, req);
296         if (req != NULL)
297                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
298                       req->request, req->request,
299                       req->requesttype, req->requesttype,
300                       le16_to_cpu(req->value), le16_to_cpu(req->value),
301                       le16_to_cpu(req->index));
302
303 #define PKT_ALIGN       512
304         /*
305          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
306          * described by a transfer descriptor (the qTD). The qTDs form a linked
307          * list with a queue head (QH).
308          *
309          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
310          * have its beginning in a qTD transfer and its end in the following
311          * one, so the qTD transfer lengths have to be chosen accordingly.
312          *
313          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
314          * single pages. The first data buffer can start at any offset within a
315          * page (not considering the cache-line alignment issues), while the
316          * following buffers must be page-aligned. There is no alignment
317          * constraint on the size of a qTD transfer.
318          */
319         if (req != NULL)
320                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
321                 qtd_count += 1 + 1;
322         if (length > 0 || req == NULL) {
323                 /*
324                  * Determine the qTD transfer size that will be used for the
325                  * data payload (not considering the first qTD transfer, which
326                  * may be longer or shorter, and the final one, which may be
327                  * shorter).
328                  *
329                  * In order to keep each packet within a qTD transfer, the qTD
330                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
331                  * wMaxPacketSize (except in some cases for interrupt transfers,
332                  * see comment in submit_int_msg()).
333                  *
334                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
335                  * QT_BUFFER_CNT full pages will be used.
336                  */
337                 int xfr_sz = QT_BUFFER_CNT;
338                 /*
339                  * However, if the input buffer is not aligned to PKT_ALIGN, the
340                  * qTD transfer size will be one page shorter, and the first qTD
341                  * data buffer of each transfer will be page-unaligned.
342                  */
343                 if ((uint32_t)buffer & (PKT_ALIGN - 1))
344                         xfr_sz--;
345                 /* Convert the qTD transfer size to bytes. */
346                 xfr_sz *= EHCI_PAGE_SIZE;
347                 /*
348                  * Approximate by excess the number of qTDs that will be
349                  * required for the data payload. The exact formula is way more
350                  * complicated and saves at most 2 qTDs, i.e. a total of 128
351                  * bytes.
352                  */
353                 qtd_count += 2 + length / xfr_sz;
354         }
355 /*
356  * Threshold value based on the worst-case total size of the allocated qTDs for
357  * a mass-storage transfer of 65535 blocks of 512 bytes.
358  */
359 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
360 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
361 #endif
362         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
363         if (qtd == NULL) {
364                 printf("unable to allocate TDs\n");
365                 return -1;
366         }
367
368         memset(qh, 0, sizeof(struct QH));
369         memset(qtd, 0, qtd_count * sizeof(*qtd));
370
371         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
372
373         /*
374          * Setup QH (3.6 in ehci-r10.pdf)
375          *
376          *   qh_link ................. 03-00 H
377          *   qh_endpt1 ............... 07-04 H
378          *   qh_endpt2 ............... 0B-08 H
379          * - qh_curtd
380          *   qh_overlay.qt_next ...... 13-10 H
381          * - qh_overlay.qt_altnext
382          */
383         qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
384         c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
385         maxpacket = usb_maxpacket(dev, pipe);
386         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
387                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
388                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
389                 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
390                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
391                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
392         qh->qh_endpt1 = cpu_to_hc32(endpt);
393         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
394                 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
395                 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
396         qh->qh_endpt2 = cpu_to_hc32(endpt);
397         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
398         qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
399
400         tdp = &qh->qh_overlay.qt_next;
401
402         if (req != NULL) {
403                 /*
404                  * Setup request qTD (3.5 in ehci-r10.pdf)
405                  *
406                  *   qt_next ................ 03-00 H
407                  *   qt_altnext ............. 07-04 H
408                  *   qt_token ............... 0B-08 H
409                  *
410                  *   [ buffer, buffer_hi ] loaded with "req".
411                  */
412                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
413                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
414                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
415                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
416                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
417                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
418                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
419                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
420                         printf("unable to construct SETUP TD\n");
421                         goto fail;
422                 }
423                 /* Update previous qTD! */
424                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
425                 tdp = &qtd[qtd_counter++].qt_next;
426                 toggle = 1;
427         }
428
429         if (length > 0 || req == NULL) {
430                 uint8_t *buf_ptr = buffer;
431                 int left_length = length;
432
433                 do {
434                         /*
435                          * Determine the size of this qTD transfer. By default,
436                          * QT_BUFFER_CNT full pages can be used.
437                          */
438                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
439                         /*
440                          * However, if the input buffer is not page-aligned, the
441                          * portion of the first page before the buffer start
442                          * offset within that page is unusable.
443                          */
444                         xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
445                         /*
446                          * In order to keep each packet within a qTD transfer,
447                          * align the qTD transfer size to PKT_ALIGN.
448                          */
449                         xfr_bytes &= ~(PKT_ALIGN - 1);
450                         /*
451                          * This transfer may be shorter than the available qTD
452                          * transfer size that has just been computed.
453                          */
454                         xfr_bytes = min(xfr_bytes, left_length);
455
456                         /*
457                          * Setup request qTD (3.5 in ehci-r10.pdf)
458                          *
459                          *   qt_next ................ 03-00 H
460                          *   qt_altnext ............. 07-04 H
461                          *   qt_token ............... 0B-08 H
462                          *
463                          *   [ buffer, buffer_hi ] loaded with "buffer".
464                          */
465                         qtd[qtd_counter].qt_next =
466                                         cpu_to_hc32(QT_NEXT_TERMINATE);
467                         qtd[qtd_counter].qt_altnext =
468                                         cpu_to_hc32(QT_NEXT_TERMINATE);
469                         token = QT_TOKEN_DT(toggle) |
470                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
471                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
472                                 QT_TOKEN_CERR(3) |
473                                 QT_TOKEN_PID(usb_pipein(pipe) ?
474                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
475                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
476                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
477                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
478                                                 xfr_bytes)) {
479                                 printf("unable to construct DATA TD\n");
480                                 goto fail;
481                         }
482                         /* Update previous qTD! */
483                         *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
484                         tdp = &qtd[qtd_counter++].qt_next;
485                         /*
486                          * Data toggle has to be adjusted since the qTD transfer
487                          * size is not always an even multiple of
488                          * wMaxPacketSize.
489                          */
490                         if ((xfr_bytes / maxpacket) & 1)
491                                 toggle ^= 1;
492                         buf_ptr += xfr_bytes;
493                         left_length -= xfr_bytes;
494                 } while (left_length > 0);
495         }
496
497         if (req != NULL) {
498                 /*
499                  * Setup request qTD (3.5 in ehci-r10.pdf)
500                  *
501                  *   qt_next ................ 03-00 H
502                  *   qt_altnext ............. 07-04 H
503                  *   qt_token ............... 0B-08 H
504                  */
505                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
506                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
507                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
508                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
509                         QT_TOKEN_PID(usb_pipein(pipe) ?
510                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
511                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
512                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
513                 /* Update previous qTD! */
514                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
515                 tdp = &qtd[qtd_counter++].qt_next;
516         }
517
518         ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
519
520         /* Flush dcache */
521         flush_dcache_range((uint32_t)&ctrl->qh_list,
522                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
523         flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
524         flush_dcache_range((uint32_t)qtd,
525                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
526
527         /* Set async. queue head pointer. */
528         ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
529
530         usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
531         ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
532
533         /* Enable async. schedule. */
534         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
535         cmd |= CMD_ASE;
536         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
537
538         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
539                         100 * 1000);
540         if (ret < 0) {
541                 printf("EHCI fail timeout STS_ASS set\n");
542                 goto fail;
543         }
544
545         /* Wait for TDs to be processed. */
546         ts = get_timer(0);
547         vtd = &qtd[qtd_counter - 1];
548         timeout = USB_TIMEOUT_MS(pipe);
549         do {
550                 /* Invalidate dcache */
551                 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
552                         ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
553                 invalidate_dcache_range((uint32_t)qh,
554                         ALIGN_END_ADDR(struct QH, qh, 1));
555                 invalidate_dcache_range((uint32_t)qtd,
556                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
557
558                 token = hc32_to_cpu(vtd->qt_token);
559                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
560                         break;
561                 WATCHDOG_RESET();
562         } while (get_timer(ts) < timeout);
563
564         /*
565          * Invalidate the memory area occupied by buffer
566          * Don't try to fix the buffer alignment, if it isn't properly
567          * aligned it's upper layer's fault so let invalidate_dcache_range()
568          * vow about it. But we have to fix the length as it's actual
569          * transfer length and can be unaligned. This is potentially
570          * dangerous operation, it's responsibility of the calling
571          * code to make sure enough space is reserved.
572          */
573         invalidate_dcache_range((uint32_t)buffer,
574                 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
575
576         /* Check that the TD processing happened */
577         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
578                 printf("EHCI timed out on TD - token=%#x\n", token);
579
580         /* Disable async schedule. */
581         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
582         cmd &= ~CMD_ASE;
583         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
584
585         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
586                         100 * 1000);
587         if (ret < 0) {
588                 printf("EHCI fail timeout STS_ASS reset\n");
589                 goto fail;
590         }
591
592         token = hc32_to_cpu(qh->qh_overlay.qt_token);
593         if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
594                 debug("TOKEN=%#x\n", token);
595                 switch (QT_TOKEN_GET_STATUS(token) &
596                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
597                 case 0:
598                         toggle = QT_TOKEN_GET_DT(token);
599                         usb_settoggle(dev, usb_pipeendpoint(pipe),
600                                        usb_pipeout(pipe), toggle);
601                         dev->status = 0;
602                         break;
603                 case QT_TOKEN_STATUS_HALTED:
604                         dev->status = USB_ST_STALLED;
605                         break;
606                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
607                 case QT_TOKEN_STATUS_DATBUFERR:
608                         dev->status = USB_ST_BUF_ERR;
609                         break;
610                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
611                 case QT_TOKEN_STATUS_BABBLEDET:
612                         dev->status = USB_ST_BABBLE_DET;
613                         break;
614                 default:
615                         dev->status = USB_ST_CRC_ERR;
616                         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
617                                 dev->status |= USB_ST_STALLED;
618                         break;
619                 }
620                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
621         } else {
622                 dev->act_len = 0;
623 #ifndef CONFIG_USB_EHCI_FARADAY
624                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
625                       dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
626                       ehci_readl(&ctrl->hcor->or_portsc[0]),
627                       ehci_readl(&ctrl->hcor->or_portsc[1]));
628 #endif
629         }
630
631         free(qtd);
632         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
633
634 fail:
635         free(qtd);
636         return -1;
637 }
638
639 __weak uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
640 {
641         if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
642                 /* Printing the message would cause a scan failure! */
643                 debug("The request port(%u) is not configured\n", port);
644                 return NULL;
645         }
646
647         return (uint32_t *)&hcor->or_portsc[port];
648 }
649
650 int
651 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
652                  int length, struct devrequest *req)
653 {
654         uint8_t tmpbuf[4];
655         u16 typeReq;
656         void *srcptr = NULL;
657         int len, srclen;
658         uint32_t reg;
659         uint32_t *status_reg;
660         int port = le16_to_cpu(req->index) & 0xff;
661         struct ehci_ctrl *ctrl = dev->controller;
662
663         srclen = 0;
664
665         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
666               req->request, req->request,
667               req->requesttype, req->requesttype,
668               le16_to_cpu(req->value), le16_to_cpu(req->index));
669
670         typeReq = req->request | req->requesttype << 8;
671
672         switch (typeReq) {
673         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
674         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
675         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
676                 status_reg = ehci_get_portsc_register(ctrl->hcor, port - 1);
677                 if (!status_reg)
678                         return -1;
679                 break;
680         default:
681                 status_reg = NULL;
682                 break;
683         }
684
685         switch (typeReq) {
686         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
687                 switch (le16_to_cpu(req->value) >> 8) {
688                 case USB_DT_DEVICE:
689                         debug("USB_DT_DEVICE request\n");
690                         srcptr = &descriptor.device;
691                         srclen = descriptor.device.bLength;
692                         break;
693                 case USB_DT_CONFIG:
694                         debug("USB_DT_CONFIG config\n");
695                         srcptr = &descriptor.config;
696                         srclen = descriptor.config.bLength +
697                                         descriptor.interface.bLength +
698                                         descriptor.endpoint.bLength;
699                         break;
700                 case USB_DT_STRING:
701                         debug("USB_DT_STRING config\n");
702                         switch (le16_to_cpu(req->value) & 0xff) {
703                         case 0: /* Language */
704                                 srcptr = "\4\3\1\0";
705                                 srclen = 4;
706                                 break;
707                         case 1: /* Vendor */
708                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
709                                 srclen = 14;
710                                 break;
711                         case 2: /* Product */
712                                 srcptr = "\52\3E\0H\0C\0I\0 "
713                                          "\0H\0o\0s\0t\0 "
714                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
715                                 srclen = 42;
716                                 break;
717                         default:
718                                 debug("unknown value DT_STRING %x\n",
719                                         le16_to_cpu(req->value));
720                                 goto unknown;
721                         }
722                         break;
723                 default:
724                         debug("unknown value %x\n", le16_to_cpu(req->value));
725                         goto unknown;
726                 }
727                 break;
728         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
729                 switch (le16_to_cpu(req->value) >> 8) {
730                 case USB_DT_HUB:
731                         debug("USB_DT_HUB config\n");
732                         srcptr = &descriptor.hub;
733                         srclen = descriptor.hub.bLength;
734                         break;
735                 default:
736                         debug("unknown value %x\n", le16_to_cpu(req->value));
737                         goto unknown;
738                 }
739                 break;
740         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
741                 debug("USB_REQ_SET_ADDRESS\n");
742                 ctrl->rootdev = le16_to_cpu(req->value);
743                 break;
744         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
745                 debug("USB_REQ_SET_CONFIGURATION\n");
746                 /* Nothing to do */
747                 break;
748         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
749                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
750                 tmpbuf[1] = 0;
751                 srcptr = tmpbuf;
752                 srclen = 2;
753                 break;
754         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
755                 memset(tmpbuf, 0, 4);
756                 reg = ehci_readl(status_reg);
757                 if (reg & EHCI_PS_CS)
758                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
759                 if (reg & EHCI_PS_PE)
760                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
761                 if (reg & EHCI_PS_SUSP)
762                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
763                 if (reg & EHCI_PS_OCA)
764                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
765                 if (reg & EHCI_PS_PR)
766                         tmpbuf[0] |= USB_PORT_STAT_RESET;
767                 if (reg & EHCI_PS_PP)
768                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
769
770                 if (ehci_is_TDI()) {
771                         switch (ehci_get_port_speed(ctrl->hcor, reg)) {
772                         case PORTSC_PSPD_FS:
773                                 break;
774                         case PORTSC_PSPD_LS:
775                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
776                                 break;
777                         case PORTSC_PSPD_HS:
778                         default:
779                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
780                                 break;
781                         }
782                 } else {
783                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
784                 }
785
786                 if (reg & EHCI_PS_CSC)
787                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
788                 if (reg & EHCI_PS_PEC)
789                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
790                 if (reg & EHCI_PS_OCC)
791                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
792                 if (ctrl->portreset & (1 << port))
793                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
794
795                 srcptr = tmpbuf;
796                 srclen = 4;
797                 break;
798         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
799                 reg = ehci_readl(status_reg);
800                 reg &= ~EHCI_PS_CLEAR;
801                 switch (le16_to_cpu(req->value)) {
802                 case USB_PORT_FEAT_ENABLE:
803                         reg |= EHCI_PS_PE;
804                         ehci_writel(status_reg, reg);
805                         break;
806                 case USB_PORT_FEAT_POWER:
807                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
808                                 reg |= EHCI_PS_PP;
809                                 ehci_writel(status_reg, reg);
810                         }
811                         break;
812                 case USB_PORT_FEAT_RESET:
813                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
814                             !ehci_is_TDI() &&
815                             EHCI_PS_IS_LOWSPEED(reg)) {
816                                 /* Low speed device, give up ownership. */
817                                 debug("port %d low speed --> companion\n",
818                                       port - 1);
819                                 reg |= EHCI_PS_PO;
820                                 ehci_writel(status_reg, reg);
821                                 break;
822                         } else {
823                                 int ret;
824
825                                 reg |= EHCI_PS_PR;
826                                 reg &= ~EHCI_PS_PE;
827                                 ehci_writel(status_reg, reg);
828                                 /*
829                                  * caller must wait, then call GetPortStatus
830                                  * usb 2.0 specification say 50 ms resets on
831                                  * root
832                                  */
833                                 ehci_powerup_fixup(status_reg, &reg);
834
835                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
836                                 /*
837                                  * A host controller must terminate the reset
838                                  * and stabilize the state of the port within
839                                  * 2 milliseconds
840                                  */
841                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
842                                                 2 * 1000);
843                                 if (!ret)
844                                         ctrl->portreset |= 1 << port;
845                                 else
846                                         printf("port(%d) reset error\n",
847                                                port - 1);
848                         }
849                         break;
850                 case USB_PORT_FEAT_TEST:
851                         ehci_shutdown(ctrl);
852                         reg &= ~(0xf << 16);
853                         reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
854                         ehci_writel(status_reg, reg);
855                         break;
856                 default:
857                         debug("unknown feature %x\n", le16_to_cpu(req->value));
858                         goto unknown;
859                 }
860                 /* unblock posted writes */
861                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
862                 break;
863         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
864                 reg = ehci_readl(status_reg);
865                 reg &= ~EHCI_PS_CLEAR;
866                 switch (le16_to_cpu(req->value)) {
867                 case USB_PORT_FEAT_ENABLE:
868                         reg &= ~EHCI_PS_PE;
869                         break;
870                 case USB_PORT_FEAT_C_ENABLE:
871                         reg |= EHCI_PS_PE;
872                         break;
873                 case USB_PORT_FEAT_POWER:
874                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
875                                 reg &= ~EHCI_PS_PP;
876                         break;
877                 case USB_PORT_FEAT_C_CONNECTION:
878                         reg |= EHCI_PS_CSC;
879                         break;
880                 case USB_PORT_FEAT_OVER_CURRENT:
881                         reg |= EHCI_PS_OCC;
882                         break;
883                 case USB_PORT_FEAT_C_RESET:
884                         ctrl->portreset &= ~(1 << port);
885                         break;
886                 default:
887                         debug("unknown feature %x\n", le16_to_cpu(req->value));
888                         goto unknown;
889                 }
890                 ehci_writel(status_reg, reg);
891                 /* unblock posted write */
892                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
893                 break;
894         default:
895                 debug("Unknown request\n");
896                 goto unknown;
897         }
898
899         mdelay(1);
900         len = min3(srclen, le16_to_cpu(req->length), length);
901         if (srcptr != NULL && len > 0)
902                 memcpy(buffer, srcptr, len);
903         else
904                 debug("Len is 0\n");
905
906         dev->act_len = len;
907         dev->status = 0;
908         return 0;
909
910 unknown:
911         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
912               req->requesttype, req->request, le16_to_cpu(req->value),
913               le16_to_cpu(req->index), le16_to_cpu(req->length));
914
915         dev->act_len = 0;
916         dev->status = USB_ST_STALLED;
917         return -1;
918 }
919
920 int usb_lowlevel_stop(int index)
921 {
922         ehci_shutdown(&ehcic[index]);
923         return ehci_hcd_stop(index);
924 }
925
926 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
927 {
928         uint32_t reg;
929         uint32_t cmd;
930         struct QH *qh_list;
931         struct QH *periodic;
932         int i;
933         int rc;
934
935         rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
936         if (rc)
937                 return rc;
938         if (init == USB_INIT_DEVICE)
939                 goto done;
940
941         /* EHCI spec section 4.1 */
942         if (ehci_reset(index))
943                 return -1;
944
945 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
946         rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
947         if (rc)
948                 return rc;
949 #endif
950         /* Set the high address word (aka segment) for 64-bit controller */
951         if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
952                 ehci_writel(&ehcic[index].hcor->or_ctrldssegment, 0);
953
954         qh_list = &ehcic[index].qh_list;
955
956         /* Set head of reclaim list */
957         memset(qh_list, 0, sizeof(*qh_list));
958         qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
959         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
960                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
961         qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
962         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
963         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
964         qh_list->qh_overlay.qt_token =
965                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
966
967         flush_dcache_range((uint32_t)qh_list,
968                            ALIGN_END_ADDR(struct QH, qh_list, 1));
969
970         /* Set async. queue head pointer. */
971         ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list);
972
973         /*
974          * Set up periodic list
975          * Step 1: Parent QH for all periodic transfers.
976          */
977         periodic = &ehcic[index].periodic_queue;
978         memset(periodic, 0, sizeof(*periodic));
979         periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
980         periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
981         periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
982
983         flush_dcache_range((uint32_t)periodic,
984                            ALIGN_END_ADDR(struct QH, periodic, 1));
985
986         /*
987          * Step 2: Setup frame-list: Every microframe, USB tries the same list.
988          *         In particular, device specifications on polling frequency
989          *         are disregarded. Keyboards seem to send NAK/NYet reliably
990          *         when polled with an empty buffer.
991          *
992          *         Split Transactions will be spread across microframes using
993          *         S-mask and C-mask.
994          */
995         if (ehcic[index].periodic_list == NULL)
996                 ehcic[index].periodic_list = memalign(4096, 1024 * 4);
997
998         if (!ehcic[index].periodic_list)
999                 return -ENOMEM;
1000         for (i = 0; i < 1024; i++) {
1001                 ehcic[index].periodic_list[i] = (uint32_t)periodic
1002                                                 | QH_LINK_TYPE_QH;
1003         }
1004
1005         flush_dcache_range((uint32_t)ehcic[index].periodic_list,
1006                            ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list,
1007                                           1024));
1008
1009         /* Set periodic list base address */
1010         ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
1011                 (uint32_t)ehcic[index].periodic_list);
1012
1013         reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
1014         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1015         debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1016         /* Port Indicators */
1017         if (HCS_INDICATOR(reg))
1018                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1019                                 | 0x80, &descriptor.hub.wHubCharacteristics);
1020         /* Port Power Control */
1021         if (HCS_PPC(reg))
1022                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1023                                 | 0x01, &descriptor.hub.wHubCharacteristics);
1024
1025         /* Start the host controller. */
1026         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
1027         /*
1028          * Philips, Intel, and maybe others need CMD_RUN before the
1029          * root hub will detect new devices (why?); NEC doesn't
1030          */
1031         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1032         cmd |= CMD_RUN;
1033         ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
1034
1035 #ifndef CONFIG_USB_EHCI_FARADAY
1036         /* take control over the ports */
1037         cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
1038         cmd |= FLAG_CF;
1039         ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
1040 #endif
1041
1042         /* unblock posted write */
1043         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
1044         mdelay(5);
1045         reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
1046         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1047
1048         ehcic[index].rootdev = 0;
1049 done:
1050         *controller = &ehcic[index];
1051         return 0;
1052 }
1053
1054 int
1055 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1056                 int length)
1057 {
1058
1059         if (usb_pipetype(pipe) != PIPE_BULK) {
1060                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1061                 return -1;
1062         }
1063         return ehci_submit_async(dev, pipe, buffer, length, NULL);
1064 }
1065
1066 int
1067 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1068                    int length, struct devrequest *setup)
1069 {
1070         struct ehci_ctrl *ctrl = dev->controller;
1071
1072         if (usb_pipetype(pipe) != PIPE_CONTROL) {
1073                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1074                 return -1;
1075         }
1076
1077         if (usb_pipedevice(pipe) == ctrl->rootdev) {
1078                 if (!ctrl->rootdev)
1079                         dev->speed = USB_SPEED_HIGH;
1080                 return ehci_submit_root(dev, pipe, buffer, length, setup);
1081         }
1082         return ehci_submit_async(dev, pipe, buffer, length, setup);
1083 }
1084
1085 struct int_queue {
1086         struct QH *first;
1087         struct QH *current;
1088         struct QH *last;
1089         struct qTD *tds;
1090 };
1091
1092 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
1093
1094 static int
1095 enable_periodic(struct ehci_ctrl *ctrl)
1096 {
1097         uint32_t cmd;
1098         struct ehci_hcor *hcor = ctrl->hcor;
1099         int ret;
1100
1101         cmd = ehci_readl(&hcor->or_usbcmd);
1102         cmd |= CMD_PSE;
1103         ehci_writel(&hcor->or_usbcmd, cmd);
1104
1105         ret = handshake((uint32_t *)&hcor->or_usbsts,
1106                         STS_PSS, STS_PSS, 100 * 1000);
1107         if (ret < 0) {
1108                 printf("EHCI failed: timeout when enabling periodic list\n");
1109                 return -ETIMEDOUT;
1110         }
1111         udelay(1000);
1112         return 0;
1113 }
1114
1115 static int
1116 disable_periodic(struct ehci_ctrl *ctrl)
1117 {
1118         uint32_t cmd;
1119         struct ehci_hcor *hcor = ctrl->hcor;
1120         int ret;
1121
1122         cmd = ehci_readl(&hcor->or_usbcmd);
1123         cmd &= ~CMD_PSE;
1124         ehci_writel(&hcor->or_usbcmd, cmd);
1125
1126         ret = handshake((uint32_t *)&hcor->or_usbsts,
1127                         STS_PSS, 0, 100 * 1000);
1128         if (ret < 0) {
1129                 printf("EHCI failed: timeout when disabling periodic list\n");
1130                 return -ETIMEDOUT;
1131         }
1132         return 0;
1133 }
1134
1135 static int periodic_schedules;
1136
1137 struct int_queue *
1138 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1139                  int elementsize, void *buffer)
1140 {
1141         struct ehci_ctrl *ctrl = dev->controller;
1142         struct int_queue *result = NULL;
1143         int i;
1144
1145         debug("Enter create_int_queue\n");
1146         if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1147                 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1148                 return NULL;
1149         }
1150
1151         /* limit to 4 full pages worth of data -
1152          * we can safely fit them in a single TD,
1153          * no matter the alignment
1154          */
1155         if (elementsize >= 16384) {
1156                 debug("too large elements for interrupt transfers\n");
1157                 return NULL;
1158         }
1159
1160         result = malloc(sizeof(*result));
1161         if (!result) {
1162                 debug("ehci intr queue: out of memory\n");
1163                 goto fail1;
1164         }
1165         result->first = memalign(32, sizeof(struct QH) * queuesize);
1166         if (!result->first) {
1167                 debug("ehci intr queue: out of memory\n");
1168                 goto fail2;
1169         }
1170         result->current = result->first;
1171         result->last = result->first + queuesize - 1;
1172         result->tds = memalign(32, sizeof(struct qTD) * queuesize);
1173         if (!result->tds) {
1174                 debug("ehci intr queue: out of memory\n");
1175                 goto fail3;
1176         }
1177         memset(result->first, 0, sizeof(struct QH) * queuesize);
1178         memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1179
1180         for (i = 0; i < queuesize; i++) {
1181                 struct QH *qh = result->first + i;
1182                 struct qTD *td = result->tds + i;
1183                 void **buf = &qh->buffer;
1184
1185                 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH;
1186                 if (i == queuesize - 1)
1187                         qh->qh_link = QH_LINK_TERMINATE;
1188
1189                 qh->qh_overlay.qt_next = (uint32_t)td;
1190                 qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE;
1191                 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
1192                         (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1193                         (1 << 14) |
1194                         QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1195                         (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1196                         (usb_pipedevice(pipe) << 0);
1197                 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */
1198                         (1 << 0); /* S-mask: microframe 0 */
1199                 if (dev->speed == USB_SPEED_LOW ||
1200                                 dev->speed == USB_SPEED_FULL) {
1201                         debug("TT: port: %d, hub address: %d\n",
1202                                 dev->portnr, dev->parent->devnum);
1203                         qh->qh_endpt2 |= (dev->portnr << 23) |
1204                                 (dev->parent->devnum << 16) |
1205                                 (0x1c << 8); /* C-mask: microframes 2-4 */
1206                 }
1207
1208                 td->qt_next = QT_NEXT_TERMINATE;
1209                 td->qt_altnext = QT_NEXT_TERMINATE;
1210                 debug("communication direction is '%s'\n",
1211                       usb_pipein(pipe) ? "in" : "out");
1212                 td->qt_token = (elementsize << 16) |
1213                         ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1214                         0x80; /* active */
1215                 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize;
1216                 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff;
1217                 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff;
1218                 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff;
1219                 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff;
1220
1221                 *buf = buffer + i * elementsize;
1222         }
1223
1224         flush_dcache_range((uint32_t)buffer,
1225                            ALIGN_END_ADDR(char, buffer,
1226                                           queuesize * elementsize));
1227         flush_dcache_range((uint32_t)result->first,
1228                            ALIGN_END_ADDR(struct QH, result->first,
1229                                           queuesize));
1230         flush_dcache_range((uint32_t)result->tds,
1231                            ALIGN_END_ADDR(struct qTD, result->tds,
1232                                           queuesize));
1233
1234         if (disable_periodic(ctrl) < 0) {
1235                 debug("FATAL: periodic should never fail, but did");
1236                 goto fail3;
1237         }
1238
1239         /* hook up to periodic list */
1240         struct QH *list = &ctrl->periodic_queue;
1241         result->last->qh_link = list->qh_link;
1242         list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
1243
1244         flush_dcache_range((uint32_t)result->last,
1245                            ALIGN_END_ADDR(struct QH, result->last, 1));
1246         flush_dcache_range((uint32_t)list,
1247                            ALIGN_END_ADDR(struct QH, list, 1));
1248
1249         if (enable_periodic(ctrl) < 0) {
1250                 debug("FATAL: periodic should never fail, but did");
1251                 goto fail3;
1252         }
1253         periodic_schedules++;
1254
1255         debug("Exit create_int_queue\n");
1256         return result;
1257 fail3:
1258         if (result->tds)
1259                 free(result->tds);
1260 fail2:
1261         if (result->first)
1262                 free(result->first);
1263         if (result)
1264                 free(result);
1265 fail1:
1266         return NULL;
1267 }
1268
1269 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1270 {
1271         struct QH *cur = queue->current;
1272
1273         /* depleted queue */
1274         if (cur == NULL) {
1275                 debug("Exit poll_int_queue with completed queue\n");
1276                 return NULL;
1277         }
1278         /* still active */
1279         invalidate_dcache_range((uint32_t)cur,
1280                                 ALIGN_END_ADDR(struct QH, cur, 1));
1281         if (cur->qh_overlay.qt_token & 0x80) {
1282                 debug("Exit poll_int_queue with no completed intr transfer. "
1283                       "token is %x\n", cur->qh_overlay.qt_token);
1284                 return NULL;
1285         }
1286         if (!(cur->qh_link & QH_LINK_TERMINATE))
1287                 queue->current++;
1288         else
1289                 queue->current = NULL;
1290         debug("Exit poll_int_queue with completed intr transfer. "
1291               "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token,
1292               &cur->qh_overlay.qt_token, queue->first);
1293         return cur->buffer;
1294 }
1295
1296 /* Do not free buffers associated with QHs, they're owned by someone else */
1297 int
1298 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1299 {
1300         struct ehci_ctrl *ctrl = dev->controller;
1301         int result = -1;
1302         unsigned long timeout;
1303
1304         if (disable_periodic(ctrl) < 0) {
1305                 debug("FATAL: periodic should never fail, but did");
1306                 goto out;
1307         }
1308         periodic_schedules--;
1309
1310         struct QH *cur = &ctrl->periodic_queue;
1311         timeout = get_timer(0) + 500; /* abort after 500ms */
1312         while (!(cur->qh_link & QH_LINK_TERMINATE)) {
1313                 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1314                 if (NEXT_QH(cur) == queue->first) {
1315                         debug("found candidate. removing from chain\n");
1316                         cur->qh_link = queue->last->qh_link;
1317                         result = 0;
1318                         break;
1319                 }
1320                 cur = NEXT_QH(cur);
1321                 if (get_timer(0) > timeout) {
1322                         printf("Timeout destroying interrupt endpoint queue\n");
1323                         result = -1;
1324                         goto out;
1325                 }
1326         }
1327
1328         if (periodic_schedules > 0) {
1329                 result = enable_periodic(ctrl);
1330                 if (result < 0)
1331                         debug("FATAL: periodic should never fail, but did");
1332         }
1333
1334 out:
1335         free(queue->tds);
1336         free(queue->first);
1337         free(queue);
1338
1339         return result;
1340 }
1341
1342 int
1343 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1344                int length, int interval)
1345 {
1346         void *backbuffer;
1347         struct int_queue *queue;
1348         unsigned long timeout;
1349         int result = 0, ret;
1350
1351         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1352               dev, pipe, buffer, length, interval);
1353
1354         /*
1355          * Interrupt transfers requiring several transactions are not supported
1356          * because bInterval is ignored.
1357          *
1358          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1359          * <= PKT_ALIGN if several qTDs are required, while the USB
1360          * specification does not constrain this for interrupt transfers. That
1361          * means that ehci_submit_async() would support interrupt transfers
1362          * requiring several transactions only as long as the transfer size does
1363          * not require more than a single qTD.
1364          */
1365         if (length > usb_maxpacket(dev, pipe)) {
1366                 printf("%s: Interrupt transfers requiring several "
1367                         "transactions are not supported.\n", __func__);
1368                 return -1;
1369         }
1370
1371         queue = create_int_queue(dev, pipe, 1, length, buffer);
1372
1373         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1374         while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1375                 if (get_timer(0) > timeout) {
1376                         printf("Timeout poll on interrupt endpoint\n");
1377                         result = -ETIMEDOUT;
1378                         break;
1379                 }
1380
1381         if (backbuffer != buffer) {
1382                 debug("got wrong buffer back (%x instead of %x)\n",
1383                       (uint32_t)backbuffer, (uint32_t)buffer);
1384                 return -EINVAL;
1385         }
1386
1387         invalidate_dcache_range((uint32_t)buffer,
1388                                 ALIGN_END_ADDR(char, buffer, length));
1389
1390         ret = destroy_int_queue(dev, queue);
1391         if (ret < 0)
1392                 return ret;
1393
1394         /* everything worked out fine */
1395         return result;
1396 }