drivers/usb/host/ehci-hcd.c

   1 /*-
   2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   3  * Copyright (c) 2008, Excito Elektronik i Skåne AB
   4  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   5  *
   6  * All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <asm/byteorder.h>
  25 #include <usb.h>
  26 #include <asm/io.h>
  27 #include <malloc.h>
  28 #include <watchdog.h>
  29
  30 #include "ehci.h"
  31
  32 int rootdev;
  33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  34 volatile struct ehci_hcor *hcor;
  35
  36 static uint16_t portreset;
  37 DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
  38
  39 #define ALIGN_END_ADDR(type, ptr, size)                 \
  40         ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  41
  42 static struct descriptor {
  43         struct usb_hub_descriptor hub;
  44         struct usb_device_descriptor device;
  45         struct usb_linux_config_descriptor config;
  46         struct usb_linux_interface_descriptor interface;
  47         struct usb_endpoint_descriptor endpoint;
  48 }  __attribute__ ((packed)) descriptor = {
  49         {
  50                 0x8,            /* bDescLength */
  51                 0x29,           /* bDescriptorType: hub descriptor */
  52                 2,              /* bNrPorts -- runtime modified */
  53                 0,              /* wHubCharacteristics */
  54                 10,             /* bPwrOn2PwrGood */
  55                 0,              /* bHubCntrCurrent */
  56                 {},             /* Device removable */
  57                 {}              /* at most 7 ports! XXX */
  58         },
  59         {
  60                 0x12,           /* bLength */
  61                 1,              /* bDescriptorType: UDESC_DEVICE */
  62                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  63                 9,              /* bDeviceClass: UDCLASS_HUB */
  64                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
  65                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  66                 64,             /* bMaxPacketSize: 64 bytes */
  67                 0x0000,         /* idVendor */
  68                 0x0000,         /* idProduct */
  69                 cpu_to_le16(0x0100), /* bcdDevice */
  70                 1,              /* iManufacturer */
  71                 2,              /* iProduct */
  72                 0,              /* iSerialNumber */
  73                 1               /* bNumConfigurations: 1 */
  74         },
  75         {
  76                 0x9,
  77                 2,              /* bDescriptorType: UDESC_CONFIG */
  78                 cpu_to_le16(0x19),
  79                 1,              /* bNumInterface */
  80                 1,              /* bConfigurationValue */
  81                 0,              /* iConfiguration */
  82                 0x40,           /* bmAttributes: UC_SELF_POWER */
  83                 0               /* bMaxPower */
  84         },
  85         {
  86                 0x9,            /* bLength */
  87                 4,              /* bDescriptorType: UDESC_INTERFACE */
  88                 0,              /* bInterfaceNumber */
  89                 0,              /* bAlternateSetting */
  90                 1,              /* bNumEndpoints */
  91                 9,              /* bInterfaceClass: UICLASS_HUB */
  92                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
  93                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  94                 0               /* iInterface */
  95         },
  96         {
  97                 0x7,            /* bLength */
  98                 5,              /* bDescriptorType: UDESC_ENDPOINT */
  99                 0x81,           /* bEndpointAddress:
 100                                  * UE_DIR_IN | EHCI_INTR_ENDPT
 101                                  */
 102                 3,              /* bmAttributes: UE_INTERRUPT */
 103                 8,              /* wMaxPacketSize */
 104                 255             /* bInterval */
 105         },
 106 };
 107
 108 #if defined(CONFIG_EHCI_IS_TDI)
 109 #define ehci_is_TDI()   (1)
 110 #else
 111 #define ehci_is_TDI()   (0)
 112 #endif
 113
 114 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 115 {
 116         mdelay(50);
 117 }
 118
 119 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 120         __attribute__((weak, alias("__ehci_powerup_fixup")));
 121
 122 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 123 {
 124         uint32_t result;
 125         do {
 126                 result = ehci_readl(ptr);
 127                 udelay(5);
 128                 if (result == ~(uint32_t)0)
 129                         return -1;
 130                 result &= mask;
 131                 if (result == done)
 132                         return 0;
 133                 usec--;
 134         } while (usec > 0);
 135         return -1;
 136 }
 137
 138 static int ehci_reset(void)
 139 {
 140         uint32_t cmd;
 141         uint32_t tmp;
 142         uint32_t *reg_ptr;
 143         int ret = 0;
 144
 145         cmd = ehci_readl(&hcor->or_usbcmd);
 146         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
 147         ehci_writel(&hcor->or_usbcmd, cmd);
 148         ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
 149         if (ret < 0) {
 150                 printf("EHCI fail to reset\n");
 151                 goto out;
 152         }
 153
 154         if (ehci_is_TDI()) {
 155                 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
 156                 tmp = ehci_readl(reg_ptr);
 157                 tmp |= USBMODE_CM_HC;
 158 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
 159                 tmp |= USBMODE_BE;
 160 #endif
 161                 ehci_writel(reg_ptr, tmp);
 162         }
 163
 164 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
 165         cmd = ehci_readl(&hcor->or_txfilltuning);
 166         cmd &= ~TXFIFO_THRESH_MASK;
 167         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
 168         ehci_writel(&hcor->or_txfilltuning, cmd);
 169 #endif
 170 out:
 171         return ret;
 172 }
 173
 174 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 175 {
 176         uint32_t delta, next;
 177         uint32_t addr = (uint32_t)buf;
 178         int idx;
 179
 180         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
 181                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
 182
 183         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
 184
 185         idx = 0;
 186         while (idx < QT_BUFFER_CNT) {
 187                 td->qt_buffer[idx] = cpu_to_hc32(addr);
 188                 td->qt_buffer_hi[idx] = 0;
 189                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
 190                 delta = next - addr;
 191                 if (delta >= sz)
 192                         break;
 193                 sz -= delta;
 194                 addr = next;
 195                 idx++;
 196         }
 197
 198         if (idx == QT_BUFFER_CNT) {
 199                 printf("out of buffer pointers (%u bytes left)\n", sz);
 200                 return -1;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static int
 207 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 208                    int length, struct devrequest *req)
 209 {
 210         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
 211         struct qTD *qtd;
 212         int qtd_count = 0;
 213         int qtd_counter = 0;
 214
 215         volatile struct qTD *vtd;
 216         unsigned long ts;
 217         uint32_t *tdp;
 218         uint32_t endpt, maxpacket, token, usbsts;
 219         uint32_t c, toggle;
 220         uint32_t cmd;
 221         int timeout;
 222         int ret = 0;
 223
 224         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
 225               buffer, length, req);
 226         if (req != NULL)
 227                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
 228                       req->request, req->request,
 229                       req->requesttype, req->requesttype,
 230                       le16_to_cpu(req->value), le16_to_cpu(req->value),
 231                       le16_to_cpu(req->index));
 232
 233 #define PKT_ALIGN       512
 234         /*
 235          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
 236          * described by a transfer descriptor (the qTD). The qTDs form a linked
 237          * list with a queue head (QH).
 238          *
 239          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
 240          * have its beginning in a qTD transfer and its end in the following
 241          * one, so the qTD transfer lengths have to be chosen accordingly.
 242          *
 243          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
 244          * single pages. The first data buffer can start at any offset within a
 245          * page (not considering the cache-line alignment issues), while the
 246          * following buffers must be page-aligned. There is no alignment
 247          * constraint on the size of a qTD transfer.
 248          */
 249         if (req != NULL)
 250                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
 251                 qtd_count += 1 + 1;
 252         if (length > 0 || req == NULL) {
 253                 /*
 254                  * Determine the qTD transfer size that will be used for the
 255                  * data payload (not considering the first qTD transfer, which
 256                  * may be longer or shorter, and the final one, which may be
 257                  * shorter).
 258                  *
 259                  * In order to keep each packet within a qTD transfer, the qTD
 260                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
 261                  * wMaxPacketSize (except in some cases for interrupt transfers,
 262                  * see comment in submit_int_msg()).
 263                  *
 264                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
 265                  * QT_BUFFER_CNT full pages will be used.
 266                  */
 267                 int xfr_sz = QT_BUFFER_CNT;
 268                 /*
 269                  * However, if the input buffer is not aligned to PKT_ALIGN, the
 270                  * qTD transfer size will be one page shorter, and the first qTD
 271                  * data buffer of each transfer will be page-unaligned.
 272                  */
 273                 if ((uint32_t)buffer & (PKT_ALIGN - 1))
 274                         xfr_sz--;
 275                 /* Convert the qTD transfer size to bytes. */
 276                 xfr_sz *= EHCI_PAGE_SIZE;
 277                 /*
 278                  * Approximate by excess the number of qTDs that will be
 279                  * required for the data payload. The exact formula is way more
 280                  * complicated and saves at most 2 qTDs, i.e. a total of 128
 281                  * bytes.
 282                  */
 283                 qtd_count += 2 + length / xfr_sz;
 284         }
 285 /*
 286  * Threshold value based on the worst-case total size of the allocated qTDs for
 287  * a mass-storage transfer of 65535 blocks of 512 bytes.
 288  */
 289 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
 290 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
 291 #endif
 292         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
 293         if (qtd == NULL) {
 294                 printf("unable to allocate TDs\n");
 295                 return -1;
 296         }
 297
 298         memset(qh, 0, sizeof(struct QH));
 299         memset(qtd, 0, qtd_count * sizeof(*qtd));
 300
 301         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
 302
 303         /*
 304          * Setup QH (3.6 in ehci-r10.pdf)
 305          *
 306          *   qh_link ................. 03-00 H
 307          *   qh_endpt1 ............... 07-04 H
 308          *   qh_endpt2 ............... 0B-08 H
 309          * - qh_curtd
 310          *   qh_overlay.qt_next ...... 13-10 H
 311          * - qh_overlay.qt_altnext
 312          */
 313         qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
 314         c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
 315         maxpacket = usb_maxpacket(dev, pipe);
 316         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
 317                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
 318                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
 319                 QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
 320                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
 321                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
 322         qh->qh_endpt1 = cpu_to_hc32(endpt);
 323         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
 324                 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
 325                 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
 326         qh->qh_endpt2 = cpu_to_hc32(endpt);
 327         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 328
 329         tdp = &qh->qh_overlay.qt_next;
 330
 331         if (req != NULL) {
 332                 /*
 333                  * Setup request qTD (3.5 in ehci-r10.pdf)
 334                  *
 335                  *   qt_next ................ 03-00 H
 336                  *   qt_altnext ............. 07-04 H
 337                  *   qt_token ............... 0B-08 H
 338                  *
 339                  *   [ buffer, buffer_hi ] loaded with "req".
 340                  */
 341                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 342                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 343                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
 344                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 345                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
 346                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 347                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 348                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
 349                         printf("unable to construct SETUP TD\n");
 350                         goto fail;
 351                 }
 352                 /* Update previous qTD! */
 353                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 354                 tdp = &qtd[qtd_counter++].qt_next;
 355                 toggle = 1;
 356         }
 357
 358         if (length > 0 || req == NULL) {
 359                 uint8_t *buf_ptr = buffer;
 360                 int left_length = length;
 361
 362                 do {
 363                         /*
 364                          * Determine the size of this qTD transfer. By default,
 365                          * QT_BUFFER_CNT full pages can be used.
 366                          */
 367                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
 368                         /*
 369                          * However, if the input buffer is not page-aligned, the
 370                          * portion of the first page before the buffer start
 371                          * offset within that page is unusable.
 372                          */
 373                         xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
 374                         /*
 375                          * In order to keep each packet within a qTD transfer,
 376                          * align the qTD transfer size to PKT_ALIGN.
 377                          */
 378                         xfr_bytes &= ~(PKT_ALIGN - 1);
 379                         /*
 380                          * This transfer may be shorter than the available qTD
 381                          * transfer size that has just been computed.
 382                          */
 383                         xfr_bytes = min(xfr_bytes, left_length);
 384
 385                         /*
 386                          * Setup request qTD (3.5 in ehci-r10.pdf)
 387                          *
 388                          *   qt_next ................ 03-00 H
 389                          *   qt_altnext ............. 07-04 H
 390                          *   qt_token ............... 0B-08 H
 391                          *
 392                          *   [ buffer, buffer_hi ] loaded with "buffer".
 393                          */
 394                         qtd[qtd_counter].qt_next =
 395                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 396                         qtd[qtd_counter].qt_altnext =
 397                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 398                         token = QT_TOKEN_DT(toggle) |
 399                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
 400                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
 401                                 QT_TOKEN_CERR(3) |
 402                                 QT_TOKEN_PID(usb_pipein(pipe) ?
 403                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
 404                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 405                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 406                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
 407                                                 xfr_bytes)) {
 408                                 printf("unable to construct DATA TD\n");
 409                                 goto fail;
 410                         }
 411                         /* Update previous qTD! */
 412                         *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 413                         tdp = &qtd[qtd_counter++].qt_next;
 414                         /*
 415                          * Data toggle has to be adjusted since the qTD transfer
 416                          * size is not always an even multiple of
 417                          * wMaxPacketSize.
 418                          */
 419                         if ((xfr_bytes / maxpacket) & 1)
 420                                 toggle ^= 1;
 421                         buf_ptr += xfr_bytes;
 422                         left_length -= xfr_bytes;
 423                 } while (left_length > 0);
 424         }
 425
 426         if (req != NULL) {
 427                 /*
 428                  * Setup request qTD (3.5 in ehci-r10.pdf)
 429                  *
 430                  *   qt_next ................ 03-00 H
 431                  *   qt_altnext ............. 07-04 H
 432                  *   qt_token ............... 0B-08 H
 433                  */
 434                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 435                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 436                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
 437                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 438                         QT_TOKEN_PID(usb_pipein(pipe) ?
 439                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
 440                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 441                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 442                 /* Update previous qTD! */
 443                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 444                 tdp = &qtd[qtd_counter++].qt_next;
 445         }
 446
 447         qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
 448
 449         /* Flush dcache */
 450         flush_dcache_range((uint32_t)qh_list,
 451                 ALIGN_END_ADDR(struct QH, qh_list, 1));
 452         flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
 453         flush_dcache_range((uint32_t)qtd,
 454                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 455
 456         /* Set async. queue head pointer. */
 457         ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
 458
 459         usbsts = ehci_readl(&hcor->or_usbsts);
 460         ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
 461
 462         /* Enable async. schedule. */
 463         cmd = ehci_readl(&hcor->or_usbcmd);
 464         cmd |= CMD_ASE;
 465         ehci_writel(&hcor->or_usbcmd, cmd);
 466
 467         ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
 468                         100 * 1000);
 469         if (ret < 0) {
 470                 printf("EHCI fail timeout STS_ASS set\n");
 471                 goto fail;
 472         }
 473
 474         /* Wait for TDs to be processed. */
 475         ts = get_timer(0);
 476         vtd = &qtd[qtd_counter - 1];
 477         timeout = USB_TIMEOUT_MS(pipe);
 478         do {
 479                 /* Invalidate dcache */
 480                 invalidate_dcache_range((uint32_t)qh_list,
 481                         ALIGN_END_ADDR(struct QH, qh_list, 1));
 482                 invalidate_dcache_range((uint32_t)qh,
 483                         ALIGN_END_ADDR(struct QH, qh, 1));
 484                 invalidate_dcache_range((uint32_t)qtd,
 485                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 486
 487                 token = hc32_to_cpu(vtd->qt_token);
 488                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
 489                         break;
 490                 WATCHDOG_RESET();
 491         } while (get_timer(ts) < timeout);
 492
 493         /*
 494          * Invalidate the memory area occupied by buffer
 495          * Don't try to fix the buffer alignment, if it isn't properly
 496          * aligned it's upper layer's fault so let invalidate_dcache_range()
 497          * vow about it. But we have to fix the length as it's actual
 498          * transfer length and can be unaligned. This is potentially
 499          * dangerous operation, it's responsibility of the calling
 500          * code to make sure enough space is reserved.
 501          */
 502         invalidate_dcache_range((uint32_t)buffer,
 503                 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
 504
 505         /* Check that the TD processing happened */
 506         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
 507                 printf("EHCI timed out on TD - token=%#x\n", token);
 508
 509         /* Disable async schedule. */
 510         cmd = ehci_readl(&hcor->or_usbcmd);
 511         cmd &= ~CMD_ASE;
 512         ehci_writel(&hcor->or_usbcmd, cmd);
 513
 514         ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
 515                         100 * 1000);
 516         if (ret < 0) {
 517                 printf("EHCI fail timeout STS_ASS reset\n");
 518                 goto fail;
 519         }
 520
 521         token = hc32_to_cpu(qh->qh_overlay.qt_token);
 522         if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
 523                 debug("TOKEN=%#x\n", token);
 524                 switch (QT_TOKEN_GET_STATUS(token) &
 525                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
 526                 case 0:
 527                         toggle = QT_TOKEN_GET_DT(token);
 528                         usb_settoggle(dev, usb_pipeendpoint(pipe),
 529                                        usb_pipeout(pipe), toggle);
 530                         dev->status = 0;
 531                         break;
 532                 case QT_TOKEN_STATUS_HALTED:
 533                         dev->status = USB_ST_STALLED;
 534                         break;
 535                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
 536                 case QT_TOKEN_STATUS_DATBUFERR:
 537                         dev->status = USB_ST_BUF_ERR;
 538                         break;
 539                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
 540                 case QT_TOKEN_STATUS_BABBLEDET:
 541                         dev->status = USB_ST_BABBLE_DET;
 542                         break;
 543                 default:
 544                         dev->status = USB_ST_CRC_ERR;
 545                         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
 546                                 dev->status |= USB_ST_STALLED;
 547                         break;
 548                 }
 549                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
 550         } else {
 551                 dev->act_len = 0;
 552                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
 553                       dev->devnum, ehci_readl(&hcor->or_usbsts),
 554                       ehci_readl(&hcor->or_portsc[0]),
 555                       ehci_readl(&hcor->or_portsc[1]));
 556         }
 557
 558         free(qtd);
 559         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
 560
 561 fail:
 562         free(qtd);
 563         return -1;
 564 }
 565
 566 static inline int min3(int a, int b, int c)
 567 {
 568
 569         if (b < a)
 570                 a = b;
 571         if (c < a)
 572                 a = c;
 573         return a;
 574 }
 575
 576 int
 577 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 578                  int length, struct devrequest *req)
 579 {
 580         uint8_t tmpbuf[4];
 581         u16 typeReq;
 582         void *srcptr = NULL;
 583         int len, srclen;
 584         uint32_t reg;
 585         uint32_t *status_reg;
 586
 587         if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
 588                 printf("The request port(%d) is not configured\n",
 589                         le16_to_cpu(req->index) - 1);
 590                 return -1;
 591         }
 592         status_reg = (uint32_t *)&hcor->or_portsc[
 593                                                 le16_to_cpu(req->index) - 1];
 594         srclen = 0;
 595
 596         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
 597               req->request, req->request,
 598               req->requesttype, req->requesttype,
 599               le16_to_cpu(req->value), le16_to_cpu(req->index));
 600
 601         typeReq = req->request | req->requesttype << 8;
 602
 603         switch (typeReq) {
 604         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 605                 switch (le16_to_cpu(req->value) >> 8) {
 606                 case USB_DT_DEVICE:
 607                         debug("USB_DT_DEVICE request\n");
 608                         srcptr = &descriptor.device;
 609                         srclen = descriptor.device.bLength;
 610                         break;
 611                 case USB_DT_CONFIG:
 612                         debug("USB_DT_CONFIG config\n");
 613                         srcptr = &descriptor.config;
 614                         srclen = descriptor.config.bLength +
 615                                         descriptor.interface.bLength +
 616                                         descriptor.endpoint.bLength;
 617                         break;
 618                 case USB_DT_STRING:
 619                         debug("USB_DT_STRING config\n");
 620                         switch (le16_to_cpu(req->value) & 0xff) {
 621                         case 0: /* Language */
 622                                 srcptr = "\4\3\1\0";
 623                                 srclen = 4;
 624                                 break;
 625                         case 1: /* Vendor */
 626                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
 627                                 srclen = 14;
 628                                 break;
 629                         case 2: /* Product */
 630                                 srcptr = "\52\3E\0H\0C\0I\0 "
 631                                          "\0H\0o\0s\0t\0 "
 632                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
 633                                 srclen = 42;
 634                                 break;
 635                         default:
 636                                 debug("unknown value DT_STRING %x\n",
 637                                         le16_to_cpu(req->value));
 638                                 goto unknown;
 639                         }
 640                         break;
 641                 default:
 642                         debug("unknown value %x\n", le16_to_cpu(req->value));
 643                         goto unknown;
 644                 }
 645                 break;
 646         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
 647                 switch (le16_to_cpu(req->value) >> 8) {
 648                 case USB_DT_HUB:
 649                         debug("USB_DT_HUB config\n");
 650                         srcptr = &descriptor.hub;
 651                         srclen = descriptor.hub.bLength;
 652                         break;
 653                 default:
 654                         debug("unknown value %x\n", le16_to_cpu(req->value));
 655                         goto unknown;
 656                 }
 657                 break;
 658         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
 659                 debug("USB_REQ_SET_ADDRESS\n");
 660                 rootdev = le16_to_cpu(req->value);
 661                 break;
 662         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
 663                 debug("USB_REQ_SET_CONFIGURATION\n");
 664                 /* Nothing to do */
 665                 break;
 666         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
 667                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
 668                 tmpbuf[1] = 0;
 669                 srcptr = tmpbuf;
 670                 srclen = 2;
 671                 break;
 672         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 673                 memset(tmpbuf, 0, 4);
 674                 reg = ehci_readl(status_reg);
 675                 if (reg & EHCI_PS_CS)
 676                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
 677                 if (reg & EHCI_PS_PE)
 678                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
 679                 if (reg & EHCI_PS_SUSP)
 680                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
 681                 if (reg & EHCI_PS_OCA)
 682                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
 683                 if (reg & EHCI_PS_PR)
 684                         tmpbuf[0] |= USB_PORT_STAT_RESET;
 685                 if (reg & EHCI_PS_PP)
 686                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
 687
 688                 if (ehci_is_TDI()) {
 689                         switch (PORTSC_PSPD(reg)) {
 690                         case PORTSC_PSPD_FS:
 691                                 break;
 692                         case PORTSC_PSPD_LS:
 693                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
 694                                 break;
 695                         case PORTSC_PSPD_HS:
 696                         default:
 697                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 698                                 break;
 699                         }
 700                 } else {
 701                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 702                 }
 703
 704                 if (reg & EHCI_PS_CSC)
 705                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
 706                 if (reg & EHCI_PS_PEC)
 707                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
 708                 if (reg & EHCI_PS_OCC)
 709                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
 710                 if (portreset & (1 << le16_to_cpu(req->index)))
 711                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
 712
 713                 srcptr = tmpbuf;
 714                 srclen = 4;
 715                 break;
 716         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 717                 reg = ehci_readl(status_reg);
 718                 reg &= ~EHCI_PS_CLEAR;
 719                 switch (le16_to_cpu(req->value)) {
 720                 case USB_PORT_FEAT_ENABLE:
 721                         reg |= EHCI_PS_PE;
 722                         ehci_writel(status_reg, reg);
 723                         break;
 724                 case USB_PORT_FEAT_POWER:
 725                         if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
 726                                 reg |= EHCI_PS_PP;
 727                                 ehci_writel(status_reg, reg);
 728                         }
 729                         break;
 730                 case USB_PORT_FEAT_RESET:
 731                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
 732                             !ehci_is_TDI() &&
 733                             EHCI_PS_IS_LOWSPEED(reg)) {
 734                                 /* Low speed device, give up ownership. */
 735                                 debug("port %d low speed --> companion\n",
 736                                       req->index - 1);
 737                                 reg |= EHCI_PS_PO;
 738                                 ehci_writel(status_reg, reg);
 739                                 break;
 740                         } else {
 741                                 int ret;
 742
 743                                 reg |= EHCI_PS_PR;
 744                                 reg &= ~EHCI_PS_PE;
 745                                 ehci_writel(status_reg, reg);
 746                                 /*
 747                                  * caller must wait, then call GetPortStatus
 748                                  * usb 2.0 specification say 50 ms resets on
 749                                  * root
 750                                  */
 751                                 ehci_powerup_fixup(status_reg, &reg);
 752
 753                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 754                                 /*
 755                                  * A host controller must terminate the reset
 756                                  * and stabilize the state of the port within
 757                                  * 2 milliseconds
 758                                  */
 759                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
 760                                                 2 * 1000);
 761                                 if (!ret)
 762                                         portreset |=
 763                                                 1 << le16_to_cpu(req->index);
 764                                 else
 765                                         printf("port(%d) reset error\n",
 766                                         le16_to_cpu(req->index) - 1);
 767                         }
 768                         break;
 769                 default:
 770                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 771                         goto unknown;
 772                 }
 773                 /* unblock posted writes */
 774                 (void) ehci_readl(&hcor->or_usbcmd);
 775                 break;
 776         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 777                 reg = ehci_readl(status_reg);
 778                 switch (le16_to_cpu(req->value)) {
 779                 case USB_PORT_FEAT_ENABLE:
 780                         reg &= ~EHCI_PS_PE;
 781                         break;
 782                 case USB_PORT_FEAT_C_ENABLE:
 783                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
 784                         break;
 785                 case USB_PORT_FEAT_POWER:
 786                         if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
 787                                 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
 788                 case USB_PORT_FEAT_C_CONNECTION:
 789                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
 790                         break;
 791                 case USB_PORT_FEAT_OVER_CURRENT:
 792                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
 793                         break;
 794                 case USB_PORT_FEAT_C_RESET:
 795                         portreset &= ~(1 << le16_to_cpu(req->index));
 796                         break;
 797                 default:
 798                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 799                         goto unknown;
 800                 }
 801                 ehci_writel(status_reg, reg);
 802                 /* unblock posted write */
 803                 (void) ehci_readl(&hcor->or_usbcmd);
 804                 break;
 805         default:
 806                 debug("Unknown request\n");
 807                 goto unknown;
 808         }
 809
 810         mdelay(1);
 811         len = min3(srclen, le16_to_cpu(req->length), length);
 812         if (srcptr != NULL && len > 0)
 813                 memcpy(buffer, srcptr, len);
 814         else
 815                 debug("Len is 0\n");
 816
 817         dev->act_len = len;
 818         dev->status = 0;
 819         return 0;
 820
 821 unknown:
 822         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
 823               req->requesttype, req->request, le16_to_cpu(req->value),
 824               le16_to_cpu(req->index), le16_to_cpu(req->length));
 825
 826         dev->act_len = 0;
 827         dev->status = USB_ST_STALLED;
 828         return -1;
 829 }
 830
 831 int usb_lowlevel_stop(void)
 832 {
 833         return ehci_hcd_stop();
 834 }
 835
 836 int usb_lowlevel_init(void)
 837 {
 838         uint32_t reg;
 839         uint32_t cmd;
 840
 841         if (ehci_hcd_init())
 842                 return -1;
 843
 844         /* EHCI spec section 4.1 */
 845         if (ehci_reset())
 846                 return -1;
 847
 848 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
 849         if (ehci_hcd_init())
 850                 return -1;
 851 #endif
 852
 853         /* Set head of reclaim list */
 854         memset(qh_list, 0, sizeof(*qh_list));
 855         qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
 856         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
 857                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
 858         qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
 859         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 860         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 861         qh_list->qh_overlay.qt_token =
 862                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
 863
 864         reg = ehci_readl(&hccr->cr_hcsparams);
 865         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
 866         printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
 867         /* Port Indicators */
 868         if (HCS_INDICATOR(reg))
 869                 descriptor.hub.wHubCharacteristics |= 0x80;
 870         /* Port Power Control */
 871         if (HCS_PPC(reg))
 872                 descriptor.hub.wHubCharacteristics |= 0x01;
 873
 874         /* Start the host controller. */
 875         cmd = ehci_readl(&hcor->or_usbcmd);
 876         /*
 877          * Philips, Intel, and maybe others need CMD_RUN before the
 878          * root hub will detect new devices (why?); NEC doesn't
 879          */
 880         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 881         cmd |= CMD_RUN;
 882         ehci_writel(&hcor->or_usbcmd, cmd);
 883
 884         /* take control over the ports */
 885         cmd = ehci_readl(&hcor->or_configflag);
 886         cmd |= FLAG_CF;
 887         ehci_writel(&hcor->or_configflag, cmd);
 888         /* unblock posted write */
 889         cmd = ehci_readl(&hcor->or_usbcmd);
 890         mdelay(5);
 891         reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
 892         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
 893
 894         rootdev = 0;
 895
 896         return 0;
 897 }
 898
 899 int
 900 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 901                 int length)
 902 {
 903
 904         if (usb_pipetype(pipe) != PIPE_BULK) {
 905                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
 906                 return -1;
 907         }
 908         return ehci_submit_async(dev, pipe, buffer, length, NULL);
 909 }
 910
 911 int
 912 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 913                    int length, struct devrequest *setup)
 914 {
 915
 916         if (usb_pipetype(pipe) != PIPE_CONTROL) {
 917                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
 918                 return -1;
 919         }
 920
 921         if (usb_pipedevice(pipe) == rootdev) {
 922                 if (!rootdev)
 923                         dev->speed = USB_SPEED_HIGH;
 924                 return ehci_submit_root(dev, pipe, buffer, length, setup);
 925         }
 926         return ehci_submit_async(dev, pipe, buffer, length, setup);
 927 }
 928
 929 int
 930 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 931                int length, int interval)
 932 {
 933         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
 934               dev, pipe, buffer, length, interval);
 935
 936         /*
 937          * Interrupt transfers requiring several transactions are not supported
 938          * because bInterval is ignored.
 939          *
 940          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
 941          * <= PKT_ALIGN if several qTDs are required, while the USB
 942          * specification does not constrain this for interrupt transfers. That
 943          * means that ehci_submit_async() would support interrupt transfers
 944          * requiring several transactions only as long as the transfer size does
 945          * not require more than a single qTD.
 946          */
 947         if (length > usb_maxpacket(dev, pipe)) {
 948                 printf("%s: Interrupt transfers requiring several transactions "
 949                         "are not supported.\n", __func__);
 950                 return -1;
 951         }
 952         return ehci_submit_async(dev, pipe, buffer, length, NULL);
 953 }