usb: create common header virtual root hub descriptors
[karo-tx-uboot.git] / drivers / usb / musb / musb_hcd.c
1 /*
2  * Mentor USB OTG Core host controller driver.
3  *
4  * Copyright (c) 2008 Texas Instruments
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  *
8  * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
9  */
10
11 #include <common.h>
12 #include <usb.h>
13 #include "musb_hcd.h"
14
15 /* MSC control transfers */
16 #define USB_MSC_BBB_RESET       0xFF
17 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
18
19 /* Endpoint configuration information */
20 static const struct musb_epinfo epinfo[3] = {
21         {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
22         {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In  - 512 Bytes */
23         {MUSB_INTR_EP, 0, 64}   /* EP2 - Interrupt IN - 64 Bytes */
24 };
25
26 /* --- Virtual Root Hub ---------------------------------------------------- */
27 #ifdef MUSB_NO_MULTIPOINT
28 static int rh_devnum;
29 static u32 port_status;
30
31 #include <usbroothubdes.h>
32
33 #endif
34
35 /*
36  * This function writes the data toggle value.
37  */
38 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
39 {
40         u16 toggle = usb_gettoggle(dev, ep, dir_out);
41         u16 csr;
42
43         if (dir_out) {
44                 csr = readw(&musbr->txcsr);
45                 if (!toggle) {
46                         if (csr & MUSB_TXCSR_MODE)
47                                 csr = MUSB_TXCSR_CLRDATATOG;
48                         else
49                                 csr = 0;
50                         writew(csr, &musbr->txcsr);
51                 } else {
52                         csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
53                         writew(csr, &musbr->txcsr);
54                         csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
55                         writew(csr, &musbr->txcsr);
56                 }
57         } else {
58                 if (!toggle) {
59                         csr = readw(&musbr->txcsr);
60                         if (csr & MUSB_TXCSR_MODE)
61                                 csr = MUSB_RXCSR_CLRDATATOG;
62                         else
63                                 csr = 0;
64                         writew(csr, &musbr->rxcsr);
65                 } else {
66                         csr = readw(&musbr->rxcsr);
67                         csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
68                         writew(csr, &musbr->rxcsr);
69                         csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
70                         writew(csr, &musbr->rxcsr);
71                 }
72         }
73 }
74
75 /*
76  * This function checks if RxStall has occured on the endpoint. If a RxStall
77  * has occured, the RxStall is cleared and 1 is returned. If RxStall has
78  * not occured, 0 is returned.
79  */
80 static u8 check_stall(u8 ep, u8 dir_out)
81 {
82         u16 csr;
83
84         /* For endpoint 0 */
85         if (!ep) {
86                 csr = readw(&musbr->txcsr);
87                 if (csr & MUSB_CSR0_H_RXSTALL) {
88                         csr &= ~MUSB_CSR0_H_RXSTALL;
89                         writew(csr, &musbr->txcsr);
90                         return 1;
91                 }
92         } else { /* For non-ep0 */
93                 if (dir_out) { /* is it tx ep */
94                         csr = readw(&musbr->txcsr);
95                         if (csr & MUSB_TXCSR_H_RXSTALL) {
96                                 csr &= ~MUSB_TXCSR_H_RXSTALL;
97                                 writew(csr, &musbr->txcsr);
98                                 return 1;
99                         }
100                 } else { /* is it rx ep */
101                         csr = readw(&musbr->rxcsr);
102                         if (csr & MUSB_RXCSR_H_RXSTALL) {
103                                 csr &= ~MUSB_RXCSR_H_RXSTALL;
104                                 writew(csr, &musbr->rxcsr);
105                                 return 1;
106                         }
107                 }
108         }
109         return 0;
110 }
111
112 /*
113  * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
114  * error and -2 for stall.
115  */
116 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
117 {
118         u16 csr;
119         int result = 1;
120         int timeout = CONFIG_MUSB_TIMEOUT;
121
122         while (result > 0) {
123                 csr = readw(&musbr->txcsr);
124                 if (csr & MUSB_CSR0_H_ERROR) {
125                         csr &= ~MUSB_CSR0_H_ERROR;
126                         writew(csr, &musbr->txcsr);
127                         dev->status = USB_ST_CRC_ERR;
128                         result = -1;
129                         break;
130                 }
131
132                 switch (bit_mask) {
133                 case MUSB_CSR0_TXPKTRDY:
134                         if (!(csr & MUSB_CSR0_TXPKTRDY)) {
135                                 if (check_stall(MUSB_CONTROL_EP, 0)) {
136                                         dev->status = USB_ST_STALLED;
137                                         result = -2;
138                                 } else
139                                         result = 0;
140                         }
141                         break;
142
143                 case MUSB_CSR0_RXPKTRDY:
144                         if (check_stall(MUSB_CONTROL_EP, 0)) {
145                                 dev->status = USB_ST_STALLED;
146                                 result = -2;
147                         } else
148                                 if (csr & MUSB_CSR0_RXPKTRDY)
149                                         result = 0;
150                         break;
151
152                 case MUSB_CSR0_H_REQPKT:
153                         if (!(csr & MUSB_CSR0_H_REQPKT)) {
154                                 if (check_stall(MUSB_CONTROL_EP, 0)) {
155                                         dev->status = USB_ST_STALLED;
156                                         result = -2;
157                                 } else
158                                         result = 0;
159                         }
160                         break;
161                 }
162
163                 /* Check the timeout */
164                 if (--timeout)
165                         udelay(1);
166                 else {
167                         dev->status = USB_ST_CRC_ERR;
168                         result = -1;
169                         break;
170                 }
171         }
172
173         return result;
174 }
175
176 /*
177  * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
178  */
179 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
180 {
181         u16 csr;
182         int timeout = CONFIG_MUSB_TIMEOUT;
183
184         do {
185                 if (check_stall(ep, 1)) {
186                         dev->status = USB_ST_STALLED;
187                         return 0;
188                 }
189
190                 csr = readw(&musbr->txcsr);
191                 if (csr & MUSB_TXCSR_H_ERROR) {
192                         dev->status = USB_ST_CRC_ERR;
193                         return 0;
194                 }
195
196                 /* Check the timeout */
197                 if (--timeout)
198                         udelay(1);
199                 else {
200                         dev->status = USB_ST_CRC_ERR;
201                         return -1;
202                 }
203
204         } while (csr & MUSB_TXCSR_TXPKTRDY);
205         return 1;
206 }
207
208 /*
209  * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
210  */
211 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
212 {
213         u16 csr;
214         int timeout = CONFIG_MUSB_TIMEOUT;
215
216         do {
217                 if (check_stall(ep, 0)) {
218                         dev->status = USB_ST_STALLED;
219                         return 0;
220                 }
221
222                 csr = readw(&musbr->rxcsr);
223                 if (csr & MUSB_RXCSR_H_ERROR) {
224                         dev->status = USB_ST_CRC_ERR;
225                         return 0;
226                 }
227
228                 /* Check the timeout */
229                 if (--timeout)
230                         udelay(1);
231                 else {
232                         dev->status = USB_ST_CRC_ERR;
233                         return -1;
234                 }
235
236         } while (!(csr & MUSB_RXCSR_RXPKTRDY));
237         return 1;
238 }
239
240 /*
241  * This function performs the setup phase of the control transfer
242  */
243 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
244 {
245         int result;
246         u16 csr;
247
248         /* write the control request to ep0 fifo */
249         write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
250
251         /* enable transfer of setup packet */
252         csr = readw(&musbr->txcsr);
253         csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
254         writew(csr, &musbr->txcsr);
255
256         /* wait until the setup packet is transmitted */
257         result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
258         dev->act_len = 0;
259         return result;
260 }
261
262 /*
263  * This function handles the control transfer in data phase
264  */
265 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
266 {
267         u16 csr;
268         u32 rxlen = 0;
269         u32 nextlen = 0;
270         u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
271         u8  *rxbuff = (u8 *)buffer;
272         u8  rxedlength;
273         int result;
274
275         while (rxlen < len) {
276                 /* Determine the next read length */
277                 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
278
279                 /* Set the ReqPkt bit */
280                 csr = readw(&musbr->txcsr);
281                 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
282                 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
283                 if (result < 0)
284                         return result;
285
286                 /* Actual number of bytes received by usb */
287                 rxedlength = readb(&musbr->rxcount);
288
289                 /* Read the data from the RxFIFO */
290                 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
291
292                 /* Clear the RxPktRdy Bit */
293                 csr = readw(&musbr->txcsr);
294                 csr &= ~MUSB_CSR0_RXPKTRDY;
295                 writew(csr, &musbr->txcsr);
296
297                 /* short packet? */
298                 if (rxedlength != nextlen) {
299                         dev->act_len += rxedlength;
300                         break;
301                 }
302                 rxlen += nextlen;
303                 dev->act_len = rxlen;
304         }
305         return 0;
306 }
307
308 /*
309  * This function handles the control transfer out data phase
310  */
311 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
312 {
313         u16 csr;
314         u32 txlen = 0;
315         u32 nextlen = 0;
316         u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
317         u8  *txbuff = (u8 *)buffer;
318         int result = 0;
319
320         while (txlen < len) {
321                 /* Determine the next write length */
322                 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
323
324                 /* Load the data to send in FIFO */
325                 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
326
327                 /* Set TXPKTRDY bit */
328                 csr = readw(&musbr->txcsr);
329                         
330                 csr |= MUSB_CSR0_TXPKTRDY;
331 #if !defined(CONFIG_SOC_DM365)
332                 csr |= MUSB_CSR0_H_DIS_PING;
333 #endif
334                 writew(csr, &musbr->txcsr);
335                 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
336                 if (result < 0)
337                         break;
338
339                 txlen += nextlen;
340                 dev->act_len = txlen;
341         }
342         return result;
343 }
344
345 /*
346  * This function handles the control transfer out status phase
347  */
348 static int ctrlreq_out_status_phase(struct usb_device *dev)
349 {
350         u16 csr;
351         int result;
352
353         /* Set the StatusPkt bit */
354         csr = readw(&musbr->txcsr);
355         csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
356 #if !defined(CONFIG_SOC_DM365)
357         csr |= MUSB_CSR0_H_DIS_PING;
358 #endif
359         writew(csr, &musbr->txcsr);
360
361         /* Wait until TXPKTRDY bit is cleared */
362         result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
363         return result;
364 }
365
366 /*
367  * This function handles the control transfer in status phase
368  */
369 static int ctrlreq_in_status_phase(struct usb_device *dev)
370 {
371         u16 csr;
372         int result;
373
374         /* Set the StatusPkt bit and ReqPkt bit */
375         csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
376 #if !defined(CONFIG_SOC_DM365)
377         csr |= MUSB_CSR0_H_DIS_PING;
378 #endif
379         writew(csr, &musbr->txcsr);
380         result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
381
382         /* clear StatusPkt bit and RxPktRdy bit */
383         csr = readw(&musbr->txcsr);
384         csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
385         writew(csr, &musbr->txcsr);
386         return result;
387 }
388
389 /*
390  * determines the speed of the device (High/Full/Slow)
391  */
392 static u8 get_dev_speed(struct usb_device *dev)
393 {
394         return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
395                 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
396                                                 MUSB_TYPE_SPEED_FULL);
397 }
398
399 /*
400  * configure the hub address and the port address.
401  */
402 static void config_hub_port(struct usb_device *dev, u8 ep)
403 {
404         u8 chid;
405         u8 hub;
406
407         /* Find out the nearest parent which is high speed */
408         while (dev->parent->parent != NULL)
409                 if (get_dev_speed(dev->parent) !=  MUSB_TYPE_SPEED_HIGH)
410                         dev = dev->parent;
411                 else
412                         break;
413
414         /* determine the port address at that hub */
415         hub = dev->parent->devnum;
416         for (chid = 0; chid < USB_MAXCHILDREN; chid++)
417                 if (dev->parent->children[chid] == dev)
418                         break;
419
420 #ifndef MUSB_NO_MULTIPOINT
421         /* configure the hub address and the port address */
422         writeb(hub, &musbr->tar[ep].txhubaddr);
423         writeb((chid + 1), &musbr->tar[ep].txhubport);
424         writeb(hub, &musbr->tar[ep].rxhubaddr);
425         writeb((chid + 1), &musbr->tar[ep].rxhubport);
426 #endif
427 }
428
429 #ifdef MUSB_NO_MULTIPOINT
430
431 static void musb_port_reset(int do_reset)
432 {
433         u8 power = readb(&musbr->power);
434
435         if (do_reset) {
436                 power &= 0xf0;
437                 writeb(power | MUSB_POWER_RESET, &musbr->power);
438                 port_status |= USB_PORT_STAT_RESET;
439                 port_status &= ~USB_PORT_STAT_ENABLE;
440                 udelay(30000);
441         } else {
442                 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
443
444                 power = readb(&musbr->power);
445                 if (power & MUSB_POWER_HSMODE)
446                         port_status |= USB_PORT_STAT_HIGH_SPEED;
447
448                 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
449                 port_status |= USB_PORT_STAT_ENABLE
450                         | (USB_PORT_STAT_C_RESET << 16)
451                         | (USB_PORT_STAT_C_ENABLE << 16);
452         }
453 }
454
455 /*
456  * root hub control
457  */
458 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
459                               void *buffer, int transfer_len,
460                               struct devrequest *cmd)
461 {
462         int leni = transfer_len;
463         int len = 0;
464         int stat = 0;
465         u32 datab[4];
466         const u8 *data_buf = (u8 *) datab;
467         u16 bmRType_bReq;
468         u16 wValue;
469         u16 wIndex;
470         u16 wLength;
471         u16 int_usb;
472
473         if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
474                 debug("Root-Hub submit IRQ: NOT implemented\n");
475                 return 0;
476         }
477
478         bmRType_bReq = cmd->requesttype | (cmd->request << 8);
479         wValue = swap_16(cmd->value);
480         wIndex = swap_16(cmd->index);
481         wLength = swap_16(cmd->length);
482
483         debug("--- HUB ----------------------------------------\n");
484         debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
485             bmRType_bReq, wValue, wIndex, wLength);
486         debug("------------------------------------------------\n");
487
488         switch (bmRType_bReq) {
489         case RH_GET_STATUS:
490                 debug("RH_GET_STATUS\n");
491
492                 *(__u16 *) data_buf = swap_16(1);
493                 len = 2;
494                 break;
495
496         case RH_GET_STATUS | RH_INTERFACE:
497                 debug("RH_GET_STATUS | RH_INTERFACE\n");
498
499                 *(__u16 *) data_buf = swap_16(0);
500                 len = 2;
501                 break;
502
503         case RH_GET_STATUS | RH_ENDPOINT:
504                 debug("RH_GET_STATUS | RH_ENDPOINT\n");
505
506                 *(__u16 *) data_buf = swap_16(0);
507                 len = 2;
508                 break;
509
510         case RH_GET_STATUS | RH_CLASS:
511                 debug("RH_GET_STATUS | RH_CLASS\n");
512
513                 *(__u32 *) data_buf = swap_32(0);
514                 len = 4;
515                 break;
516
517         case RH_GET_STATUS | RH_OTHER | RH_CLASS:
518                 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
519
520                 int_usb = readw(&musbr->intrusb);
521                 if (int_usb & MUSB_INTR_CONNECT) {
522                         port_status |= USB_PORT_STAT_CONNECTION
523                                 | (USB_PORT_STAT_C_CONNECTION << 16);
524                         port_status |= USB_PORT_STAT_HIGH_SPEED
525                                 | USB_PORT_STAT_ENABLE;
526                 }
527
528                 if (port_status & USB_PORT_STAT_RESET)
529                         musb_port_reset(0);
530
531                 *(__u32 *) data_buf = swap_32(port_status);
532                 len = 4;
533                 break;
534
535         case RH_CLEAR_FEATURE | RH_ENDPOINT:
536                 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
537
538                 switch (wValue) {
539                 case RH_ENDPOINT_STALL:
540                         debug("C_HUB_ENDPOINT_STALL\n");
541                         len = 0;
542                         break;
543                 }
544                 port_status &= ~(1 << wValue);
545                 break;
546
547         case RH_CLEAR_FEATURE | RH_CLASS:
548                 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
549
550                 switch (wValue) {
551                 case RH_C_HUB_LOCAL_POWER:
552                         debug("C_HUB_LOCAL_POWER\n");
553                         len = 0;
554                         break;
555
556                 case RH_C_HUB_OVER_CURRENT:
557                         debug("C_HUB_OVER_CURRENT\n");
558                         len = 0;
559                         break;
560                 }
561                 port_status &= ~(1 << wValue);
562                 break;
563
564         case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
565                 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
566
567                 switch (wValue) {
568                 case RH_PORT_ENABLE:
569                         len = 0;
570                         break;
571
572                 case RH_PORT_SUSPEND:
573                         len = 0;
574                         break;
575
576                 case RH_PORT_POWER:
577                         len = 0;
578                         break;
579
580                 case RH_C_PORT_CONNECTION:
581                         len = 0;
582                         break;
583
584                 case RH_C_PORT_ENABLE:
585                         len = 0;
586                         break;
587
588                 case RH_C_PORT_SUSPEND:
589                         len = 0;
590                         break;
591
592                 case RH_C_PORT_OVER_CURRENT:
593                         len = 0;
594                         break;
595
596                 case RH_C_PORT_RESET:
597                         len = 0;
598                         break;
599
600                 default:
601                         debug("invalid wValue\n");
602                         stat = USB_ST_STALLED;
603                 }
604
605                 port_status &= ~(1 << wValue);
606                 break;
607
608         case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
609                 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
610
611                 switch (wValue) {
612                 case RH_PORT_SUSPEND:
613                         len = 0;
614                         break;
615
616                 case RH_PORT_RESET:
617                         musb_port_reset(1);
618                         len = 0;
619                         break;
620
621                 case RH_PORT_POWER:
622                         len = 0;
623                         break;
624
625                 case RH_PORT_ENABLE:
626                         len = 0;
627                         break;
628
629                 default:
630                         debug("invalid wValue\n");
631                         stat = USB_ST_STALLED;
632                 }
633
634                 port_status |= 1 << wValue;
635                 break;
636
637         case RH_SET_ADDRESS:
638                 debug("RH_SET_ADDRESS\n");
639
640                 rh_devnum = wValue;
641                 len = 0;
642                 break;
643
644         case RH_GET_DESCRIPTOR:
645                 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
646
647                 switch (wValue) {
648                 case (USB_DT_DEVICE << 8):      /* device descriptor */
649                         len = min_t(unsigned int,
650                                     leni, min_t(unsigned int,
651                                                 sizeof(root_hub_dev_des),
652                                                 wLength));
653                         data_buf = root_hub_dev_des;
654                         break;
655
656                 case (USB_DT_CONFIG << 8):      /* configuration descriptor */
657                         len = min_t(unsigned int,
658                                     leni, min_t(unsigned int,
659                                                 sizeof(root_hub_config_des),
660                                                 wLength));
661                         data_buf = root_hub_config_des;
662                         break;
663
664                 case ((USB_DT_STRING << 8) | 0x00):     /* string 0 descriptors */
665                         len = min_t(unsigned int,
666                                     leni, min_t(unsigned int,
667                                                 sizeof(root_hub_str_index0),
668                                                 wLength));
669                         data_buf = root_hub_str_index0;
670                         break;
671
672                 case ((USB_DT_STRING << 8) | 0x01):     /* string 1 descriptors */
673                         len = min_t(unsigned int,
674                                     leni, min_t(unsigned int,
675                                                 sizeof(root_hub_str_index1),
676                                                 wLength));
677                         data_buf = root_hub_str_index1;
678                         break;
679
680                 default:
681                         debug("invalid wValue\n");
682                         stat = USB_ST_STALLED;
683                 }
684
685                 break;
686
687         case RH_GET_DESCRIPTOR | RH_CLASS: {
688                 u8 *_data_buf = (u8 *) datab;
689                 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
690
691                 _data_buf[0] = 0x09;    /* min length; */
692                 _data_buf[1] = 0x29;
693                 _data_buf[2] = 0x1;     /* 1 port */
694                 _data_buf[3] = 0x01;    /* per-port power switching */
695                 _data_buf[3] |= 0x10;   /* no overcurrent reporting */
696
697                 /* Corresponds to data_buf[4-7] */
698                 _data_buf[4] = 0;
699                 _data_buf[5] = 5;
700                 _data_buf[6] = 0;
701                 _data_buf[7] = 0x02;
702                 _data_buf[8] = 0xff;
703
704                 len = min_t(unsigned int, leni,
705                             min_t(unsigned int, data_buf[0], wLength));
706                 break;
707         }
708
709         case RH_GET_CONFIGURATION:
710                 debug("RH_GET_CONFIGURATION\n");
711
712                 *(__u8 *) data_buf = 0x01;
713                 len = 1;
714                 break;
715
716         case RH_SET_CONFIGURATION:
717                 debug("RH_SET_CONFIGURATION\n");
718
719                 len = 0;
720                 break;
721
722         default:
723                 debug("*** *** *** unsupported root hub command *** *** ***\n");
724                 stat = USB_ST_STALLED;
725         }
726
727         len = min_t(int, len, leni);
728         if (buffer != data_buf)
729                 memcpy(buffer, data_buf, len);
730
731         dev->act_len = len;
732         dev->status = stat;
733         debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
734
735         return stat;
736 }
737
738 static void musb_rh_init(void)
739 {
740         rh_devnum = 0;
741         port_status = 0;
742 }
743
744 #else
745
746 static void musb_rh_init(void) {}
747
748 #endif
749
750 /*
751  * do a control transfer
752  */
753 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
754                         int len, struct devrequest *setup)
755 {
756         int devnum = usb_pipedevice(pipe);
757         u8  devspeed;
758
759 #ifdef MUSB_NO_MULTIPOINT
760         /* Control message is for the HUB? */
761         if (devnum == rh_devnum) {
762                 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
763                 if (stat)
764                         return stat;
765         }
766 #endif
767
768         /* select control endpoint */
769         writeb(MUSB_CONTROL_EP, &musbr->index);
770         readw(&musbr->txcsr);
771
772 #ifndef MUSB_NO_MULTIPOINT
773         /* target addr and (for multipoint) hub addr/port */
774         writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
775         writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
776 #endif
777
778         /* configure the hub address and the port number as required */
779         devspeed = get_dev_speed(dev);
780         if ((musb_ishighspeed()) && (dev->parent != NULL) &&
781                 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
782                 config_hub_port(dev, MUSB_CONTROL_EP);
783                 writeb(devspeed << 6, &musbr->txtype);
784         } else {
785                 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
786 #ifndef MUSB_NO_MULTIPOINT
787                 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
788                 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
789                 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
790                 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
791 #endif
792         }
793
794         /* Control transfer setup phase */
795         if (ctrlreq_setup_phase(dev, setup) < 0)
796                 return 0;
797
798         switch (setup->request) {
799         case USB_REQ_GET_DESCRIPTOR:
800         case USB_REQ_GET_CONFIGURATION:
801         case USB_REQ_GET_INTERFACE:
802         case USB_REQ_GET_STATUS:
803         case USB_MSC_BBB_GET_MAX_LUN:
804                 /* control transfer in-data-phase */
805                 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
806                         return 0;
807                 /* control transfer out-status-phase */
808                 if (ctrlreq_out_status_phase(dev) < 0)
809                         return 0;
810                 break;
811
812         case USB_REQ_SET_ADDRESS:
813         case USB_REQ_SET_CONFIGURATION:
814         case USB_REQ_SET_FEATURE:
815         case USB_REQ_SET_INTERFACE:
816         case USB_REQ_CLEAR_FEATURE:
817         case USB_MSC_BBB_RESET:
818                 /* control transfer in status phase */
819                 if (ctrlreq_in_status_phase(dev) < 0)
820                         return 0;
821                 break;
822
823         case USB_REQ_SET_DESCRIPTOR:
824                 /* control transfer out data phase */
825                 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
826                         return 0;
827                 /* control transfer in status phase */
828                 if (ctrlreq_in_status_phase(dev) < 0)
829                         return 0;
830                 break;
831
832         default:
833                 /* unhandled control transfer */
834                 return -1;
835         }
836
837         dev->status = 0;
838         dev->act_len = len;
839
840 #ifdef MUSB_NO_MULTIPOINT
841         /* Set device address to USB_FADDR register */
842         if (setup->request == USB_REQ_SET_ADDRESS)
843                 writeb(dev->devnum, &musbr->faddr);
844 #endif
845
846         return len;
847 }
848
849 /*
850  * do a bulk transfer
851  */
852 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
853                                         void *buffer, int len)
854 {
855         int dir_out = usb_pipeout(pipe);
856         int ep = usb_pipeendpoint(pipe);
857 #ifndef MUSB_NO_MULTIPOINT
858         int devnum = usb_pipedevice(pipe);
859 #endif
860         u8  type;
861         u16 csr;
862         u32 txlen = 0;
863         u32 nextlen = 0;
864         u8  devspeed;
865
866         /* select bulk endpoint */
867         writeb(MUSB_BULK_EP, &musbr->index);
868
869 #ifndef MUSB_NO_MULTIPOINT
870         /* write the address of the device */
871         if (dir_out)
872                 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
873         else
874                 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
875 #endif
876
877         /* configure the hub address and the port number as required */
878         devspeed = get_dev_speed(dev);
879         if ((musb_ishighspeed()) && (dev->parent != NULL) &&
880                 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
881                 /*
882                  * MUSB is in high speed and the destination device is full
883                  * speed device. So configure the hub address and port
884                  * address registers.
885                  */
886                 config_hub_port(dev, MUSB_BULK_EP);
887         } else {
888 #ifndef MUSB_NO_MULTIPOINT
889                 if (dir_out) {
890                         writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
891                         writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
892                 } else {
893                         writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
894                         writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
895                 }
896 #endif
897                 devspeed = musb_cfg.musb_speed;
898         }
899
900         /* Write the saved toggle bit value */
901         write_toggle(dev, ep, dir_out);
902
903         if (dir_out) { /* bulk-out transfer */
904                 /* Program the TxType register */
905                 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
906                            (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
907                            (ep & MUSB_TYPE_REMOTE_END);
908                 writeb(type, &musbr->txtype);
909
910                 /* Write maximum packet size to the TxMaxp register */
911                 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
912                 while (txlen < len) {
913                         nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
914                                         (len-txlen) : dev->epmaxpacketout[ep];
915
916 #ifdef CONFIG_USB_BLACKFIN
917                         /* Set the transfer data size */
918                         writew(nextlen, &musbr->txcount);
919 #endif
920
921                         /* Write the data to the FIFO */
922                         write_fifo(MUSB_BULK_EP, nextlen,
923                                         (void *)(((u8 *)buffer) + txlen));
924
925                         /* Set the TxPktRdy bit */
926                         csr = readw(&musbr->txcsr);
927                         writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
928
929                         /* Wait until the TxPktRdy bit is cleared */
930                         if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
931                                 readw(&musbr->txcsr);
932                                 usb_settoggle(dev, ep, dir_out,
933                                 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
934                                 dev->act_len = txlen;
935                                 return 0;
936                         }
937                         txlen += nextlen;
938                 }
939
940                 /* Keep a copy of the data toggle bit */
941                 csr = readw(&musbr->txcsr);
942                 usb_settoggle(dev, ep, dir_out,
943                                 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
944         } else { /* bulk-in transfer */
945                 /* Write the saved toggle bit value */
946                 write_toggle(dev, ep, dir_out);
947
948                 /* Program the RxType register */
949                 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
950                            (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
951                            (ep & MUSB_TYPE_REMOTE_END);
952                 writeb(type, &musbr->rxtype);
953
954                 /* Write the maximum packet size to the RxMaxp register */
955                 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
956                 while (txlen < len) {
957                         nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
958                                         (len-txlen) : dev->epmaxpacketin[ep];
959
960                         /* Set the ReqPkt bit */
961                         csr = readw(&musbr->rxcsr);
962                         writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
963
964                         /* Wait until the RxPktRdy bit is set */
965                         if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
966                                 csr = readw(&musbr->rxcsr);
967                                 usb_settoggle(dev, ep, dir_out,
968                                 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
969                                 csr &= ~MUSB_RXCSR_RXPKTRDY;
970                                 writew(csr, &musbr->rxcsr);
971                                 dev->act_len = txlen;
972                                 return 0;
973                         }
974
975                         /* Read the data from the FIFO */
976                         read_fifo(MUSB_BULK_EP, nextlen,
977                                         (void *)(((u8 *)buffer) + txlen));
978
979                         /* Clear the RxPktRdy bit */
980                         csr =  readw(&musbr->rxcsr);
981                         csr &= ~MUSB_RXCSR_RXPKTRDY;
982                         writew(csr, &musbr->rxcsr);
983                         txlen += nextlen;
984                 }
985
986                 /* Keep a copy of the data toggle bit */
987                 csr = readw(&musbr->rxcsr);
988                 usb_settoggle(dev, ep, dir_out,
989                                 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
990         }
991
992         /* bulk transfer is complete */
993         dev->status = 0;
994         dev->act_len = len;
995         return 0;
996 }
997
998 /*
999  * This function initializes the usb controller module.
1000  */
1001 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1002 {
1003         u8  power;
1004         u32 timeout;
1005
1006         musb_rh_init();
1007
1008         if (musb_platform_init() == -1)
1009                 return -1;
1010
1011         /* Configure all the endpoint FIFO's and start usb controller */
1012         musbr = musb_cfg.regs;
1013         musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1014         musb_start();
1015
1016         /*
1017          * Wait until musb is enabled in host mode with a timeout. There
1018          * should be a usb device connected.
1019          */
1020         timeout = musb_cfg.timeout;
1021         while (--timeout)
1022                 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1023                         break;
1024
1025         /* if musb core is not in host mode, then return */
1026         if (!timeout)
1027                 return -1;
1028
1029         /* start usb bus reset */
1030         power = readb(&musbr->power);
1031         writeb(power | MUSB_POWER_RESET, &musbr->power);
1032
1033         /* After initiating a usb reset, wait for about 20ms to 30ms */
1034         udelay(30000);
1035
1036         /* stop usb bus reset */
1037         power = readb(&musbr->power);
1038         power &= ~MUSB_POWER_RESET;
1039         writeb(power, &musbr->power);
1040
1041         /* Determine if the connected device is a high/full/low speed device */
1042         musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1043                         MUSB_TYPE_SPEED_HIGH :
1044                         ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1045                         MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1046         return 0;
1047 }
1048
1049 /*
1050  * This function stops the operation of the davinci usb module.
1051  */
1052 int usb_lowlevel_stop(int index)
1053 {
1054         /* Reset the USB module */
1055         musb_platform_deinit();
1056         writeb(0, &musbr->devctl);
1057         return 0;
1058 }
1059
1060 /*
1061  * This function supports usb interrupt transfers. Currently, usb interrupt
1062  * transfers are not supported.
1063  */
1064 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1065                                 void *buffer, int len, int interval)
1066 {
1067         int dir_out = usb_pipeout(pipe);
1068         int ep = usb_pipeendpoint(pipe);
1069 #ifndef MUSB_NO_MULTIPOINT
1070         int devnum = usb_pipedevice(pipe);
1071 #endif
1072         u8  type;
1073         u16 csr;
1074         u32 txlen = 0;
1075         u32 nextlen = 0;
1076         u8  devspeed;
1077
1078         /* select interrupt endpoint */
1079         writeb(MUSB_INTR_EP, &musbr->index);
1080
1081 #ifndef MUSB_NO_MULTIPOINT
1082         /* write the address of the device */
1083         if (dir_out)
1084                 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1085         else
1086                 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1087 #endif
1088
1089         /* configure the hub address and the port number as required */
1090         devspeed = get_dev_speed(dev);
1091         if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1092                 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1093                 /*
1094                  * MUSB is in high speed and the destination device is full
1095                  * speed device. So configure the hub address and port
1096                  * address registers.
1097                  */
1098                 config_hub_port(dev, MUSB_INTR_EP);
1099         } else {
1100 #ifndef MUSB_NO_MULTIPOINT
1101                 if (dir_out) {
1102                         writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1103                         writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1104                 } else {
1105                         writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1106                         writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1107                 }
1108 #endif
1109                 devspeed = musb_cfg.musb_speed;
1110         }
1111
1112         /* Write the saved toggle bit value */
1113         write_toggle(dev, ep, dir_out);
1114
1115         if (!dir_out) { /* intrrupt-in transfer */
1116                 /* Write the saved toggle bit value */
1117                 write_toggle(dev, ep, dir_out);
1118                 writeb(interval, &musbr->rxinterval);
1119
1120                 /* Program the RxType register */
1121                 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1122                            (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1123                            (ep & MUSB_TYPE_REMOTE_END);
1124                 writeb(type, &musbr->rxtype);
1125
1126                 /* Write the maximum packet size to the RxMaxp register */
1127                 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1128
1129                 while (txlen < len) {
1130                         nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1131                                         (len-txlen) : dev->epmaxpacketin[ep];
1132
1133                         /* Set the ReqPkt bit */
1134                         csr = readw(&musbr->rxcsr);
1135                         writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1136
1137                         /* Wait until the RxPktRdy bit is set */
1138                         if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1139                                 csr = readw(&musbr->rxcsr);
1140                                 usb_settoggle(dev, ep, dir_out,
1141                                 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1142                                 csr &= ~MUSB_RXCSR_RXPKTRDY;
1143                                 writew(csr, &musbr->rxcsr);
1144                                 dev->act_len = txlen;
1145                                 return 0;
1146                         }
1147
1148                         /* Read the data from the FIFO */
1149                         read_fifo(MUSB_INTR_EP, nextlen,
1150                                         (void *)(((u8 *)buffer) + txlen));
1151
1152                         /* Clear the RxPktRdy bit */
1153                         csr =  readw(&musbr->rxcsr);
1154                         csr &= ~MUSB_RXCSR_RXPKTRDY;
1155                         writew(csr, &musbr->rxcsr);
1156                         txlen += nextlen;
1157                 }
1158
1159                 /* Keep a copy of the data toggle bit */
1160                 csr = readw(&musbr->rxcsr);
1161                 usb_settoggle(dev, ep, dir_out,
1162                                 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1163         }
1164
1165         /* interrupt transfer is complete */
1166         dev->irq_status = 0;
1167         dev->irq_act_len = len;
1168         dev->irq_handle(dev);
1169         dev->status = 0;
1170         dev->act_len = len;
1171         return 0;
1172 }