drivers/video/atmel_hlcdfb.c

   1 /*
   2  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   3  *
   4  * Copyright (C) 2012 Atmel Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/gpio.h>
  12 #include <asm/arch/clk.h>
  13 #include <lcd.h>
  14 #include <atmel_hlcdc.h>
  15
  16 #if defined(CONFIG_LCD_LOGO)
  17 #include <bmp_logo.h>
  18 #endif
  19
  20 /* configurable parameters */
  21 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  22 #define ATMEL_LCDC_DMA_BURST_LEN        8
  23 #ifndef ATMEL_LCDC_GUARD_TIME
  24 #define ATMEL_LCDC_GUARD_TIME           1
  25 #endif
  26
  27 #define ATMEL_LCDC_FIFO_SIZE            512
  28
  29 #define lcdc_readl(reg)         __raw_readl((reg))
  30 #define lcdc_writel(reg, val)   __raw_writel((val), (reg))
  31
  32 /*
  33  * the CLUT register map as following
  34  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  35  */
  36 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  37 {
  38         lcdc_writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  39                 ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) |
  40                 ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) |
  41                 ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  42 }
  43
  44 ushort *configuration_get_cmap(void)
  45 {
  46 #if defined(CONFIG_LCD_LOGO)
  47         return bmp_logo_palette;
  48 #else
  49         return NULL;
  50 #endif
  51 }
  52
  53 void lcd_ctrl_init(void *lcdbase)
  54 {
  55         unsigned long value;
  56         struct lcd_dma_desc *desc;
  57         struct atmel_hlcd_regs *regs;
  58         u32 clk_pol;
  59
  60         if (!has_lcdc())
  61                 return;     /* No lcdc */
  62
  63         regs = panel_info.mmio;
  64         clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0;
  65
  66         /* Disable DISP signal */
  67         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
  68         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
  69                 udelay(1);
  70         /* Disable synchronization */
  71         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
  72         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
  73                 udelay(1);
  74         /* Disable pixel clock */
  75         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
  76         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
  77                 udelay(1);
  78         /* Disable PWM */
  79         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
  80         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
  81                 udelay(1);
  82
  83         /* Set pixel clock */
  84         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  85         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  86                 value++;
  87
  88         if (value < 1) {
  89                 /* Using system clock as pixel clock */
  90                 lcdc_writel(&regs->lcdc_lcdcfg0,
  91                                         LCDC_LCDCFG0_CLKDIV(0)
  92                                         | LCDC_LCDCFG0_CGDISHCR
  93                                         | LCDC_LCDCFG0_CGDISHEO
  94                                         | LCDC_LCDCFG0_CGDISOVR1
  95                                         | LCDC_LCDCFG0_CGDISBASE
  96                                         | LCDC_LCDCFG0_CLKSEL
  97                                         | clk_pol);
  98
  99         } else {
 100                 lcdc_writel(&regs->lcdc_lcdcfg0,
 101                                 LCDC_LCDCFG0_CLKDIV(value - 2)
 102                                 | LCDC_LCDCFG0_CGDISHCR
 103                                 | LCDC_LCDCFG0_CGDISHEO
 104                                 | LCDC_LCDCFG0_CGDISOVR1
 105                                 | LCDC_LCDCFG0_CGDISBASE
 106                                 | clk_pol);
 107         }
 108
 109         /* Initialize control register 5 */
 110         value = 0;
 111
 112         value |= panel_info.vl_sync;
 113
 114 #ifndef LCD_OUTPUT_BPP
 115         /* Output is 24bpp */
 116         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 117 #else
 118         switch (LCD_OUTPUT_BPP) {
 119         case 12:
 120                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 121                 break;
 122         case 16:
 123                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 124                 break;
 125         case 18:
 126                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 127                 break;
 128         case 24:
 129                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 130                 break;
 131         default:
 132                 BUG();
 133                 break;
 134         }
 135 #endif
 136
 137         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 138         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 139         lcdc_writel(&regs->lcdc_lcdcfg5, value);
 140
 141         /* Vertical & Horizontal Timing */
 142         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 143         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 144         lcdc_writel(&regs->lcdc_lcdcfg1, value);
 145
 146         value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
 147         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 148         lcdc_writel(&regs->lcdc_lcdcfg2, value);
 149
 150         value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
 151         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 152         lcdc_writel(&regs->lcdc_lcdcfg3, value);
 153
 154         /* Display size */
 155         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 156         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 157         lcdc_writel(&regs->lcdc_lcdcfg4, value);
 158
 159         lcdc_writel(&regs->lcdc_basecfg0,
 160                         LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
 161
 162         switch (NBITS(panel_info.vl_bpix)) {
 163         case 16:
 164                 lcdc_writel(&regs->lcdc_basecfg1,
 165                         LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
 166                 break;
 167         default:
 168                 BUG();
 169                 break;
 170         }
 171
 172         lcdc_writel(&regs->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
 173         lcdc_writel(&regs->lcdc_basecfg3, 0);
 174         lcdc_writel(&regs->lcdc_basecfg4, LCDC_BASECFG4_DMA);
 175
 176         /* Disable all interrupts */
 177         lcdc_writel(&regs->lcdc_lcdidr, ~0UL);
 178         lcdc_writel(&regs->lcdc_baseidr, ~0UL);
 179
 180         /* Setup the DMA descriptor, this descriptor will loop to itself */
 181         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 182
 183         desc->address = (u32)lcdbase;
 184         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 185         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 186                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 187         desc->next = (u32)desc;
 188
 189         /* Flush the DMA descriptor if we enabled dcache */
 190         flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
 191
 192         lcdc_writel(&regs->lcdc_baseaddr, desc->address);
 193         lcdc_writel(&regs->lcdc_basectrl, desc->control);
 194         lcdc_writel(&regs->lcdc_basenext, desc->next);
 195         lcdc_writel(&regs->lcdc_basecher, LCDC_BASECHER_CHEN |
 196                                           LCDC_BASECHER_UPDATEEN);
 197
 198         /* Enable LCD */
 199         value = lcdc_readl(&regs->lcdc_lcden);
 200         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
 201         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
 202                 udelay(1);
 203         value = lcdc_readl(&regs->lcdc_lcden);
 204         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
 205         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
 206                 udelay(1);
 207         value = lcdc_readl(&regs->lcdc_lcden);
 208         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
 209         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
 210                 udelay(1);
 211         value = lcdc_readl(&regs->lcdc_lcden);
 212         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
 213         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
 214                 udelay(1);
 215
 216         /* Enable flushing if we enabled dcache */
 217         lcd_set_flush_dcache(1);
 218 }