drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /* #define DEBUG */
  15 #include <common.h>
  16 #include <div64.h>
  17 #include <ipu.h>
  18 #include <linux/types.h>
  19 #include <linux/err.h>
  20 #include <asm/io.h>
  21 #include <asm/errno.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/crm_regs.h>
  24 #include <asm/arch/clock.h>
  25
  26 #include "ipu_regs.h"
  27
  28 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
  29
  30 struct ipu_ch_param_word {
  31         uint32_t data[5];
  32         uint32_t res[3];
  33 };
  34
  35 struct ipu_ch_param {
  36         struct ipu_ch_param_word word[2];
  37 };
  38
  39 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  40
  41 #define _param_word(base, w) \
  42         (((struct ipu_ch_param *)(base))->word[w].data)
  43
  44 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
  45         int i = (bit) / 32;                                             \
  46         int off = (bit) % 32;                                           \
  47         _param_word(base, w)[i] |= (v) << off;                          \
  48         if (((bit) + (size) - 1) / 32 > i) {                            \
  49                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  50         }                                                               \
  51 }
  52
  53 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
  54         int i = (bit) / 32;                                     \
  55         int off = (bit) % 32;                                   \
  56         u32 mask = (1UL << size) - 1;                           \
  57         u32 temp = _param_word(base, w)[i];                     \
  58         temp &= ~(mask << off);                                 \
  59         _param_word(base, w)[i] = temp | (v) << off;            \
  60         if (((bit) + (size) - 1) / 32 > i) {                    \
  61                 temp = _param_word(base, w)[i + 1];             \
  62                 temp &= ~(mask >> (32 - off));                  \
  63                 _param_word(base, w)[i + 1] =                   \
  64                         temp | ((v) >> (off ? (32 - off) : 0)); \
  65         }                                                       \
  66 }
  67
  68 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
  69         u32 temp2;                                              \
  70         int i = (bit) / 32;                                     \
  71         int off = (bit) % 32;                                   \
  72         u32 mask = (1UL << size) - 1;                           \
  73         u32 temp1 = _param_word(base, w)[i];                    \
  74         temp1 = mask & (temp1 >> off);                          \
  75         if (((bit)+(size) - 1) / 32 > i) {                      \
  76                 temp2 = _param_word(base, w)[i + 1];            \
  77                 temp2 &= mask >> (off ? (32 - off) : 0);        \
  78                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
  79         }                                                       \
  80         temp1;                                                  \
  81 })
  82
  83 #define IPU_SW_RST_TOUT_USEC    10000
  84
  85 static int clk_ipu_enable(struct clk *clk)
  86 {
  87         ipu_clk_enable();
  88         return 0;
  89 }
  90
  91 static void clk_ipu_disable(struct clk *clk)
  92 {
  93         ipu_clk_disable();
  94 }
  95
  96 static struct clk ipu_clk = {
  97         .name = "ipu_clk",
  98         .rate = CONFIG_IPUV3_CLK,
  99         .enable = clk_ipu_enable,
 100         .disable = clk_ipu_disable,
 101 };
 102
 103 static int clk_ldb_enable(struct clk *clk)
 104 {
 105         ldb_clk_enable(0);
 106         ldb_clk_enable(1);
 107         return 0;
 108 }
 109
 110 static void clk_ldb_disable(struct clk *clk)
 111 {
 112         ldb_clk_disable(0);
 113         ldb_clk_disable(1);
 114 }
 115
 116 #if !defined CONFIG_SYS_LDB_CLOCK
 117 #define CONFIG_SYS_LDB_CLOCK 65000000
 118 #endif
 119
 120 static struct clk ldb_clk = {
 121         .name = "ldb_clk",
 122         .rate = CONFIG_SYS_LDB_CLOCK,
 123         .enable = clk_ldb_enable,
 124         .disable = clk_ldb_disable,
 125 };
 126
 127 /* Globals */
 128 struct clk *g_ipu_clk = &ipu_clk;
 129 struct clk *g_ldb_clk = &ldb_clk;
 130 struct clk *g_di_clk[2];
 131 struct clk *g_pixel_clk[2];
 132 unsigned char g_dc_di_assignment[10];
 133 int g_ipu_clk_enabled;
 134 u32 *ipu_dc_tmpl_reg;
 135
 136 static uint32_t g_channel_init_mask;
 137 static uint32_t g_channel_enable_mask;
 138 static int ipu_dc_use_count;
 139 static int ipu_dp_use_count;
 140 static int ipu_dmfc_use_count;
 141 static int ipu_di_use_count[2];
 142
 143 static u32 *ipu_cpmem_base;
 144
 145 /* Static functions */
 146
 147 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 148 {
 149         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 150 };
 151
 152 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 153 {
 154         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 155 };
 156
 157 /* Either DP BG or DP FG can be graphic window */
 158 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 159 {
 160         return (dma_chan == 23 || dma_chan == 27);
 161 }
 162
 163 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 164 {
 165         return ((dma_chan >= 23) && (dma_chan <= 29));
 166 }
 167
 168
 169 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 170                                             dma_addr_t phyaddr)
 171 {
 172         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 173                                phyaddr / 8);
 174 };
 175
 176 #define idma_is_valid(ch)       (ch != NO_DMA)
 177 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 178 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 179
 180 static void ipu_pixel_clk_recalc(struct clk *clk)
 181 {
 182         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 183         u64 parent_rate = (u64)clk->parent->rate * 16;
 184
 185         if (div == 0)
 186                 clk->rate = 0;
 187         else
 188                 clk->rate = lldiv(parent_rate, div);
 189 }
 190
 191 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 192         unsigned long rate)
 193 {
 194         u32 div, div1;
 195         u64 tmp;
 196
 197         /*
 198          * Calculate divider
 199          * Fractional part is 4 bits,
 200          * so simply multiply by 2^4 to get fractional part.
 201          */
 202         tmp = (u64)clk->parent->rate * 16;
 203         div = lldiv(tmp, rate);
 204
 205         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 206                 div = 0x10;
 207         if (div & ~0xFEF) {
 208                 div &= 0xFF8;
 209         } else {
 210                 div1 = div & 0xFE0;
 211
 212                 if ((lldiv(tmp, div1) - lldiv(tmp, div)) < rate / 4)
 213                         div = div1;
 214                 else
 215                         div &= 0xFF8;
 216         }
 217         do_div(tmp, div);
 218 #if 1
 219         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
 220                 rate / 1000000, rate / 1000 % 1000,
 221                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 222                 lldiv(tmp, 1000000), lldiv(tmp, 1000) % 1000, div / 16, div % 16);
 223 #endif
 224         return tmp;
 225 }
 226
 227 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 228 {
 229         u64 parent_rate = (u64)clk->parent->rate * 16;
 230         u32 div = lldiv(parent_rate, rate);
 231
 232         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
 233                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 234                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
 235
 236         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 237
 238         /* Setup pixel clock timing */
 239         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 240         clk->rate = lldiv(parent_rate, div);
 241         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
 242                 clk->rate / 1000000, clk->rate / 1000 % 1000);
 243         return 0;
 244 }
 245
 246 static int ipu_pixel_clk_enable(struct clk *clk)
 247 {
 248         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 249         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 250         __raw_writel(disp_gen, IPU_DISP_GEN);
 251
 252         return 0;
 253 }
 254
 255 static void ipu_pixel_clk_disable(struct clk *clk)
 256 {
 257         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 258         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 259         __raw_writel(disp_gen, IPU_DISP_GEN);
 260 }
 261
 262 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 263 {
 264         int ret;
 265         u32 di_gen;
 266
 267         ret = clk_enable(clk);
 268         if (ret)
 269                 return ret;
 270
 271         di_gen = __raw_readl(DI_GENERAL(clk->id));
 272
 273         if (parent == g_ipu_clk)
 274                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 275         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
 276                 di_gen |= DI_GEN_DI_CLK_EXT;
 277         else
 278                 goto err;
 279
 280         ret = clk_enable(parent);
 281         if (ret)
 282                 goto err;
 283         __raw_writel(di_gen, DI_GENERAL(clk->id));
 284         ipu_pixel_clk_recalc(clk);
 285         clk->disable(clk->parent);
 286         clk->parent = parent;
 287 err:
 288         clk_disable(clk);
 289         return ret;
 290 }
 291
 292 static struct clk pixel_clk[] = {
 293         {
 294                 .name = "pixel_clk",
 295                 .id = 0,
 296                 .recalc = ipu_pixel_clk_recalc,
 297                 .set_rate = ipu_pixel_clk_set_rate,
 298                 .round_rate = ipu_pixel_clk_round_rate,
 299                 .set_parent = ipu_pixel_clk_set_parent,
 300                 .enable = ipu_pixel_clk_enable,
 301                 .disable = ipu_pixel_clk_disable,
 302         },
 303         {
 304                 .name = "pixel_clk",
 305                 .id = 1,
 306                 .recalc = ipu_pixel_clk_recalc,
 307                 .set_rate = ipu_pixel_clk_set_rate,
 308                 .round_rate = ipu_pixel_clk_round_rate,
 309                 .set_parent = ipu_pixel_clk_set_parent,
 310                 .enable = ipu_pixel_clk_enable,
 311                 .disable = ipu_pixel_clk_disable,
 312         },
 313 };
 314
 315 static int clk_ipu_di_enable(struct clk *clk)
 316 {
 317         ipu_di_clk_enable(clk->id);
 318         return 0;
 319 }
 320
 321 static void clk_ipu_di_disable(struct clk *clk)
 322 {
 323         ipu_di_clk_disable(clk->id);
 324 }
 325
 326 static struct clk di_clk[] = {
 327         {
 328                 .name = "ipu_di_clk",
 329                 .id = 0,
 330                 .enable = clk_ipu_di_enable,
 331                 .disable = clk_ipu_di_disable,
 332         },
 333         {
 334                 .name = "ipu_di_clk",
 335                 .id = 1,
 336                 .enable = clk_ipu_di_enable,
 337                 .disable = clk_ipu_di_disable,
 338         },
 339 };
 340
 341 /*
 342  * This function resets IPU
 343  */
 344 static void ipu_reset(void)
 345 {
 346         u32 *reg;
 347         u32 value;
 348         int timeout = IPU_SW_RST_TOUT_USEC;
 349
 350         reg = (u32 *)SRC_BASE_ADDR;
 351         value = __raw_readl(reg);
 352         value = value | SW_IPU_RST;
 353         __raw_writel(value, reg);
 354
 355         while (__raw_readl(reg) & SW_IPU_RST) {
 356                 udelay(1);
 357                 if (!(timeout--)) {
 358                         printf("ipu software reset timeout\n");
 359                         break;
 360                 }
 361         };
 362 }
 363
 364 /*
 365  * This function is called by the driver framework to initialize the IPU
 366  * hardware.
 367  *
 368  * @param       dev     The device structure for the IPU passed in by the
 369  *                      driver framework.
 370  *
 371  * @return      Returns 0 on success or negative error code on error
 372  */
 373 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
 374 {
 375         int ret;
 376         void *ipu_base;
 377         unsigned long start;
 378 #if defined CONFIG_SOC_MX51
 379         u32 temp;
 380         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 381         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 382
 383          __raw_writel(0xF00, reg_hsc_mcd);
 384
 385         /* CSI mode reserved */
 386         temp = __raw_readl(reg_hsc_mxt_conf);
 387          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 388
 389         temp = __raw_readl(reg_hsc_mxt_conf);
 390         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 391 #endif
 392         ipu_base = (void *)IPU_SOC_BASE_ADDR;
 393         /* base fixup */
 394         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
 395                 ipu_base += IPUV3H_REG_BASE;
 396         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
 397                 ipu_base += IPUV3M_REG_BASE;
 398         else                    /* IPUv3D, v3E, v3EX */
 399                 ipu_base += IPUV3DEX_REG_BASE;
 400         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
 401         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
 402
 403         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
 404
 405         g_pixel_clk[0] = &pixel_clk[0];
 406         g_pixel_clk[1] = &pixel_clk[1];
 407
 408         g_di_clk[0] = &di_clk[0];
 409         g_di_clk[1] = &di_clk[1];
 410         g_di_clk[di]->rate = di_clk_val;
 411
 412         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 413         debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
 414
 415         ret = clk_enable(g_ipu_clk);
 416         if (ret)
 417                 return ret;
 418         ipu_reset();
 419
 420         if (di_clk_parent == DI_PCLK_LDB) {
 421                 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
 422         } else {
 423                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 424                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 425         }
 426
 427         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 428         start = get_timer_masked();
 429         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
 430                 if (get_timer(start) > CONFIG_SYS_HZ)
 431                         return -ETIME;
 432         }
 433
 434         ipu_init_dc_mappings();
 435
 436         __raw_writel(0, IPU_INT_CTRL(5));
 437         __raw_writel(0, IPU_INT_CTRL(6));
 438         __raw_writel(0, IPU_INT_CTRL(9));
 439         __raw_writel(0, IPU_INT_CTRL(10));
 440
 441         /* DMFC Init */
 442         ipu_dmfc_init(DMFC_NORMAL, 1);
 443
 444         /* Set sync refresh channels as high priority */
 445         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 446
 447         /* Set MCU_T to divide MCU access window into 2 */
 448         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 449
 450         clk_disable(g_ipu_clk);
 451
 452         return 0;
 453 }
 454
 455 void ipu_dump_registers(void)
 456 {
 457         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
 458         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
 459         debug("IDMAC_CHA_EN1        0x%08X\n",
 460                __raw_readl(IDMAC_CHA_EN(0)));
 461         debug("IDMAC_CHA_EN2        0x%08X\n",
 462                __raw_readl(IDMAC_CHA_EN(32)));
 463         debug("IDMAC_CHA_PRI1       0x%08X\n",
 464                __raw_readl(IDMAC_CHA_PRI(0)));
 465         debug("IDMAC_CHA_PRI2       0x%08X\n",
 466                __raw_readl(IDMAC_CHA_PRI(32)));
 467         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
 468                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 469         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
 470                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 471         debug("DMFC_WR_CHAN         0x%08X\n",
 472                __raw_readl(DMFC_WR_CHAN));
 473         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
 474                __raw_readl(DMFC_WR_CHAN_DEF));
 475         debug("DMFC_DP_CHAN         0x%08X\n",
 476                __raw_readl(DMFC_DP_CHAN));
 477         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
 478                __raw_readl(DMFC_DP_CHAN_DEF));
 479         debug("DMFC_IC_CTRL         0x%08X\n",
 480                __raw_readl(DMFC_IC_CTRL));
 481         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
 482                __raw_readl(IPU_FS_PROC_FLOW1));
 483         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
 484                __raw_readl(IPU_FS_PROC_FLOW2));
 485         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
 486                __raw_readl(IPU_FS_PROC_FLOW3));
 487         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
 488                __raw_readl(IPU_FS_DISP_FLOW1));
 489 }
 490
 491 /*
 492  * This function is called to initialize a logical IPU channel.
 493  *
 494  * @param       channel Input parameter for the logical channel ID to init.
 495  *
 496  * @param       params  Input parameter containing union of channel
 497  *                      initialization parameters.
 498  *
 499  * @return      Returns 0 on success or negative error code on fail
 500  */
 501 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 502 {
 503         int ret = 0;
 504         uint32_t ipu_conf;
 505
 506         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 507
 508         if (g_ipu_clk_enabled == 0) {
 509                 g_ipu_clk_enabled = 1;
 510                 clk_enable(g_ipu_clk);
 511         }
 512
 513
 514         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 515                 printf("Warning: channel already initialized %d\n",
 516                         IPU_CHAN_ID(channel));
 517         }
 518
 519         ipu_conf = __raw_readl(IPU_CONF);
 520
 521         switch (channel) {
 522         case MEM_DC_SYNC:
 523                 if (params->mem_dc_sync.di > 1) {
 524                         ret = -EINVAL;
 525                         goto err;
 526                 }
 527
 528                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 529                 ipu_dc_init(1, params->mem_dc_sync.di,
 530                              params->mem_dc_sync.interlaced);
 531                 ipu_di_use_count[params->mem_dc_sync.di]++;
 532                 ipu_dc_use_count++;
 533                 ipu_dmfc_use_count++;
 534                 break;
 535         case MEM_BG_SYNC:
 536                 if (params->mem_dp_bg_sync.di > 1) {
 537                         ret = -EINVAL;
 538                         goto err;
 539                 }
 540
 541                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 542                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 543                              params->mem_dp_bg_sync.out_pixel_fmt);
 544                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 545                              params->mem_dp_bg_sync.interlaced);
 546                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 547                 ipu_dc_use_count++;
 548                 ipu_dp_use_count++;
 549                 ipu_dmfc_use_count++;
 550                 break;
 551         case MEM_FG_SYNC:
 552                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 553                              params->mem_dp_fg_sync.out_pixel_fmt);
 554
 555                 ipu_dc_use_count++;
 556                 ipu_dp_use_count++;
 557                 ipu_dmfc_use_count++;
 558                 break;
 559         default:
 560                 printf("Missing channel initialization\n");
 561         }
 562
 563         /* Enable IPU sub module */
 564         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 565         if (ipu_dc_use_count == 1)
 566                 ipu_conf |= IPU_CONF_DC_EN;
 567         if (ipu_dp_use_count == 1)
 568                 ipu_conf |= IPU_CONF_DP_EN;
 569         if (ipu_dmfc_use_count == 1)
 570                 ipu_conf |= IPU_CONF_DMFC_EN;
 571         if (ipu_di_use_count[0] == 1) {
 572                 ipu_conf |= IPU_CONF_DI0_EN;
 573                 clk_enable(g_di_clk[0]);
 574         }
 575         if (ipu_di_use_count[1] == 1) {
 576                 ipu_conf |= IPU_CONF_DI1_EN;
 577                 clk_enable(g_di_clk[1]);
 578         }
 579
 580         __raw_writel(ipu_conf, IPU_CONF);
 581
 582 err:
 583         return ret;
 584 }
 585
 586 /*
 587  * This function is called to uninitialize a logical IPU channel.
 588  *
 589  * @param       channel Input parameter for the logical channel ID to uninit.
 590  */
 591 void ipu_uninit_channel(ipu_channel_t channel)
 592 {
 593         uint32_t reg;
 594         uint32_t in_dma, out_dma = 0;
 595         uint32_t ipu_conf;
 596
 597         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 598                 debug("Channel already uninitialized %d\n",
 599                         IPU_CHAN_ID(channel));
 600                 return;
 601         }
 602
 603         /*
 604          * Make sure channel is disabled
 605          * Get input and output dma channels
 606          */
 607         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 608         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 609
 610         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 611             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 612                 printf("Channel %d is not disabled, disable first\n",
 613                         IPU_CHAN_ID(channel));
 614                 return;
 615         }
 616
 617         ipu_conf = __raw_readl(IPU_CONF);
 618
 619         /* Reset the double buffer */
 620         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 621         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 622         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 623         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 624
 625         switch (channel) {
 626         case MEM_DC_SYNC:
 627                 ipu_dc_uninit(1);
 628                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 629                 ipu_dc_use_count--;
 630                 ipu_dmfc_use_count--;
 631                 break;
 632         case MEM_BG_SYNC:
 633                 ipu_dp_uninit(channel);
 634                 ipu_dc_uninit(5);
 635                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 636                 ipu_dc_use_count--;
 637                 ipu_dp_use_count--;
 638                 ipu_dmfc_use_count--;
 639                 break;
 640         case MEM_FG_SYNC:
 641                 ipu_dp_uninit(channel);
 642                 ipu_dc_use_count--;
 643                 ipu_dp_use_count--;
 644                 ipu_dmfc_use_count--;
 645                 break;
 646         default:
 647                 break;
 648         }
 649
 650         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 651
 652         if (ipu_dc_use_count == 0)
 653                 ipu_conf &= ~IPU_CONF_DC_EN;
 654         if (ipu_dp_use_count == 0)
 655                 ipu_conf &= ~IPU_CONF_DP_EN;
 656         if (ipu_dmfc_use_count == 0)
 657                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 658         if (ipu_di_use_count[0] == 0 && ipu_conf & IPU_CONF_DI0_EN) {
 659                 ipu_conf &= ~IPU_CONF_DI0_EN;
 660                 clk_disable(g_di_clk[0]);
 661         }
 662         if (ipu_di_use_count[1] == 0 && ipu_conf & IPU_CONF_DI1_EN) {
 663                 ipu_conf &= ~IPU_CONF_DI1_EN;
 664                 clk_disable(g_di_clk[1]);
 665         }
 666
 667         __raw_writel(ipu_conf, IPU_CONF);
 668
 669         /* clear interrupt status */
 670         __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
 671
 672         if (ipu_conf == 0) {
 673                 clk_disable(g_ipu_clk);
 674                 g_ipu_clk_enabled = 0;
 675         }
 676 }
 677
 678 static inline void ipu_ch_param_dump(int ch)
 679 {
 680 #ifdef DEBUG
 681         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 682         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 683                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 684                  p->word[0].data[3], p->word[0].data[4]);
 685         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 686                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 687                  p->word[1].data[3], p->word[1].data[4]);
 688         debug("PFS 0x%x, ",
 689                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 690         debug("BPP 0x%x, ",
 691                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 692         debug("NPB 0x%x\n",
 693                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 694
 695         debug("FW %d, ",
 696                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 697         debug("FH %d, ",
 698                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 699         debug("Stride %d\n",
 700                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 701
 702         debug("Width0 %d+1, ",
 703                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 704         debug("Width1 %d+1, ",
 705                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 706         debug("Width2 %d+1, ",
 707                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 708         debug("Width3 %d+1, ",
 709                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 710         debug("Offset0 %d, ",
 711                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 712         debug("Offset1 %d, ",
 713                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 714         debug("Offset2 %d, ",
 715                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 716         debug("Offset3 %d\n",
 717                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 718 #endif
 719 }
 720
 721 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 722                                               int red_width, int red_offset,
 723                                               int green_width, int green_offset,
 724                                               int blue_width, int blue_offset,
 725                                               int alpha_width, int alpha_offset)
 726 {
 727         /* Setup red width and offset */
 728         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 729         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 730         /* Setup green width and offset */
 731         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 732         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 733         /* Setup blue width and offset */
 734         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 735         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 736         /* Setup alpha width and offset */
 737         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 738         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 739 }
 740
 741 static void ipu_ch_param_init(int ch,
 742                               uint32_t pixel_fmt, uint32_t width,
 743                               uint32_t height, uint32_t stride,
 744                               uint32_t u, uint32_t v,
 745                               uint32_t uv_stride, dma_addr_t addr0,
 746                               dma_addr_t addr1)
 747 {
 748         uint32_t u_offset = 0;
 749         uint32_t v_offset = 0;
 750
 751         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
 752
 753         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 754                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
 755                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
 756         } else {
 757                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
 758                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
 759         }
 760
 761         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
 762         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
 763
 764         switch (pixel_fmt) {
 765         case IPU_PIX_FMT_GENERIC:
 766                 /*Represents 8-bit Generic data */
 767                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
 768                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
 769                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
 770
 771                 break;
 772         case IPU_PIX_FMT_GENERIC_32:
 773                 /*Represents 32-bit Generic data */
 774                 break;
 775         case IPU_PIX_FMT_RGB565:
 776                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 777                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 778                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 779
 780                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
 781                 break;
 782         case IPU_PIX_FMT_BGR24:
 783                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 784                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 785                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 786
 787                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 788                 break;
 789         case IPU_PIX_FMT_RGB24:
 790         case IPU_PIX_FMT_YUV444:
 791                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 792                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 793                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 794
 795                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
 796                 break;
 797         case IPU_PIX_FMT_BGRA32:
 798         case IPU_PIX_FMT_BGR32:
 799                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 800                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 801                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 802
 803                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
 804                 break;
 805         case IPU_PIX_FMT_RGBA32:
 806         case IPU_PIX_FMT_RGB32:
 807                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 808                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 809                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 810
 811                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
 812                 break;
 813         case IPU_PIX_FMT_ABGR32:
 814                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 815                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 816
 817                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 818                 break;
 819         case IPU_PIX_FMT_UYVY:
 820                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 821                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
 822                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 823                 break;
 824         case IPU_PIX_FMT_YUYV:
 825                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 826                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
 827                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 828                 break;
 829         case IPU_PIX_FMT_YUV420P2:
 830         case IPU_PIX_FMT_YUV420P:
 831                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
 832
 833                 if (uv_stride < stride / 2)
 834                         uv_stride = stride / 2;
 835
 836                 u_offset = stride * height;
 837                 v_offset = u_offset + (uv_stride * height / 2);
 838                 /* burst size */
 839                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 840                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
 841                         uv_stride = uv_stride*2;
 842                 } else {
 843                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
 844                 }
 845                 break;
 846         case IPU_PIX_FMT_YVU422P:
 847                 /* BPP & pixel format */
 848                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 849                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 850
 851                 if (uv_stride < stride / 2)
 852                         uv_stride = stride / 2;
 853
 854                 v_offset = (v == 0) ? stride * height : v;
 855                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 856                 break;
 857         case IPU_PIX_FMT_YUV422P:
 858                 /* BPP & pixel format */
 859                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 860                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 861
 862                 if (uv_stride < stride / 2)
 863                         uv_stride = stride / 2;
 864
 865                 u_offset = (u == 0) ? stride * height : u;
 866                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 867                 break;
 868         case IPU_PIX_FMT_NV12:
 869                 /* BPP & pixel format */
 870                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
 871                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 872                 uv_stride = stride;
 873                 u_offset = (u == 0) ? stride * height : u;
 874                 break;
 875         default:
 876                 printf("mxc ipu: unimplemented pixel format: %08x\n",
 877                         pixel_fmt);
 878         }
 879
 880
 881         if (uv_stride)
 882                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
 883
 884         /* Get the uv offset from user when need cropping */
 885         if (u || v) {
 886                 u_offset = u;
 887                 v_offset = v;
 888         }
 889
 890         /* UBO and VBO are 22-bit */
 891         if (u_offset/8 > 0x3fffff)
 892                 puts("The value of U offset exceeds IPU limitation\n");
 893         if (v_offset/8 > 0x3fffff)
 894                 puts("The value of V offset exceeds IPU limitation\n");
 895
 896         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 897         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
 898
 899         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 900 };
 901
 902 /*
 903  * This function is called to initialize a buffer for logical IPU channel.
 904  *
 905  * @param       channel         Input parameter for the logical channel ID.
 906  *
 907  * @param       type            Input parameter which buffer to initialize.
 908  *
 909  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 910  *                              Pixel format is a FOURCC ASCII code.
 911  *
 912  * @param       width           Input parameter for width of buffer in pixels.
 913  *
 914  * @param       height          Input parameter for height of buffer in pixels.
 915  *
 916  * @param       stride          Input parameter for stride length of buffer
 917  *                              in pixels.
 918  *
 919  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 920  *
 921  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 922  *                              Setting this to a value other than NULL enables
 923  *                              double buffering mode.
 924  *
 925  * @param       u               private u offset for additional cropping,
 926  *                              zero if not used.
 927  *
 928  * @param       v               private v offset for additional cropping,
 929  *                              zero if not used.
 930  *
 931  * @return      Returns 0 on success or negative error code on fail
 932  */
 933 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 934                                 uint32_t pixel_fmt,
 935                                 uint16_t width, uint16_t height,
 936                                 uint32_t stride,
 937                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 938                                 uint32_t u, uint32_t v)
 939 {
 940         uint32_t reg;
 941         uint32_t dma_chan;
 942
 943         dma_chan = channel_2_dma(channel, type);
 944         if (!idma_is_valid(dma_chan))
 945                 return -EINVAL;
 946
 947         if (stride < width * bytes_per_pixel(pixel_fmt))
 948                 stride = width * bytes_per_pixel(pixel_fmt);
 949
 950         if (stride % 4) {
 951                 printf("Stride %d not 32-bit aligned\n", stride);
 952                 return -EINVAL;
 953         }
 954         /* Build parameter memory data for DMA channel */
 955         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 956                            phyaddr_0, phyaddr_1);
 957
 958         if (ipu_is_dmfc_chan(dma_chan)) {
 959                 ipu_dmfc_set_wait4eot(dma_chan, width);
 960         }
 961
 962         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 963                 ipu_ch_param_set_high_priority(dma_chan);
 964
 965         ipu_ch_param_dump(dma_chan);
 966
 967         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 968         if (phyaddr_1)
 969                 reg |= idma_mask(dma_chan);
 970         else
 971                 reg &= ~idma_mask(dma_chan);
 972         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 973
 974         /* Reset to buffer 0 */
 975         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 976
 977         return 0;
 978 }
 979
 980 /*
 981  * This function enables a logical channel.
 982  *
 983  * @param       channel         Input parameter for the logical channel ID.
 984  *
 985  * @return      This function returns 0 on success or negative error code on
 986  *              fail.
 987  */
 988 int32_t ipu_enable_channel(ipu_channel_t channel)
 989 {
 990         uint32_t reg;
 991         uint32_t in_dma;
 992         uint32_t out_dma;
 993
 994         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
 995                 printf("Warning: channel already enabled %d\n",
 996                         IPU_CHAN_ID(channel));
 997         }
 998
 999         /* Get input and output dma channels */
1000         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1001         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1002
1003         if (idma_is_valid(in_dma)) {
1004                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1005                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1006         }
1007         if (idma_is_valid(out_dma)) {
1008                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1009                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1010         }
1011
1012         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1013             (channel == MEM_FG_SYNC)) {
1014                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1015                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1016
1017                 ipu_dp_dc_enable(channel);
1018         }
1019
1020         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1021
1022         return 0;
1023 }
1024
1025 /*
1026  * This function clear buffer ready for a logical channel.
1027  *
1028  * @param       channel         Input parameter for the logical channel ID.
1029  *
1030  * @param       type            Input parameter which buffer to clear.
1031  *
1032  * @param       bufNum          Input parameter for which buffer number clear
1033  *                              ready state.
1034  *
1035  */
1036 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1037                 uint32_t bufNum)
1038 {
1039         uint32_t dma_ch = channel_2_dma(channel, type);
1040
1041         if (!idma_is_valid(dma_ch))
1042                 return;
1043
1044         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1045         if (bufNum == 0) {
1046                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1047                         __raw_writel(idma_mask(dma_ch),
1048                                         IPU_CHA_BUF0_RDY(dma_ch));
1049                 }
1050         } else {
1051                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1052                         __raw_writel(idma_mask(dma_ch),
1053                                         IPU_CHA_BUF1_RDY(dma_ch));
1054                 }
1055         }
1056         __raw_writel(0x0, IPU_GPR); /* write one to set */
1057 }
1058
1059 /*
1060  * This function disables a logical channel.
1061  *
1062  * @param       channel         Input parameter for the logical channel ID.
1063  *
1064  * @param       wait_for_stop   Flag to set whether to wait for channel end
1065  *                              of frame or return immediately.
1066  *
1067  * @return      This function returns 0 on success or negative error code on
1068  *              fail.
1069  */
1070 int32_t ipu_disable_channel(ipu_channel_t channel)
1071 {
1072         uint32_t reg;
1073         uint32_t in_dma;
1074         uint32_t out_dma;
1075
1076         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1077                 debug("Channel already disabled %d\n",
1078                         IPU_CHAN_ID(channel));
1079                 return 0;
1080         }
1081
1082         /* Get input and output dma channels */
1083         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1084         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1085
1086         if ((idma_is_valid(in_dma) &&
1087                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1088                 && (idma_is_valid(out_dma) &&
1089                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1090                 return -EINVAL;
1091
1092         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1093             (channel == MEM_DC_SYNC)) {
1094                 ipu_dp_dc_disable(channel, 0);
1095         }
1096
1097         /* Disable DMA channel(s) */
1098         if (idma_is_valid(in_dma)) {
1099                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1100                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1101                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1102         }
1103         if (idma_is_valid(out_dma)) {
1104                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1105                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1106                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1107         }
1108
1109         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1110
1111         /* Set channel buffers NOT to be ready */
1112         if (idma_is_valid(in_dma)) {
1113                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1114                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1115         }
1116         if (idma_is_valid(out_dma)) {
1117                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1118                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1119         }
1120
1121         return 0;
1122 }
1123
1124 uint32_t bytes_per_pixel(uint32_t fmt)
1125 {
1126         switch (fmt) {
1127         case IPU_PIX_FMT_GENERIC:       /* generic data */
1128         case IPU_PIX_FMT_RGB332:
1129         case IPU_PIX_FMT_YUV420P:
1130         case IPU_PIX_FMT_YUV422P:
1131                 return 1;
1132         case IPU_PIX_FMT_RGB565:
1133         case IPU_PIX_FMT_YUYV:
1134         case IPU_PIX_FMT_UYVY:
1135                 return 2;
1136         case IPU_PIX_FMT_BGR24:
1137         case IPU_PIX_FMT_RGB24:
1138                 return 3;
1139         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
1140         case IPU_PIX_FMT_BGR32:
1141         case IPU_PIX_FMT_BGRA32:
1142         case IPU_PIX_FMT_RGB32:
1143         case IPU_PIX_FMT_RGBA32:
1144         case IPU_PIX_FMT_ABGR32:
1145                 return 4;
1146         default:
1147                 return 1;
1148         }
1149         return 0;
1150 }
1151
1152 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1153 {
1154         switch (fmt) {
1155         case IPU_PIX_FMT_RGB666:
1156         case IPU_PIX_FMT_RGB565:
1157         case IPU_PIX_FMT_BGR24:
1158         case IPU_PIX_FMT_RGB24:
1159         case IPU_PIX_FMT_BGR32:
1160         case IPU_PIX_FMT_BGRA32:
1161         case IPU_PIX_FMT_RGB32:
1162         case IPU_PIX_FMT_RGBA32:
1163         case IPU_PIX_FMT_ABGR32:
1164         case IPU_PIX_FMT_LVDS666:
1165         case IPU_PIX_FMT_LVDS888:
1166                 return RGB;
1167
1168         default:
1169                 return YCbCr;
1170         }
1171         return RGB;
1172 }
1173
1174 /* should be removed when clk framework is availiable */
1175 int ipu_set_ldb_clock(int rate)
1176 {
1177         ldb_clk.rate = rate;
1178
1179         return 0;
1180 }