drivers/video/ipu_disp.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /* #define DEBUG */
  15
  16 #include <common.h>
  17 #include <ipu.h>
  18 #include <linux/types.h>
  19 #include <asm/errno.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include "ipu_regs.h"
  24
  25 enum csc_type_t {
  26         RGB2YUV = 0,
  27         YUV2RGB,
  28         RGB2RGB,
  29         YUV2YUV,
  30         CSC_NONE,
  31         CSC_NUM
  32 };
  33
  34 struct dp_csc_param_t {
  35         int mode;
  36         const int (*coeff)[5][3];
  37 };
  38
  39 #define SYNC_WAVE 0
  40
  41 /* DC display ID assignments */
  42 #define DC_DISP_ID_SYNC(di)     (di)
  43 #define DC_DISP_ID_SERIAL       2
  44 #define DC_DISP_ID_ASYNC        3
  45
  46 static int dmfc_type_setup;
  47 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
  48 static int g_di1_tvout;
  49
  50 void ipu_dmfc_init(int dmfc_type, int first)
  51 {
  52         u32 dmfc_wr_chan, dmfc_dp_chan;
  53
  54         if (first) {
  55                 if (dmfc_type_setup > dmfc_type)
  56                         dmfc_type = dmfc_type_setup;
  57                 else
  58                         dmfc_type_setup = dmfc_type;
  59
  60                 /* disable DMFC-IC channel*/
  61                 __raw_writel(0x2, DMFC_IC_CTRL);
  62         } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
  63                 printf("DMFC high resolution has set, will not change\n");
  64                 return;
  65         } else
  66                 dmfc_type_setup = dmfc_type;
  67
  68         if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
  69                 /* 1 - segment 0~3;
  70                  * 5B - segement 4, 5;
  71                  * 5F - segement 6, 7;
  72                  * 1C, 2C and 6B, 6F unused;
  73                  */
  74                 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
  75                 dmfc_wr_chan = 0x00000088;
  76                 dmfc_dp_chan = 0x00009694;
  77                 dmfc_size_28 = 256 * 4;
  78                 dmfc_size_29 = 0;
  79                 dmfc_size_24 = 0;
  80                 dmfc_size_27 = 128 * 4;
  81                 dmfc_size_23 = 128 * 4;
  82         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
  83                 /* 1 - segment 0, 1;
  84                  * 5B - segement 2~5;
  85                  * 5F - segement 6,7;
  86                  * 1C, 2C and 6B, 6F unused;
  87                  */
  88                 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
  89                 dmfc_wr_chan = 0x00000090;
  90                 dmfc_dp_chan = 0x0000968a;
  91                 dmfc_size_28 = 128 * 4;
  92                 dmfc_size_29 = 0;
  93                 dmfc_size_24 = 0;
  94                 dmfc_size_27 = 128 * 4;
  95                 dmfc_size_23 = 256 * 4;
  96         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
  97                 /* 5B - segement 0~3;
  98                  * 5F - segement 4~7;
  99                  * 1, 1C, 2C and 6B, 6F unused;
 100                  */
 101                 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
 102                 dmfc_wr_chan = 0x00000000;
 103                 dmfc_dp_chan = 0x00008c88;
 104                 dmfc_size_28 = 0;
 105                 dmfc_size_29 = 0;
 106                 dmfc_size_24 = 0;
 107                 dmfc_size_27 = 256 * 4;
 108                 dmfc_size_23 = 256 * 4;
 109         } else {
 110                 /* 1 - segment 0, 1;
 111                  * 5B - segement 4, 5;
 112                  * 5F - segement 6, 7;
 113                  * 1C, 2C and 6B, 6F unused;
 114                  */
 115                 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
 116                 dmfc_wr_chan = 0x00000090;
 117                 dmfc_dp_chan = 0x00009694;
 118                 dmfc_size_28 = 128 * 4;
 119                 dmfc_size_29 = 0;
 120                 dmfc_size_24 = 0;
 121                 dmfc_size_27 = 128 * 4;
 122                 dmfc_size_23 = 128 * 4;
 123         }
 124         __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
 125         __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
 126         __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
 127         /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
 128         __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
 129 }
 130
 131 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
 132 {
 133         u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
 134
 135         if (width >= HIGH_RESOLUTION_WIDTH) {
 136                 if (dma_chan == 23)
 137                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
 138                 else if (dma_chan == 28)
 139                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
 140         }
 141
 142         if (dma_chan == 23) { /*5B*/
 143                 if (dmfc_size_23 / width > 3)
 144                         dmfc_gen1 |= 1UL << 20;
 145                 else
 146                         dmfc_gen1 &= ~(1UL << 20);
 147         } else if (dma_chan == 24) { /*6B*/
 148                 if (dmfc_size_24 / width > 1)
 149                         dmfc_gen1 |= 1UL << 22;
 150                 else
 151                         dmfc_gen1 &= ~(1UL << 22);
 152         } else if (dma_chan == 27) { /*5F*/
 153                 if (dmfc_size_27 / width > 2)
 154                         dmfc_gen1 |= 1UL << 21;
 155                 else
 156                         dmfc_gen1 &= ~(1UL << 21);
 157         } else if (dma_chan == 28) { /*1*/
 158                 if (dmfc_size_28 / width > 2)
 159                         dmfc_gen1 |= 1UL << 16;
 160                 else
 161                         dmfc_gen1 &= ~(1UL << 16);
 162         } else if (dma_chan == 29) { /*6F*/
 163                 if (dmfc_size_29 / width > 1)
 164                         dmfc_gen1 |= 1UL << 23;
 165                 else
 166                         dmfc_gen1 &= ~(1UL << 23);
 167         }
 168
 169         __raw_writel(dmfc_gen1, DMFC_GENERAL1);
 170 }
 171
 172 static void ipu_di_data_wave_config(int di,
 173                                      int wave_gen,
 174                                      int access_size, int component_size)
 175 {
 176         u32 reg;
 177         reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
 178             (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
 179         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 180 }
 181
 182 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
 183                                     int up, int down)
 184 {
 185         u32 reg;
 186
 187         reg = __raw_readl(DI_DW_GEN(di, wave_gen));
 188         reg &= ~(0x3 << (di_pin * 2));
 189         reg |= set << (di_pin * 2);
 190         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 191
 192         __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
 193 }
 194
 195 static void ipu_di_sync_config(int di, int wave_gen,
 196                                 int run_count, int run_src,
 197                                 int offset_count, int offset_src,
 198                                 int repeat_count, int cnt_clr_src,
 199                                 int cnt_polarity_gen_en,
 200                                 int cnt_polarity_clr_src,
 201                                 int cnt_polarity_trigger_src,
 202                                 int cnt_up, int cnt_down)
 203 {
 204         u32 reg;
 205
 206         if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
 207                 (repeat_count >= 0x1000) ||
 208                 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
 209                 printf("DI%d counters out of range.\n", di);
 210                 return;
 211         }
 212
 213         reg = (run_count << 19) | (++run_src << 16) |
 214             (offset_count << 3) | ++offset_src;
 215         __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
 216         reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
 217             (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
 218         reg |= (cnt_down << 16) | cnt_up;
 219         if (repeat_count == 0) {
 220                 /* Enable auto reload */
 221                 reg |= 0x10000000;
 222         }
 223         __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
 224         reg = __raw_readl(DI_STP_REP(di, wave_gen));
 225         reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
 226         reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
 227         __raw_writel(reg, DI_STP_REP(di, wave_gen));
 228 }
 229
 230 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
 231 {
 232         int ptr = map * 3 + byte_num;
 233         u32 reg;
 234
 235         reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
 236         reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
 237         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 238         __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
 239
 240         reg = __raw_readl(DC_MAP_CONF_PTR(map));
 241         reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
 242         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 243         __raw_writel(reg, DC_MAP_CONF_PTR(map));
 244 }
 245
 246 static void ipu_dc_map_clear(int map)
 247 {
 248         u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
 249         __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
 250                      DC_MAP_CONF_PTR(map));
 251 }
 252
 253 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
 254                                int wave, int glue, int sync)
 255 {
 256         u32 reg;
 257         int stop = 1;
 258
 259         reg = sync;
 260         reg |= (glue << 4);
 261         reg |= (++wave << 11);
 262         reg |= (++map << 15);
 263         reg |= (operand << 20) & 0xFFF00000;
 264         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
 265
 266         reg = (operand >> 12);
 267         reg |= opcode << 4;
 268         reg |= (stop << 9);
 269         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
 270 }
 271
 272 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
 273 {
 274         u32 reg;
 275
 276         reg = __raw_readl(DC_RL_CH(chan, event));
 277         reg &= ~(0xFFFF << (16 * (event & 0x1)));
 278         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 279         __raw_writel(reg, DC_RL_CH(chan, event));
 280 }
 281
 282 /* Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
 283  * U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
 284  * V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;
 285  */
 286 static const int rgb2ycbcr_coeff[5][3] = {
 287         {0x4D, 0x96, 0x1D},
 288         {0x3D5, 0x3AB, 0x80},
 289         {0x80, 0x395, 0x3EB},
 290         {0x0000, 0x0200, 0x0200},       /* B0, B1, B2 */
 291         {0x2, 0x2, 0x2},        /* S0, S1, S2 */
 292 };
 293
 294 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 295  * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 296  * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
 297  */
 298 static const int ycbcr2rgb_coeff[5][3] = {
 299         {0x095, 0x000, 0x0CC},
 300         {0x095, 0x3CE, 0x398},
 301         {0x095, 0x0FF, 0x000},
 302         {0x3E42, 0x010A, 0x3DD6},       /*B0,B1,B2 */
 303         {0x1, 0x1, 0x1},        /*S0,S1,S2 */
 304 };
 305
 306 #define mask_a(a) ((u32)(a) & 0x3FF)
 307 #define mask_b(b) ((u32)(b) & 0x3FFF)
 308
 309 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
 310 static int rgb_to_yuv(int n, int red, int green, int blue)
 311 {
 312         int c;
 313         c = red * rgb2ycbcr_coeff[n][0];
 314         c += green * rgb2ycbcr_coeff[n][1];
 315         c += blue * rgb2ycbcr_coeff[n][2];
 316         c /= 16;
 317         c += rgb2ycbcr_coeff[3][n] * 4;
 318         c += 8;
 319         c /= 16;
 320         if (c < 0)
 321                 c = 0;
 322         if (c > 255)
 323                 c = 255;
 324         return c;
 325 }
 326
 327 /*
 328  * Row is for BG:       RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 329  * Column is for FG:    RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 330  */
 331 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 332         {
 333                 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
 334                 {0, 0},
 335                 {0, 0},
 336                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
 337                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
 338         },
 339         {
 340                 {0, 0},
 341                 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
 342                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
 343                 {0, 0},
 344                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
 345         },
 346         {
 347                 {0, 0},
 348                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 349                 {0, 0},
 350                 {0, 0},
 351                 {0, 0}
 352         },
 353         {
 354                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 355                 {0, 0},
 356                 {0, 0},
 357                 {0, 0},
 358                 {0, 0}
 359         },
 360         {
 361                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 362                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 363                 {0, 0},
 364                 {0, 0},
 365                 {0, 0}
 366         }
 367 };
 368
 369 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
 370 static int color_key_4rgb = 1;
 371
 372 static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
 373                         unsigned char srm_mode_update)
 374 {
 375         u32 reg;
 376         const int (*coeff)[5][3];
 377
 378         if (dp_csc_param.mode >= 0) {
 379                 reg = __raw_readl(DP_COM_CONF());
 380                 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 381                 reg |= dp_csc_param.mode;
 382                 __raw_writel(reg, DP_COM_CONF());
 383         }
 384
 385         coeff = dp_csc_param.coeff;
 386
 387         if (coeff) {
 388                 __raw_writel(mask_a((*coeff)[0][0]) |
 389                                 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
 390                 __raw_writel(mask_a((*coeff)[0][2]) |
 391                                 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
 392                 __raw_writel(mask_a((*coeff)[1][1]) |
 393                                 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
 394                 __raw_writel(mask_a((*coeff)[2][0]) |
 395                                 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
 396                 __raw_writel(mask_a((*coeff)[2][2]) |
 397                                 (mask_b((*coeff)[3][0]) << 16) |
 398                                 ((*coeff)[4][0] << 30), DP_CSC_0());
 399                 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
 400                                 (mask_b((*coeff)[3][2]) << 16) |
 401                                 ((*coeff)[4][2] << 30), DP_CSC_1());
 402         }
 403
 404         if (srm_mode_update) {
 405                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 406                 __raw_writel(reg, IPU_SRM_PRI2);
 407         }
 408 }
 409
 410 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 411                  uint32_t out_pixel_fmt)
 412 {
 413         int in_fmt, out_fmt;
 414         int dp;
 415         int partial = 0;
 416         uint32_t reg;
 417
 418         if (channel == MEM_FG_SYNC) {
 419                 dp = DP_SYNC;
 420                 partial = 1;
 421         } else if (channel == MEM_BG_SYNC) {
 422                 dp = DP_SYNC;
 423                 partial = 0;
 424         } else if (channel == MEM_BG_ASYNC0) {
 425                 dp = DP_ASYNC0;
 426                 partial = 0;
 427         } else {
 428                 return -EINVAL;
 429         }
 430
 431         in_fmt = format_to_colorspace(in_pixel_fmt);
 432         out_fmt = format_to_colorspace(out_pixel_fmt);
 433
 434         if (partial) {
 435                 if (in_fmt == RGB) {
 436                         if (out_fmt == RGB)
 437                                 fg_csc_type = RGB2RGB;
 438                         else
 439                                 fg_csc_type = RGB2YUV;
 440                 } else {
 441                         if (out_fmt == RGB)
 442                                 fg_csc_type = YUV2RGB;
 443                         else
 444                                 fg_csc_type = YUV2YUV;
 445                 }
 446         } else {
 447                 if (in_fmt == RGB) {
 448                         if (out_fmt == RGB)
 449                                 bg_csc_type = RGB2RGB;
 450                         else
 451                                 bg_csc_type = RGB2YUV;
 452                 } else {
 453                         if (out_fmt == RGB)
 454                                 bg_csc_type = YUV2RGB;
 455                         else
 456                                 bg_csc_type = YUV2YUV;
 457                 }
 458         }
 459
 460         /* Transform color key from rgb to yuv if CSC is enabled */
 461         reg = __raw_readl(DP_COM_CONF());
 462         if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
 463                 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
 464                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
 465                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
 466                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
 467                 int red, green, blue;
 468                 int y, u, v;
 469                 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
 470                         0xFFFFFFL;
 471
 472                 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
 473                         color_key);
 474
 475                 red = (color_key >> 16) & 0xFF;
 476                 green = (color_key >> 8) & 0xFF;
 477                 blue = color_key & 0xFF;
 478
 479                 y = rgb_to_yuv(0, red, green, blue);
 480                 u = rgb_to_yuv(1, red, green, blue);
 481                 v = rgb_to_yuv(2, red, green, blue);
 482                 color_key = (y << 16) | (u << 8) | v;
 483
 484                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
 485                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
 486                 color_key_4rgb = 0;
 487
 488                 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
 489                         color_key);
 490         }
 491
 492         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
 493
 494         return 0;
 495 }
 496
 497 void ipu_dp_uninit(ipu_channel_t channel)
 498 {
 499         int dp;
 500         int partial = 0;
 501
 502         if (channel == MEM_FG_SYNC) {
 503                 dp = DP_SYNC;
 504                 partial = 1;
 505         } else if (channel == MEM_BG_SYNC) {
 506                 dp = DP_SYNC;
 507                 partial = 0;
 508         } else if (channel == MEM_BG_ASYNC0) {
 509                 dp = DP_ASYNC0;
 510                 partial = 0;
 511         } else {
 512                 return;
 513         }
 514
 515         if (partial)
 516                 fg_csc_type = CSC_NONE;
 517         else
 518                 bg_csc_type = CSC_NONE;
 519
 520         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
 521 }
 522
 523 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
 524 {
 525         u32 reg = 0;
 526
 527         if ((dc_chan == 1) || (dc_chan == 5)) {
 528                 if (interlaced) {
 529                         ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
 530                         ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
 531                         ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
 532                 } else {
 533                         if (di) {
 534                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
 535                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
 536                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 537                                         4, 1);
 538                         } else {
 539                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
 540                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
 541                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 542                                         7, 1);
 543                         }
 544                 }
 545                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 546                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 547                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 548                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 549                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 550                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 551
 552                 reg = 0x2;
 553                 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 554                 reg |= di << 2;
 555                 if (interlaced)
 556                         reg |= DC_WR_CH_CONF_FIELD_MODE;
 557         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 558                 /* async channels */
 559                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
 560                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
 561
 562                 reg = 0x3;
 563                 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 564         }
 565         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 566
 567         __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
 568
 569         __raw_writel(0x00000084, DC_GEN);
 570 }
 571
 572 void ipu_dc_uninit(int dc_chan)
 573 {
 574         if ((dc_chan == 1) || (dc_chan == 5)) {
 575                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
 576                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
 577                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
 578                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 579                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 580                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 581                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 582                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 583                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 584         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 585                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 586                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
 587                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
 588                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
 589                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
 590                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
 591                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
 592                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
 593                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
 594                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
 595                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
 596                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
 597         }
 598 }
 599
 600 void ipu_dp_dc_enable(ipu_channel_t channel)
 601 {
 602         int di;
 603         uint32_t reg;
 604         uint32_t dc_chan;
 605
 606         if (channel == MEM_FG_SYNC)
 607                 dc_chan = 5;
 608         if (channel == MEM_DC_SYNC)
 609                 dc_chan = 1;
 610         else if (channel == MEM_BG_SYNC)
 611                 dc_chan = 5;
 612         else
 613                 return;
 614
 615         if (channel == MEM_FG_SYNC) {
 616                 /* Enable FG channel */
 617                 reg = __raw_readl(DP_COM_CONF());
 618                 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
 619
 620                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 621                 __raw_writel(reg, IPU_SRM_PRI2);
 622                 return;
 623         }
 624
 625         di = g_dc_di_assignment[dc_chan];
 626
 627         /* Make sure other DC sync channel is not assigned same DI */
 628         reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
 629         if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
 630                 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
 631                 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
 632                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 633         }
 634
 635         reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 636         reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
 637         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 638
 639         clk_enable(g_pixel_clk[di]);
 640 }
 641
 642 static unsigned char dc_swap;
 643
 644 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
 645 {
 646         uint32_t reg;
 647         uint32_t csc;
 648         uint32_t dc_chan = 0;
 649         int timeout = 50;
 650         int irq = 0;
 651
 652         dc_swap = swap;
 653
 654         if (channel == MEM_DC_SYNC) {
 655                 dc_chan = 1;
 656                 irq = IPU_IRQ_DC_FC_1;
 657         } else if (channel == MEM_BG_SYNC) {
 658                 dc_chan = 5;
 659                 irq = IPU_IRQ_DP_SF_END;
 660         } else if (channel == MEM_FG_SYNC) {
 661                 /* Disable FG channel */
 662                 dc_chan = 5;
 663
 664                 reg = __raw_readl(DP_COM_CONF());
 665                 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
 666                 if (csc == DP_COM_CONF_CSC_DEF_FG)
 667                         reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 668
 669                 reg &= ~DP_COM_CONF_FG_EN;
 670                 __raw_writel(reg, DP_COM_CONF());
 671
 672                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 673                 __raw_writel(reg, IPU_SRM_PRI2);
 674
 675                 timeout = 50;
 676
 677                 /*
 678                  * Wait for DC triple buffer to empty,
 679                  * this check is useful for tv overlay.
 680                  */
 681                 if (g_dc_di_assignment[dc_chan] == 0)
 682                         while ((__raw_readl(DC_STAT) & 0x00000002)
 683                                != 0x00000002) {
 684                                 udelay(2000);
 685                                 timeout -= 2;
 686                                 if (timeout <= 0)
 687                                         break;
 688                         }
 689                 else if (g_dc_di_assignment[dc_chan] == 1)
 690                         while ((__raw_readl(DC_STAT) & 0x00000020)
 691                                != 0x00000020) {
 692                                 udelay(2000);
 693                                 timeout -= 2;
 694                                 if (timeout <= 0)
 695                                         break;
 696                         }
 697                 return;
 698         } else {
 699                 return;
 700         }
 701
 702         if (dc_swap) {
 703                 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
 704                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 705                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 706                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 707                 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
 708                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 709         } else {
 710                 /* Make sure that we leave at the irq starting edge */
 711                 __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
 712                 do {
 713                         reg = __raw_readl(IPUIRQ_2_STATREG(irq));
 714                 } while (!(reg & IPUIRQ_2_MASK(irq)));
 715
 716                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 717                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 718                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 719
 720                 reg = __raw_readl(IPU_DISP_GEN);
 721                 if (g_dc_di_assignment[dc_chan])
 722                         reg &= ~DI1_COUNTER_RELEASE;
 723                 else
 724                         reg &= ~DI0_COUNTER_RELEASE;
 725                 __raw_writel(reg, IPU_DISP_GEN);
 726
 727                 /* Clock is already off because it must be done quickly, but
 728                    we need to fix the ref count */
 729                 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
 730         }
 731 }
 732
 733 void ipu_init_dc_mappings(void)
 734 {
 735         /* IPU_PIX_FMT_RGB24 */
 736         ipu_dc_map_clear(0);
 737         ipu_dc_map_config(0, 0, 7, 0xFF);
 738         ipu_dc_map_config(0, 1, 15, 0xFF);
 739         ipu_dc_map_config(0, 2, 23, 0xFF);
 740
 741         /* IPU_PIX_FMT_RGB666 */
 742         ipu_dc_map_clear(1);
 743         ipu_dc_map_config(1, 0, 5, 0xFC);
 744         ipu_dc_map_config(1, 1, 11, 0xFC);
 745         ipu_dc_map_config(1, 2, 17, 0xFC);
 746
 747         /* IPU_PIX_FMT_YUV444 */
 748         ipu_dc_map_clear(2);
 749         ipu_dc_map_config(2, 0, 15, 0xFF);
 750         ipu_dc_map_config(2, 1, 23, 0xFF);
 751         ipu_dc_map_config(2, 2, 7, 0xFF);
 752
 753         /* IPU_PIX_FMT_RGB565 */
 754         ipu_dc_map_clear(3);
 755         ipu_dc_map_config(3, 0, 4, 0xF8);
 756         ipu_dc_map_config(3, 1, 10, 0xFC);
 757         ipu_dc_map_config(3, 2, 15, 0xF8);
 758
 759         /* IPU_PIX_FMT_LVDS666 */
 760         ipu_dc_map_clear(4);
 761         ipu_dc_map_config(4, 0, 5, 0xFC);
 762         ipu_dc_map_config(4, 1, 11, 0xFC);
 763         ipu_dc_map_config(4, 2, 17, 0xFC);
 764 }
 765
 766 static int ipu_pixfmt_to_map(uint32_t fmt)
 767 {
 768         switch (fmt) {
 769         case IPU_PIX_FMT_GENERIC:
 770         case IPU_PIX_FMT_RGB24:
 771         case IPU_PIX_FMT_LVDS888:
 772                 return 0;
 773         case IPU_PIX_FMT_RGB666:
 774                 return 1;
 775         case IPU_PIX_FMT_YUV444:
 776                 return 2;
 777         case IPU_PIX_FMT_RGB565:
 778                 return 3;
 779         case IPU_PIX_FMT_LVDS666:
 780                 return 4;
 781         }
 782
 783         return -EINVAL;
 784 }
 785
 786 /*
 787  * This function is called to initialize a synchronous LCD panel.
 788  *
 789  * @param       disp            The DI the panel is attached to.
 790  *
 791  * @param       pixel_clk       Desired pixel clock frequency in Hz.
 792  *
 793  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 794  *                              Pixel format is a FOURCC ASCII code.
 795  *
 796  * @param       width           The width of panel in pixels.
 797  *
 798  * @param       height          The height of panel in pixels.
 799  *
 800  * @param       hStartWidth     The number of pixel clocks between the HSYNC
 801  *                              signal pulse and the start of valid data.
 802  *
 803  * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
 804  *                              clocks.
 805  *
 806  * @param       hEndWidth       The number of pixel clocks between the end of
 807  *                              valid data and the HSYNC signal for next line.
 808  *
 809  * @param       vStartWidth     The number of lines between the VSYNC
 810  *                              signal pulse and the start of valid data.
 811  *
 812  * @param       vSyncWidth      The width of the VSYNC signal in units of lines
 813  *
 814  * @param       vEndWidth       The number of lines between the end of valid
 815  *                              data and the VSYNC signal for next frame.
 816  *
 817  * @param       sig             Bitfield of signal polarities for LCD interface.
 818  *
 819  * @return      This function returns 0 on success or negative error code on
 820  *              fail.
 821  */
 822
 823 int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 824                         uint16_t width, uint16_t height,
 825                         uint32_t pixel_fmt,
 826                         uint16_t h_start_width, uint16_t h_sync_width,
 827                         uint16_t h_end_width, uint16_t v_start_width,
 828                         uint16_t v_sync_width, uint16_t v_end_width,
 829                         uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
 830 {
 831         uint32_t reg;
 832         uint32_t di_gen, vsync_cnt;
 833         uint32_t div, rounded_pixel_clk;
 834         uint32_t h_total, v_total;
 835         int map;
 836         struct clk *di_parent;
 837
 838         debug("panel size = %d x %d\n", width, height);
 839
 840         if ((v_sync_width == 0) || (h_sync_width == 0))
 841                 return -EINVAL;
 842
 843         /* adapt panel to ipu restricitions */
 844         if (v_end_width < 2) {
 845                 v_end_width = 2;
 846                 puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n");
 847         }
 848
 849         h_total = width + h_sync_width + h_start_width + h_end_width;
 850         v_total = height + v_sync_width + v_start_width + v_end_width;
 851
 852         /* Init clocking */
 853         debug("pixel clk = %dHz\n", pixel_clk);
 854
 855         if (sig.ext_clk) {
 856                 if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
 857                         /*
 858                          * Set the  PLL to be an even multiple
 859                          * of the pixel clock.
 860                          */
 861                         if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
 862                                 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
 863                                 di_parent = clk_get_parent(g_di_clk[disp]);
 864                                 rounded_pixel_clk =
 865                                         clk_round_rate(g_pixel_clk[disp],
 866                                                 pixel_clk);
 867                                 if (di_parent != NULL) {
 868                                         div  = clk_get_rate(di_parent) /
 869                                                 rounded_pixel_clk;
 870                                         if (div % 2)
 871                                                 div++;
 872                                         if (clk_get_rate(di_parent) != div *
 873                                                 rounded_pixel_clk)
 874                                                 clk_set_rate(di_parent,
 875                                                         div * rounded_pixel_clk);
 876                                         udelay(10000);
 877                                         clk_set_rate(g_di_clk[disp],
 878                                                 2 * rounded_pixel_clk);
 879                                         udelay(10000);
 880                                 }
 881                         }
 882                 }
 883                 clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
 884         } else {
 885                 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
 886                         clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
 887         }
 888
 889         /* Enable for a divide by 2 clock change. */
 890         reg = __raw_readl(IPU_PM);
 891         reg &= ~(0x7f << 7);
 892         reg |= 0x20 << 7;
 893         reg &= ~(0x7f << 23);
 894         reg |= 0x20 << 23;
 895         __raw_writel(reg, IPU_PM);
 896
 897         di_gen = 0;
 898
 899         if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
 900                         pixel_fmt != IPU_PIX_FMT_LVDS888) {
 901                 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
 902                 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 903                 udelay(5000);
 904                 /* Get integer portion of divider */
 905                 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
 906                         rounded_pixel_clk;
 907                 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
 908         } else {
 909                 rounded_pixel_clk = clk_get_rate(clk_get_parent(g_pixel_clk[disp]));
 910                 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 911                 div = 1;
 912                 ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
 913                 di_gen |= (6 << 24);
 914                 di_gen |= DI_GEN_DI_CLK_EXT;
 915         }
 916         ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
 917
 918         map = ipu_pixfmt_to_map(pixel_fmt);
 919         if (map < 0) {
 920                 printf("IPU_DISP: No MAP for pixel format: %c%c%c%c\n",
 921                         pixel_fmt, pixel_fmt >> 8, pixel_fmt >> 16,
 922                         pixel_fmt >> 24);
 923                 return map;
 924         }
 925
 926         if (sig.interlaced) {
 927                 /* Setup internal HSYNC waveform */
 928                 ipu_di_sync_config(
 929                                 disp,           /* display */
 930                                 1,              /* counter */
 931                                 h_total / 2 - 1,/* run count */
 932                                 DI_SYNC_CLK,    /* run_resolution */
 933                                 0,              /* offset */
 934                                 DI_SYNC_NONE,   /* offset resolution */
 935                                 0,              /* repeat count */
 936                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
 937                                 0,              /* CNT_POLARITY_GEN_EN */
 938                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
 939                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
 940                                 0,              /* COUNT UP */
 941                                 0               /* COUNT DOWN */
 942                                 );
 943
 944                 /* Field 1 VSYNC waveform */
 945                 ipu_di_sync_config(
 946                                 disp,           /* display */
 947                                 2,              /* counter */
 948                                 h_total - 1,    /* run count */
 949                                 DI_SYNC_CLK,    /* run_resolution */
 950                                 0,              /* offset */
 951                                 DI_SYNC_NONE,   /* offset resolution */
 952                                 0,              /* repeat count */
 953                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
 954                                 0,              /* CNT_POLARITY_GEN_EN */
 955                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
 956                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
 957                                 0,              /* COUNT UP */
 958                                 4               /* COUNT DOWN */
 959                                 );
 960
 961                 /* Setup internal HSYNC waveform */
 962                 ipu_di_sync_config(
 963                                 disp,           /* display */
 964                                 3,              /* counter */
 965                                 v_total * 2 - 1,/* run count */
 966                                 DI_SYNC_INT_HSYNC,      /* run_resolution */
 967                                 1,              /* offset */
 968                                 DI_SYNC_INT_HSYNC,      /* offset resolution */
 969                                 0,              /* repeat count */
 970                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
 971                                 0,              /* CNT_POLARITY_GEN_EN */
 972                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
 973                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
 974                                 0,              /* COUNT UP */
 975                                 4               /* COUNT DOWN */
 976                                 );
 977
 978                 /* Active Field ? */
 979                 ipu_di_sync_config(
 980                                 disp,           /* display */
 981                                 4,              /* counter */
 982                                 v_total / 2 - 1,/* run count */
 983                                 DI_SYNC_HSYNC,  /* run_resolution */
 984                                 v_start_width,  /*  offset */
 985                                 DI_SYNC_HSYNC,  /* offset resolution */
 986                                 2,              /* repeat count */
 987                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
 988                                 0,              /* CNT_POLARITY_GEN_EN */
 989                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
 990                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
 991                                 0,              /* COUNT UP */
 992                                 0               /* COUNT DOWN */
 993                                 );
 994
 995                 /* Active Line */
 996                 ipu_di_sync_config(
 997                                 disp,           /* display */
 998                                 5,              /* counter */
 999                                 0,              /* run count */
1000                                 DI_SYNC_HSYNC,  /* run_resolution */
1001                                 0,              /*  offset */
1002                                 DI_SYNC_NONE,   /* offset resolution */
1003                                 height / 2,     /* repeat count */
1004                                 4,              /* CNT_CLR_SEL */
1005                                 0,              /* CNT_POLARITY_GEN_EN */
1006                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1007                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1008                                 0,              /* COUNT UP */
1009                                 0               /* COUNT DOWN */
1010                                 );
1011
1012                 /* Field 0 VSYNC waveform */
1013                 ipu_di_sync_config(
1014                                 disp,           /* display */
1015                                 6,              /* counter */
1016                                 v_total - 1,    /* run count */
1017                                 DI_SYNC_HSYNC,  /* run_resolution */
1018                                 0,              /* offset */
1019                                 DI_SYNC_NONE,   /* offset resolution */
1020                                 0,              /* repeat count */
1021                                 DI_SYNC_NONE,   /* CNT_CLR_SEL  */
1022                                 0,              /* CNT_POLARITY_GEN_EN */
1023                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1024                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1025                                 0,              /* COUNT UP */
1026                                 0               /* COUNT DOWN */
1027                                 );
1028
1029                 /* DC VSYNC waveform */
1030                 vsync_cnt = 7;
1031                 ipu_di_sync_config(
1032                                 disp,           /* display */
1033                                 7,              /* counter */
1034                                 v_total / 2 - 1,/* run count */
1035                                 DI_SYNC_HSYNC,  /* run_resolution  */
1036                                 9,              /* offset  */
1037                                 DI_SYNC_HSYNC,  /* offset resolution */
1038                                 2,              /* repeat count */
1039                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1040                                 0,              /* CNT_POLARITY_GEN_EN */
1041                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1042                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1043                                 0,              /* COUNT UP */
1044                                 0               /* COUNT DOWN */
1045                                 );
1046
1047                 /* active pixel waveform */
1048                 ipu_di_sync_config(
1049                                 disp,           /* display */
1050                                 8,              /* counter */
1051                                 0,              /* run count  */
1052                                 DI_SYNC_CLK,    /* run_resolution */
1053                                 h_start_width,  /* offset  */
1054                                 DI_SYNC_CLK,    /* offset resolution */
1055                                 width,          /* repeat count  */
1056                                 5,              /* CNT_CLR_SEL  */
1057                                 0,              /* CNT_POLARITY_GEN_EN  */
1058                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1059                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL  */
1060                                 0,              /* COUNT UP  */
1061                                 0               /* COUNT DOWN */
1062                                 );
1063
1064                 ipu_di_sync_config(
1065                                 disp,           /* display */
1066                                 9,              /* counter */
1067                                 v_total - 1,    /* run count */
1068                                 DI_SYNC_INT_HSYNC,/* run_resolution */
1069                                 v_total / 2,    /* offset  */
1070                                 DI_SYNC_INT_HSYNC,/* offset resolution  */
1071                                 0,              /* repeat count */
1072                                 DI_SYNC_HSYNC,  /* CNT_CLR_SEL */
1073                                 0,              /* CNT_POLARITY_GEN_EN  */
1074                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL  */
1075                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1076                                 0,              /* COUNT UP */
1077                                 4               /* COUNT DOWN */
1078                                 );
1079
1080                 /* set gentime select and tag sel */
1081                 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1082                 reg &= 0x1FFFFFFF;
1083                 reg |= ((3 - 1) << 29) | 0x00008000;
1084                 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1085
1086                 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1087
1088                 /* set y_sel = 1 */
1089                 di_gen |= 0x10000000;
1090                 di_gen |= DI_GEN_POLARITY_5;
1091                 di_gen |= DI_GEN_POLARITY_8;
1092         } else {
1093                 /* Setup internal HSYNC waveform */
1094                 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1095                                 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1096                                 0, DI_SYNC_NONE,
1097                                 DI_SYNC_NONE, 0, 0);
1098
1099                 /* Setup external (delayed) HSYNC waveform */
1100                 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1101                                 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1102                                 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1103                                 DI_SYNC_CLK, 0, h_sync_width * 2);
1104                 /* Setup VSYNC waveform */
1105                 vsync_cnt = DI_SYNC_VSYNC;
1106                 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1107                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1108                                 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1109                                 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1110                 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1111
1112                 /* Setup active data waveform to sync with DC */
1113                 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1114                                 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1115                                 height,
1116                                 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1117                                 DI_SYNC_NONE, 0, 0);
1118                 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1119                                 h_sync_width + h_start_width, DI_SYNC_CLK,
1120                                 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1121                                 0);
1122
1123                 /* reset all unused counters */
1124                 __raw_writel(0, DI_SW_GEN0(disp, 6));
1125                 __raw_writel(0, DI_SW_GEN1(disp, 6));
1126                 __raw_writel(0, DI_SW_GEN0(disp, 7));
1127                 __raw_writel(0, DI_SW_GEN1(disp, 7));
1128                 __raw_writel(0, DI_SW_GEN0(disp, 8));
1129                 __raw_writel(0, DI_SW_GEN1(disp, 8));
1130                 __raw_writel(0, DI_SW_GEN0(disp, 9));
1131                 __raw_writel(0, DI_SW_GEN1(disp, 9));
1132
1133                 reg = __raw_readl(DI_STP_REP(disp, 6));
1134                 reg &= 0x0000FFFF;
1135                 __raw_writel(reg, DI_STP_REP(disp, 6));
1136                 __raw_writel(0, DI_STP_REP(disp, 7));
1137                 __raw_writel(0, DI_STP_REP(disp, 9));
1138
1139                 h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
1140                 ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
1141                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
1142                                 DI_SYNC_NONE, 0, 0);
1143
1144                 /* Init template microcode */
1145                 if (disp) {
1146                         ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1147                         ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1148                         ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1149                 } else {
1150                         ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1151                         ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1152                         ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1153                 }
1154
1155                 if (sig.Hsync_pol)
1156                         di_gen |= DI_GEN_POLARITY_2;
1157                 if (sig.Vsync_pol)
1158                         di_gen |= DI_GEN_POLARITY_3;
1159
1160                 if (sig.clk_pol)
1161                         di_gen |= DI_GEN_POL_CLK;
1162
1163                 /* Set the clock to stop at counter 6. */
1164                 di_gen |= 0x6000000;
1165         }
1166
1167         __raw_writel(di_gen, DI_GENERAL(disp));
1168
1169         if (sig.interlaced)
1170                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1171                                 0x00000002, DI_SYNC_AS_GEN(disp));
1172         else
1173                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
1174                                 DI_SYNC_AS_GEN(disp));
1175
1176         reg = __raw_readl(DI_POL(disp));
1177         reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1178         if (sig.enable_pol)
1179                 reg |= DI_POL_DRDY_POLARITY_15;
1180         if (sig.data_pol)
1181                 reg |= DI_POL_DRDY_DATA_POLARITY;
1182         __raw_writel(reg, DI_POL(disp));
1183
1184         __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1185
1186         return 0;
1187 }
1188
1189 /*
1190  * This function sets the foreground and background plane global alpha blending
1191  * modes. This function also sets the DP graphic plane according to the
1192  * parameter of IPUv3 DP channel.
1193  *
1194  * @param       channel         IPUv3 DP channel
1195  *
1196  * @param       enable          Boolean to enable or disable global alpha
1197  *                              blending. If disabled, local blending is used.
1198  *
1199  * @param       alpha           Global alpha value.
1200  *
1201  * @return      Returns 0 on success or negative error code on fail
1202  */
1203 int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1204                                   uint8_t alpha)
1205 {
1206         int ret;
1207         uint32_t reg;
1208
1209         unsigned char bg_chan;
1210
1211         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1212                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1213                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1214                 return -EINVAL;
1215
1216         if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1217             channel == MEM_BG_ASYNC1)
1218                 bg_chan = 1;
1219         else
1220                 bg_chan = 0;
1221
1222         ret = clk_enable(g_ipu_clk);
1223         if (ret)
1224                 return ret;
1225
1226         if (bg_chan) {
1227                 reg = __raw_readl(DP_COM_CONF());
1228                 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1229         } else {
1230                 reg = __raw_readl(DP_COM_CONF());
1231                 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1232         }
1233
1234         if (enable) {
1235                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1236                 __raw_writel(reg | ((uint32_t) alpha << 24),
1237                              DP_GRAPH_WIND_CTRL());
1238
1239                 reg = __raw_readl(DP_COM_CONF());
1240                 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1241         } else {
1242                 reg = __raw_readl(DP_COM_CONF());
1243                 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1244         }
1245
1246         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1247         __raw_writel(reg, IPU_SRM_PRI2);
1248
1249         clk_disable(g_ipu_clk);
1250
1251         return 0;
1252 }
1253
1254 /*
1255  * This function sets the transparent color key for SDC graphic plane.
1256  *
1257  * @param       channel         Input parameter for the logical channel ID.
1258  *
1259  * @param       enable          Boolean to enable or disable color key
1260  *
1261  * @param       colorKey        24-bit RGB color for transparent color key.
1262  *
1263  * @return      Returns 0 on success or negative error code on fail
1264  */
1265 int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1266                                uint32_t color_key)
1267 {
1268         int ret;
1269         uint32_t reg;
1270         int y, u, v;
1271         int red, green, blue;
1272
1273         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1274                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1275                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1276                 return -EINVAL;
1277
1278         ret = clk_enable(g_ipu_clk);
1279         if (ret)
1280                 return ret;
1281
1282         color_key_4rgb = 1;
1283         /* Transform color key from rgb to yuv if CSC is enabled */
1284         if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1285                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1286                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1287                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1288
1289                 debug("color key 0x%x need change to yuv fmt\n", color_key);
1290
1291                 red = (color_key >> 16) & 0xFF;
1292                 green = (color_key >> 8) & 0xFF;
1293                 blue = color_key & 0xFF;
1294
1295                 y = rgb_to_yuv(0, red, green, blue);
1296                 u = rgb_to_yuv(1, red, green, blue);
1297                 v = rgb_to_yuv(2, red, green, blue);
1298                 color_key = (y << 16) | (u << 8) | v;
1299
1300                 color_key_4rgb = 0;
1301
1302                 debug("color key change to yuv fmt 0x%x\n", color_key);
1303         }
1304
1305         if (enable) {
1306                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1307                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1308
1309                 reg = __raw_readl(DP_COM_CONF());
1310                 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1311         } else {
1312                 reg = __raw_readl(DP_COM_CONF());
1313                 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1314         }
1315
1316         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1317         __raw_writel(reg, IPU_SRM_PRI2);
1318
1319         clk_disable(g_ipu_clk);
1320
1321         return 0;
1322 }