include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * B4860 QDS board configuration file
  12  */
  13 #define CONFIG_B4860QDS
  14 #define CONFIG_PHYS_64BIT
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #define CONFIG_SYS_NO_FLASH
  28 #endif
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE
  32 #define CONFIG_E500                     /* BOOKE e500 family */
  33 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  34 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  35 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  36 #define CONFIG_MP                       /* support multiple processors */
  37
  38 #ifndef CONFIG_SYS_TEXT_BASE
  39 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  40 #endif
  41
  42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  44 #endif
  45
  46 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  47 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  48 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  49 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  50 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  51 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  52 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  53
  54 #ifndef CONFIG_PPC_B4420
  55 #define CONFIG_SYS_SRIO
  56 #define CONFIG_SRIO1                    /* SRIO port 1 */
  57 #define CONFIG_SRIO2                    /* SRIO port 2 */
  58 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  59 #endif
  60
  61 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  62
  63 /* I2C bus multiplexer */
  64 #define I2C_MUX_PCA_ADDR                0x77
  65
  66 /* VSC Crossbar switches */
  67 #define CONFIG_VSC_CROSSBAR
  68 #define I2C_CH_DEFAULT                  0x8
  69 #define I2C_CH_VSC3316                  0xc
  70 #define I2C_CH_VSC3308                  0xd
  71
  72 #define VSC3316_TX_ADDRESS              0x70
  73 #define VSC3316_RX_ADDRESS              0x71
  74 #define VSC3308_TX_ADDRESS              0x02
  75 #define VSC3308_RX_ADDRESS              0x03
  76
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 #ifdef CONFIG_SYS_NO_FLASH
  80 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  81 #define CONFIG_ENV_IS_NOWHERE
  82 #endif
  83 #else
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_CFI
  86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  87 #endif
  88
  89 #if defined(CONFIG_SPIFLASH)
  90 #define CONFIG_SYS_EXTRA_ENV_RELOC
  91 #define CONFIG_ENV_IS_IN_SPI_FLASH
  92 #define CONFIG_ENV_SPI_BUS              0
  93 #define CONFIG_ENV_SPI_CS               0
  94 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  95 #define CONFIG_ENV_SPI_MODE             0
  96 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  97 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  98 #define CONFIG_ENV_SECT_SIZE            0x10000
  99 #elif defined(CONFIG_SDCARD)
 100 #define CONFIG_SYS_EXTRA_ENV_RELOC
 101 #define CONFIG_ENV_IS_IN_MMC
 102 #define CONFIG_SYS_MMC_ENV_DEV          0
 103 #define CONFIG_ENV_SIZE                 0x2000
 104 #define CONFIG_ENV_OFFSET               (512 * 1097)
 105 #elif defined(CONFIG_NAND)
 106 #define CONFIG_SYS_EXTRA_ENV_RELOC
 107 #define CONFIG_ENV_IS_IN_NAND
 108 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 109 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 110 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 111 #define CONFIG_ENV_IS_IN_REMOTE
 112 #define CONFIG_ENV_ADDR         0xffe20000
 113 #define CONFIG_ENV_SIZE         0x2000
 114 #elif defined(CONFIG_ENV_IS_NOWHERE)
 115 #define CONFIG_ENV_SIZE         0x2000
 116 #else
 117 #define CONFIG_ENV_IS_IN_FLASH
 118 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 119 #define CONFIG_ENV_SIZE         0x2000
 120 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 121 #endif
 122
 123 #ifndef __ASSEMBLY__
 124 unsigned long get_board_sys_clk(void);
 125 unsigned long get_board_ddr_clk(void);
 126 #endif
 127 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 128 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 129
 130 /*
 131  * These can be toggled for performance analysis, otherwise use default.
 132  */
 133 #define CONFIG_SYS_CACHE_STASHING
 134 #define CONFIG_BTB                      /* toggle branch predition */
 135 #define CONFIG_DDR_ECC
 136 #ifdef CONFIG_DDR_ECC
 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 138 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 139 #endif
 140
 141 #define CONFIG_ENABLE_36BIT_PHYS
 142
 143 #ifdef CONFIG_PHYS_64BIT
 144 #define CONFIG_ADDR_MAP
 145 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 146 #endif
 147
 148 #if 0
 149 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 150 #endif
 151 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 152 #define CONFIG_SYS_MEMTEST_END          0x00400000
 153 #define CONFIG_SYS_ALT_MEMTEST
 154 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 155
 156 /*
 157  *  Config the L3 Cache as L3 SRAM
 158  */
 159 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 160
 161 #ifdef CONFIG_PHYS_64BIT
 162 #define CONFIG_SYS_DCSRBAR              0xf0000000
 163 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 164 #endif
 165
 166 /* EEPROM */
 167 #define CONFIG_SYS_I2C_EEPROM_NXID
 168 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 169 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 173
 174 /*
 175  * DDR Setup
 176  */
 177 #define CONFIG_VERY_BIG_RAM
 178 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 179 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 180
 181 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 182 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 183 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 184
 185 #define CONFIG_DDR_SPD
 186 #define CONFIG_SYS_DDR_RAW_TIMING
 187 #define CONFIG_FSL_DDR3
 188 #define CONFIG_FSL_DDR_INTERACTIVE
 189
 190 #define CONFIG_SYS_SPD_BUS_NUM  0
 191 #define SPD_EEPROM_ADDRESS1     0x51
 192 #define SPD_EEPROM_ADDRESS2     0x53
 193
 194 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 195 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 196
 197 /*
 198  * IFC Definitions
 199  */
 200 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 201 #ifdef CONFIG_PHYS_64BIT
 202 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 203 #else
 204 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 205 #endif
 206
 207 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 209                                 + 0x8000000) | \
 210                                 CSPR_PORT_SIZE_16 | \
 211                                 CSPR_MSEL_NOR | \
 212                                 CSPR_V)
 213 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 214 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 215                                 CSPR_PORT_SIZE_16 | \
 216                                 CSPR_MSEL_NOR | \
 217                                 CSPR_V)
 218 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 219 /* NOR Flash Timing Params */
 220 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 221 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 222                                 FTIM0_NOR_TEADC(0x04) | \
 223                                 FTIM0_NOR_TEAHC(0x20))
 224 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 225                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 226                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 227 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 228                                 FTIM2_NOR_TCH(0x0E) | \
 229                                 FTIM2_NOR_TWPH(0x0E) | \
 230                                 FTIM2_NOR_TWP(0x1c))
 231 #define CONFIG_SYS_NOR_FTIM3    0x0
 232
 233 #define CONFIG_SYS_FLASH_QUIET_TEST
 234 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 235
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 237 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 238 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 239 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 240
 241 #define CONFIG_SYS_FLASH_EMPTY_INFO
 242 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 243                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 244
 245 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 246 #define CONFIG_FSL_QIXIS_V2
 247 #define QIXIS_BASE              0xffdf0000
 248 #ifdef CONFIG_PHYS_64BIT
 249 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 250 #else
 251 #define QIXIS_BASE_PHYS         QIXIS_BASE
 252 #endif
 253 #define QIXIS_LBMAP_SWITCH              0x01
 254 #define QIXIS_LBMAP_MASK                0x0f
 255 #define QIXIS_LBMAP_SHIFT               0
 256 #define QIXIS_LBMAP_DFLTBANK            0x00
 257 #define QIXIS_LBMAP_ALTBANK             0x02
 258 #define QIXIS_RST_CTL_RESET             0x31
 259 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 260 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 261 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 262
 263 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 264 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 265                                 | CSPR_PORT_SIZE_8 \
 266                                 | CSPR_MSEL_GPCM \
 267                                 | CSPR_V)
 268 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 269 #define CONFIG_SYS_CSOR3        0x0
 270 /* QIXIS Timing parameters for IFC CS3 */
 271 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 272                                         FTIM0_GPCM_TEADC(0x0e) | \
 273                                         FTIM0_GPCM_TEAHC(0x0e))
 274 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 275                                         FTIM1_GPCM_TRAD(0x1f))
 276 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 277                                         FTIM2_GPCM_TCH(0x0) | \
 278                                         FTIM2_GPCM_TWP(0x1f))
 279 #define CONFIG_SYS_CS3_FTIM3            0x0
 280
 281 /* NAND Flash on IFC */
 282 #define CONFIG_NAND_FSL_IFC
 283 #define CONFIG_SYS_NAND_BASE            0xff800000
 284 #ifdef CONFIG_PHYS_64BIT
 285 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 286 #else
 287 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 288 #endif
 289
 290 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 291 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 292                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 293                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 294                                 | CSPR_V)
 295 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 296
 297 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 298                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 299                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 300                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 301                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 302                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 303                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 304
 305 #define CONFIG_SYS_NAND_ONFI_DETECTION
 306
 307 /* ONFI NAND Flash mode0 Timing Params */
 308 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 309                                         FTIM0_NAND_TWP(0x18)   | \
 310                                         FTIM0_NAND_TWCHT(0x07) | \
 311                                         FTIM0_NAND_TWH(0x0a))
 312 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 313                                         FTIM1_NAND_TWBE(0x39)  | \
 314                                         FTIM1_NAND_TRR(0x0e)   | \
 315                                         FTIM1_NAND_TRP(0x18))
 316 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 317                                         FTIM2_NAND_TREH(0x0a) | \
 318                                         FTIM2_NAND_TWHRE(0x1e))
 319 #define CONFIG_SYS_NAND_FTIM3           0x0
 320
 321 #define CONFIG_SYS_NAND_DDR_LAW         11
 322
 323 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 324 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 325 #define CONFIG_MTD_NAND_VERIFY_WRITE
 326 #define CONFIG_CMD_NAND
 327
 328 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 329
 330 #if defined(CONFIG_NAND)
 331 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 332 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 333 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 334 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 335 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 336 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 337 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 338 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 339 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 340 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 341 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 342 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 343 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 344 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 345 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 346 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 347 #else
 348 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 349 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 350 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 351 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 352 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 353 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 354 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 355 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 356 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 357 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 358 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 359 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 360 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 361 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 362 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 363 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 364 #endif
 365 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 366 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 367 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 368 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 369 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 370 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 371 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 372 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 373
 374 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 375
 376 #if defined(CONFIG_RAMBOOT_PBL)
 377 #define CONFIG_SYS_RAMBOOT
 378 #endif
 379
 380 #define CONFIG_BOARD_EARLY_INIT_R
 381 #define CONFIG_MISC_INIT_R
 382
 383 #define CONFIG_HWCONFIG
 384
 385 /* define to use L1 as initial stack */
 386 #define CONFIG_L1_INIT_RAM
 387 #define CONFIG_SYS_INIT_RAM_LOCK
 388 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 389 #ifdef CONFIG_PHYS_64BIT
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 392 /* The assembler doesn't like typecast */
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 394         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 395           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 396 #else
 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe0ec000 /* Initial L1 address */
 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 400 #endif
 401 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 402
 403 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 404                                         GENERATED_GBL_DATA_SIZE)
 405 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 406
 407 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 408 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 409
 410 /* Serial Port - controlled on board with jumper J8
 411  * open - index 2
 412  * shorted - index 1
 413  */
 414 #define CONFIG_CONS_INDEX       1
 415 #define CONFIG_SYS_NS16550
 416 #define CONFIG_SYS_NS16550_SERIAL
 417 #define CONFIG_SYS_NS16550_REG_SIZE     1
 418 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 419
 420 #define CONFIG_SYS_BAUDRATE_TABLE       \
 421         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 422
 423 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 424 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 425 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 426 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 427 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
 428 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 429
 430
 431 /* Use the HUSH parser */
 432 #define CONFIG_SYS_HUSH_PARSER
 433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 434
 435 /* pass open firmware flat tree */
 436 #define CONFIG_OF_LIBFDT
 437 #define CONFIG_OF_BOARD_SETUP
 438 #define CONFIG_OF_STDOUT_VIA_ALIAS
 439
 440 /* new uImage format support */
 441 #define CONFIG_FIT
 442 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 443
 444 /* I2C */
 445 #define CONFIG_SYS_I2C
 446 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 447 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 448 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 449 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 450 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 451 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 452 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 453
 454 /*
 455  * RTC configuration
 456  */
 457 #define RTC
 458 #define CONFIG_RTC_DS3231               1
 459 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 460
 461 /*
 462  * RapidIO
 463  */
 464 #ifdef CONFIG_SYS_SRIO
 465 #ifdef CONFIG_SRIO1
 466 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 467 #ifdef CONFIG_PHYS_64BIT
 468 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 469 #else
 470 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 471 #endif
 472 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 473 #endif
 474
 475 #ifdef CONFIG_SRIO2
 476 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 477 #ifdef CONFIG_PHYS_64BIT
 478 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 479 #else
 480 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 481 #endif
 482 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 483 #endif
 484 #endif
 485
 486 /*
 487  * for slave u-boot IMAGE instored in master memory space,
 488  * PHYS must be aligned based on the SIZE
 489  */
 490 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 491 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 492 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000        /* 512K */
 493 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 494 /*
 495  * for slave UCODE and ENV instored in master memory space,
 496  * PHYS must be aligned based on the SIZE
 497  */
 498 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 499 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 500 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 501
 502 /* slave core release by master*/
 503 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 504 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 505
 506 /*
 507  * SRIO_PCIE_BOOT - SLAVE
 508  */
 509 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 510 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 511 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 512                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 513 #endif
 514
 515 /*
 516  * eSPI - Enhanced SPI
 517  */
 518 #define CONFIG_FSL_ESPI
 519 #define CONFIG_SPI_FLASH
 520 #define CONFIG_SPI_FLASH_SST
 521 #define CONFIG_CMD_SF
 522 #define CONFIG_SF_DEFAULT_SPEED         10000000
 523 #define CONFIG_SF_DEFAULT_MODE          0
 524
 525 /*
 526  * MAPLE
 527  */
 528 #ifdef CONFIG_PHYS_64BIT
 529 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 530 #else
 531 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 532 #endif
 533
 534 /*
 535  * General PCI
 536  * Memory space is mapped 1-1, but I/O space must start from 0.
 537  */
 538
 539 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 540 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 541 #ifdef CONFIG_PHYS_64BIT
 542 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 543 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 544 #else
 545 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 546 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 547 #endif
 548 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 549 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 550 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 551 #ifdef CONFIG_PHYS_64BIT
 552 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 553 #else
 554 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 555 #endif
 556 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 557
 558 /* Qman/Bman */
 559 #ifndef CONFIG_NOBQFMAN
 560 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 561 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 562 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 563 #ifdef CONFIG_PHYS_64BIT
 564 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 565 #else
 566 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 567 #endif
 568 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 569 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 570 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 571 #ifdef CONFIG_PHYS_64BIT
 572 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 573 #else
 574 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 575 #endif
 576 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 577
 578 #define CONFIG_SYS_DPAA_FMAN
 579
 580 /* Default address of microcode for the Linux Fman driver */
 581 #if defined(CONFIG_SPIFLASH)
 582 /*
 583  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 584  * env, so we got 0x110000.
 585  */
 586 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 587 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 588 #elif defined(CONFIG_SDCARD)
 589 /*
 590  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 591  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 592  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 593  */
 594 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 595 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 596 #elif defined(CONFIG_NAND)
 597 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 598 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 599 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 600 /*
 601  * Slave has no ucode locally, it can fetch this from remote. When implementing
 602  * in two corenet boards, slave's ucode could be stored in master's memory
 603  * space, the address can be mapped from slave TLB->slave LAW->
 604  * slave SRIO or PCIE outbound window->master inbound window->
 605  * master LAW->the ucode address in master's memory space.
 606  */
 607 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 608 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 609 #else
 610 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 611 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEFF40000
 612 #endif
 613 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 614 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 615 #endif /* CONFIG_NOBQFMAN */
 616
 617 #ifdef CONFIG_SYS_DPAA_FMAN
 618 #define CONFIG_FMAN_ENET
 619 #define CONFIG_PHYLIB_10G
 620 #define CONFIG_PHY_VITESSE
 621 #define CONFIG_PHY_TERANETICS
 622 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 623 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 624 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 625 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 626 #endif
 627
 628 #ifdef CONFIG_PCI
 629 #define CONFIG_PCI_INDIRECT_BRIDGE
 630 #define CONFIG_NET_MULTI
 631 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 632 #define CONFIG_E1000
 633
 634 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 635 #define CONFIG_DOS_PARTITION
 636 #endif  /* CONFIG_PCI */
 637
 638 #ifdef CONFIG_FMAN_ENET
 639 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x10
 640 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR  0x11
 641
 642 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 643 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 644 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 645
 646
 647 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 648 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 649 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 650 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 651
 652 #define CONFIG_MII              /* MII PHY management */
 653 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 654 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 655 #endif
 656
 657 /*
 658  * Environment
 659  */
 660 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 661 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 662
 663 /*
 664  * Command line configuration.
 665  */
 666 #include <config_cmd_default.h>
 667
 668 #define CONFIG_CMD_DATE
 669 #define CONFIG_CMD_DHCP
 670 #define CONFIG_CMD_EEPROM
 671 #define CONFIG_CMD_ELF
 672 #define CONFIG_CMD_ERRATA
 673 #define CONFIG_CMD_GREPENV
 674 #define CONFIG_CMD_IRQ
 675 #define CONFIG_CMD_I2C
 676 #define CONFIG_CMD_MII
 677 #define CONFIG_CMD_PING
 678 #define CONFIG_CMD_REGINFO
 679 #define CONFIG_CMD_SETEXPR
 680
 681 #ifdef CONFIG_PCI
 682 #define CONFIG_CMD_PCI
 683 #define CONFIG_CMD_NET
 684 #endif
 685
 686 /*
 687 * USB
 688 */
 689 #define CONFIG_HAS_FSL_DR_USB
 690
 691 #ifdef CONFIG_HAS_FSL_DR_USB
 692 #define CONFIG_USB_EHCI
 693
 694 #ifdef CONFIG_USB_EHCI
 695 #define CONFIG_CMD_USB
 696 #define CONFIG_USB_STORAGE
 697 #define CONFIG_USB_EHCI_FSL
 698 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 699 #define CONFIG_CMD_EXT2
 700 #endif
 701 #endif
 702
 703 /*
 704  * Miscellaneous configurable options
 705  */
 706 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 707 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 708 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 709 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 710 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 711 #ifdef CONFIG_CMD_KGDB
 712 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 713 #else
 714 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 715 #endif
 716 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 717 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 718 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 719 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks*/
 720
 721 /*
 722  * For booting Linux, the board info and command line data
 723  * have to be in the first 64 MB of memory, since this is
 724  * the maximum mapped by the Linux kernel during initialization.
 725  */
 726 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 727 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 728
 729 #ifdef CONFIG_CMD_KGDB
 730 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 731 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 732 #endif
 733
 734 /*
 735  * Environment Configuration
 736  */
 737 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 738 #define CONFIG_BOOTFILE         "uImage"
 739 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 740
 741 /* default location for tftp and bootm */
 742 #define CONFIG_LOADADDR         1000000
 743
 744 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 745
 746 #define CONFIG_BAUDRATE 115200
 747
 748 #define __USB_PHY_TYPE  ulpi
 749
 750 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 751         "hwconfig=fsl_ddr:ctlr_intlv=null,"             \
 752         "bank_intlv=cs0_cs1;"                                   \
 753         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 754         "netdev=eth0\0"                                         \
 755         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 756         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 757         "tftpflash=tftpboot $loadaddr $uboot && "               \
 758         "protect off $ubootaddr +$filesize && "                 \
 759         "erase $ubootaddr +$filesize && "                       \
 760         "cp.b $loadaddr $ubootaddr $filesize && "               \
 761         "protect on $ubootaddr +$filesize && "                  \
 762         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 763         "consoledev=ttyS0\0"                                    \
 764         "ramdiskaddr=2000000\0"                                 \
 765         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 766         "fdtaddr=c00000\0"                                      \
 767         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 768         "bdev=sda3\0"                                           \
 769         "c=ffe\0"
 770
 771 /* For emulation this causes u-boot to jump to the start of the proof point
 772    app code automatically */
 773 #define CONFIG_PROOF_POINTS                     \
 774  "setenv bootargs root=/dev/$bdev rw "          \
 775  "console=$consoledev,$baudrate $othbootargs;"  \
 776  "cpu 1 release 0x29000000 - - -;"              \
 777  "cpu 2 release 0x29000000 - - -;"              \
 778  "cpu 3 release 0x29000000 - - -;"              \
 779  "cpu 4 release 0x29000000 - - -;"              \
 780  "cpu 5 release 0x29000000 - - -;"              \
 781  "cpu 6 release 0x29000000 - - -;"              \
 782  "cpu 7 release 0x29000000 - - -;"              \
 783  "go 0x29000000"
 784
 785 #define CONFIG_HVBOOT   \
 786  "setenv bootargs config-addr=0x60000000; "     \
 787  "bootm 0x01000000 - 0x00f00000"
 788
 789 #define CONFIG_ALU                              \
 790  "setenv bootargs root=/dev/$bdev rw "          \
 791  "console=$consoledev,$baudrate $othbootargs;"  \
 792  "cpu 1 release 0x01000000 - - -;"              \
 793  "cpu 2 release 0x01000000 - - -;"              \
 794  "cpu 3 release 0x01000000 - - -;"              \
 795  "cpu 4 release 0x01000000 - - -;"              \
 796  "cpu 5 release 0x01000000 - - -;"              \
 797  "cpu 6 release 0x01000000 - - -;"              \
 798  "cpu 7 release 0x01000000 - - -;"              \
 799  "go 0x01000000"
 800
 801 #define CONFIG_LINUX                            \
 802  "setenv bootargs root=/dev/ram rw "            \
 803  "console=$consoledev,$baudrate $othbootargs;"  \
 804  "setenv ramdiskaddr 0x02000000;"               \
 805  "setenv fdtaddr 0x00c00000;"                   \
 806  "setenv loadaddr 0x1000000;"                   \
 807  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 808
 809 #define CONFIG_HDBOOT                                   \
 810         "setenv bootargs root=/dev/$bdev rw "           \
 811         "console=$consoledev,$baudrate $othbootargs;"   \
 812         "tftp $loadaddr $bootfile;"                     \
 813         "tftp $fdtaddr $fdtfile;"                       \
 814         "bootm $loadaddr - $fdtaddr"
 815
 816 #define CONFIG_NFSBOOTCOMMAND                   \
 817         "setenv bootargs root=/dev/nfs rw "     \
 818         "nfsroot=$serverip:$rootpath "          \
 819         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 820         "console=$consoledev,$baudrate $othbootargs;"   \
 821         "tftp $loadaddr $bootfile;"             \
 822         "tftp $fdtaddr $fdtfile;"               \
 823         "bootm $loadaddr - $fdtaddr"
 824
 825 #define CONFIG_RAMBOOTCOMMAND                           \
 826         "setenv bootargs root=/dev/ram rw "             \
 827         "console=$consoledev,$baudrate $othbootargs;"   \
 828         "tftp $ramdiskaddr $ramdiskfile;"               \
 829         "tftp $loadaddr $bootfile;"                     \
 830         "tftp $fdtaddr $fdtfile;"                       \
 831         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 832
 833 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 834
 835 #ifdef CONFIG_SECURE_BOOT
 836 #include <asm/fsl_secure_boot.h>
 837 #endif
 838
 839 #endif  /* __CONFIG_H */