include/configs/MPC8360ERDK.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1 /* E300 family */
  24 #define CONFIG_QE               1 /* Has QE */
  25 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  26 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  27 #define CONFIG_MPC8360ERDK      1 /* MPC8360ERDK board specific */
  28
  29 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  30
  31 /*
  32  * System Clock Setup
  33  */
  34 #ifdef CONFIG_CLKIN_33MHZ
  35 #define CONFIG_83XX_CLKIN               33333333
  36 #define CONFIG_SYS_CLK_FREQ             33333333
  37 #define CONFIG_PCI_33M                          1
  38 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_10X1
  39 #else
  40 #define CONFIG_83XX_CLKIN               66000000
  41 #define CONFIG_SYS_CLK_FREQ             66000000
  42 #define CONFIG_PCI_66M                          1
  43 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_5X1
  44 #endif /* CONFIG_CLKIN_33MHZ */
  45
  46 /*
  47  * Hardware Reset Configuration Word
  48  */
  49 #define CONFIG_SYS_HRCW_LOW (\
  50         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  51         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  52         HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
  53         HRCWL_CORE_TO_CSB_2X1 |\
  54         HRCWL_CE_TO_PLL_1X15)
  55
  56 #define CONFIG_SYS_HRCW_HIGH (\
  57         HRCWH_PCI_HOST |\
  58         HRCWH_PCI1_ARBITER_ENABLE |\
  59         HRCWH_PCICKDRV_ENABLE |\
  60         HRCWH_CORE_ENABLE |\
  61         HRCWH_FROM_0X00000100 |\
  62         HRCWH_BOOTSEQ_DISABLE |\
  63         HRCWH_SW_WATCHDOG_DISABLE |\
  64         HRCWH_ROM_LOC_LOCAL_16BIT |\
  65         HRCWH_SECONDARY_DDR_DISABLE |\
  66         HRCWH_BIG_ENDIAN |\
  67         HRCWH_LALE_EARLY)
  68
  69 /*
  70  * System IO Config
  71  */
  72 #define CONFIG_SYS_SICRH                0x00000000
  73 #define CONFIG_SYS_SICRL                0x40000000
  74
  75 #define CONFIG_BOARD_EARLY_INIT_R
  76
  77 /*
  78  * IMMR new address
  79  */
  80 #define CONFIG_SYS_IMMR         0xE0000000
  81
  82 /*
  83  * DDR Setup
  84  */
  85 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  87 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  88 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  89                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  90
  91 #define CONFIG_SYS_83XX_DDR_USES_CS0
  92
  93 #define CONFIG_DDR_ECC          /* support DDR ECC function */
  94 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
  95
  96 /*
  97  * DDRCDR - DDR Control Driver Register
  98  */
  99 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 100
 101 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 102
 103 /*
 104  * Manually set up DDR parameters
 105  */
 106 #define CONFIG_DDR_II
 107 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 108 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
 109 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 110                                         | CSCONFIG_ROW_BIT_13 \
 111                                         | CSCONFIG_COL_BIT_10 \
 112                                         | CSCONFIG_ODT_WR_ACS)
 113 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 \
 114                                         | SDRAM_CFG_ECC_EN)
 115 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000
 116 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 117 #define CONFIG_SYS_DDR_INTERVAL         ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
 118                                         | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 119 #define CONFIG_SYS_DDR_MODE             0x47800432
 120 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 121
 122 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 123                                  (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 124                                  (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 125                                  (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 126                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 127                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 128                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 129                                  (0 << TIMING_CFG0_RWT_SHIFT))
 130
 131 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
 132                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 133                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 134                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 135                                  (10 << TIMING_CFG1_REFREC_SHIFT) | \
 136                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 137                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 138                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 139
 140 #define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 141                                  (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 142                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 143                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 144                                  (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 145                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 146                                  (0 << TIMING_CFG2_CPO_SHIFT))
 147
 148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 149
 150 /*
 151  * Memory test
 152  */
 153 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 154 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 155 #define CONFIG_SYS_MEMTEST_END          0x00100000
 156
 157 /*
 158  * The reserved memory
 159  */
 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 161 #define CONFIG_SYS_FLASH_BASE           0xFF800000 /* FLASH base address */
 162
 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 164 #define CONFIG_SYS_RAMBOOT
 165 #else
 166 #undef  CONFIG_SYS_RAMBOOT
 167 #endif
 168
 169 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 170 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024) /* Reserved for malloc */
 171
 172 /*
 173  * Initial RAM Base Address Setup
 174  */
 175 #define CONFIG_SYS_INIT_RAM_LOCK        1
 176 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 177 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 178 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 179                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 180
 181 /*
 182  * Local Bus Configuration & Clock Setup
 183  */
 184 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 185 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 186 #define CONFIG_SYS_LBC_LBCR     0x00000000
 187
 188 /*
 189  * FLASH on the Local Bus
 190  */
 191 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 192 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 193 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 194 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use intel Flash protection. */
 195
 196                                         /* Window base at flash base */
 197 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 198 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 199
 200 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 201                                 | (2 << BR_PS_SHIFT) /* 16 bit port */ \
 202                                 | BR_V) /* valid */
 203 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 204                                 | OR_UPM_XAM \
 205                                 | OR_GPCM_CSNT \
 206                                 | OR_GPCM_ACS_DIV2 \
 207                                 | OR_GPCM_XACS \
 208                                 | OR_GPCM_SCY_15 \
 209                                 | OR_GPCM_TRLX \
 210                                 | OR_GPCM_EHTR \
 211                                 | OR_GPCM_EAD)
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 215
 216 #undef  CONFIG_SYS_FLASH_CHECKSUM
 217
 218 /*
 219  * NAND flash on the local bus
 220  */
 221 #define CONFIG_SYS_NAND_BASE            0x60000000
 222 #define CONFIG_CMD_NAND         1
 223 #define CONFIG_NAND_FSL_UPM     1
 224 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 225 #define CONFIG_MTD_NAND_VERIFY_WRITE
 226
 227 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 228 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001b /* Access window size 4K */
 229
 230 /* Port size 8 bit, UPMA */
 231 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_NAND_BASE | 0x00000881)
 232 #define CONFIG_SYS_OR1_PRELIM           0xfc000001
 233
 234 /*
 235  * Fujitsu MB86277 (MINT) graphics controller
 236  */
 237 #define CONFIG_SYS_VIDEO_BASE           0x70000000
 238
 239 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VIDEO_BASE
 240 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* Access window size 64MB */
 241
 242 /* Port size 32 bit, UPMB */
 243                                 /* PS=11, UPMB */
 244 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
 245 #define CONFIG_SYS_OR2_PRELIM   0xfc000001 /* (64MB, EAD=1) */
 246
 247 /*
 248  * Serial Port
 249  */
 250 #define CONFIG_CONS_INDEX       1
 251 #define CONFIG_SYS_NS16550
 252 #define CONFIG_SYS_NS16550_SERIAL
 253 #define CONFIG_SYS_NS16550_REG_SIZE     1
 254 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 255
 256 #define CONFIG_SYS_BAUDRATE_TABLE  \
 257                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 258
 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 261
 262 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 263 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 264 /* Use the HUSH parser */
 265 #define CONFIG_SYS_HUSH_PARSER
 266 #ifdef  CONFIG_SYS_HUSH_PARSER
 267 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 268 #endif
 269
 270 /* Pass open firmware flat tree */
 271 #define CONFIG_OF_LIBFDT        1
 272 #define CONFIG_OF_BOARD_SETUP   1
 273 #define CONFIG_OF_STDOUT_VIA_ALIAS
 274
 275 /* I2C */
 276 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 277 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 278 #define CONFIG_FSL_I2C
 279 #define CONFIG_I2C_MULTI_BUS
 280 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 281 #define CONFIG_SYS_I2C_SLAVE    0x7F
 282 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
 283 #define CONFIG_SYS_I2C_OFFSET   0x3000
 284 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 285
 286 /*
 287  * General PCI
 288  * Addresses are mapped 1-1.
 289  */
 290 #define CONFIG_PCI
 291
 292 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 293 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 294 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 295 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 296 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 297 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 298 #define CONFIG_SYS_PCI1_IO_BASE         0xE0300000
 299 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 300 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
 301
 302 #ifdef CONFIG_PCI
 303
 304 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 305
 306 #undef CONFIG_EEPRO100
 307 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 308 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 309
 310 #endif  /* CONFIG_PCI */
 311
 312 /*
 313  * QE UEC ethernet configuration
 314  */
 315 #define CONFIG_UEC_ETH
 316 #define CONFIG_ETHPRIME         "UEC0"
 317
 318 #define CONFIG_UEC_ETH1         /* GETH1 */
 319
 320 #ifdef CONFIG_UEC_ETH1
 321 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 322 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 323 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 324 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 325 #define CONFIG_SYS_UEC1_PHY_ADDR        2
 326 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RGMII_RXID
 327 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 328 #endif
 329
 330 #define CONFIG_UEC_ETH2         /* GETH2 */
 331
 332 #ifdef CONFIG_UEC_ETH2
 333 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 334 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 335 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 336 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 337 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 338 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RGMII_RXID
 339 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 340 #endif
 341
 342 /*
 343  * Environment
 344  */
 345
 346 #ifndef CONFIG_SYS_RAMBOOT
 347 #define CONFIG_ENV_IS_IN_FLASH  1
 348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 349 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 350 #define CONFIG_ENV_SIZE         0x20000
 351 #else /* CONFIG_SYS_RAMBOOT */
 352 #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 353 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 354 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 355 #define CONFIG_ENV_SIZE         0x2000
 356 #endif /* CONFIG_SYS_RAMBOOT */
 357
 358 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 359 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 360
 361 /*
 362  * BOOTP options
 363  */
 364 #define CONFIG_BOOTP_BOOTFILESIZE
 365 #define CONFIG_BOOTP_BOOTPATH
 366 #define CONFIG_BOOTP_GATEWAY
 367 #define CONFIG_BOOTP_HOSTNAME
 368
 369
 370 /*
 371  * Command line configuration.
 372  */
 373 #include <config_cmd_default.h>
 374
 375 #define CONFIG_CMD_PING
 376 #define CONFIG_CMD_I2C
 377 #define CONFIG_CMD_ASKENV
 378 #define CONFIG_CMD_DHCP
 379
 380 #if defined(CONFIG_PCI)
 381 #define CONFIG_CMD_PCI
 382 #endif
 383
 384 #if defined(CONFIG_SYS_RAMBOOT)
 385 #undef CONFIG_CMD_SAVEENV
 386 #undef CONFIG_CMD_LOADS
 387 #endif
 388
 389 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 390
 391 /*
 392  * Miscellaneous configurable options
 393  */
 394 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 395 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 396 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 397
 398 #if defined(CONFIG_CMD_KGDB)
 399         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 400 #else
 401         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 402 #endif
 403
 404                                 /* Print Buffer Size */
 405 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 406 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 407                                 /* Boot Argument Buffer Size */
 408 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 409 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 410
 411 /*
 412  * For booting Linux, the board info and command line data
 413  * have to be in the first 256 MB of memory, since this is
 414  * the maximum mapped by the Linux kernel during initialization.
 415  */
 416 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 417
 418 /*
 419  * Core HID Setup
 420  */
 421 #define CONFIG_SYS_HID0_INIT    0x000000000
 422 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 423                                  HID0_ENABLE_INSTRUCTION_CACHE)
 424 #define CONFIG_SYS_HID2         HID2_HBE
 425
 426 /*
 427  * MMU Setup
 428  */
 429
 430 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 431
 432 /* DDR: cache cacheable */
 433 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 434                                 | BATL_PP_10 \
 435                                 | BATL_MEMCOHERENCE)
 436 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 437                                 | BATU_BL_256M \
 438                                 | BATU_VS \
 439                                 | BATU_VP)
 440 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 441 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 442
 443 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 444 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 445                                 | BATL_PP_10 \
 446                                 | BATL_CACHEINHIBIT \
 447                                 | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 449                                 | BATU_BL_4M \
 450                                 | BATU_VS \
 451                                 | BATU_VP)
 452 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 453 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 454
 455 /* NAND: cache-inhibit and guarded */
 456 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_NAND_BASE \
 457                                 | BATL_PP_10 \
 458                                 | BATL_CACHEINHIBIT \
 459                                 | BATL_GUARDEDSTORAGE)
 460 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_NAND_BASE \
 461                                 | BATU_BL_64M \
 462                                 | BATU_VS \
 463                                 | BATU_VP)
 464 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 465 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 466
 467 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 468 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 469                                 | BATL_PP_10 \
 470                                 | BATL_MEMCOHERENCE)
 471 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 472                                 | BATU_BL_32M \
 473                                 | BATU_VS \
 474                                 | BATU_VP)
 475 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 476                                 | BATL_PP_10 \
 477                                 | BATL_CACHEINHIBIT \
 478                                 | BATL_GUARDEDSTORAGE)
 479 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 480
 481 /* Stack in dcache: cacheable, no memory coherence */
 482 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR \
 483                                 | BATL_PP_10)
 484 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 485                                 | BATU_BL_128K \
 486                                 | BATU_VS \
 487                                 | BATU_VP)
 488 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 489 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 490
 491 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_VIDEO_BASE \
 492                                 | BATL_PP_10 \
 493                                 | BATL_CACHEINHIBIT \
 494                                 | BATL_GUARDEDSTORAGE)
 495 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_VIDEO_BASE \
 496                                 | BATU_BL_64M \
 497                                 | BATU_VS \
 498                                 | BATU_VP)
 499 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 500 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 501
 502 #ifdef CONFIG_PCI
 503 /* PCI MEM space: cacheable */
 504 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 505                                 | BATL_PP_10 \
 506                                 | BATL_MEMCOHERENCE)
 507 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 508                                 | BATU_BL_256M \
 509                                 | BATU_VS \
 510                                 | BATU_VP)
 511 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 512 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 513 /* PCI MMIO space: cache-inhibit and guarded */
 514 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 515                                 | BATL_PP_10 \
 516                                 | BATL_CACHEINHIBIT \
 517                                 | BATL_GUARDEDSTORAGE)
 518 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 519                                 | BATU_BL_256M \
 520                                 | BATU_VS \
 521                                 | BATU_VP)
 522 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 523 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 524 #else /* CONFIG_PCI */
 525 #define CONFIG_SYS_IBAT6L       (0)
 526 #define CONFIG_SYS_IBAT6U       (0)
 527 #define CONFIG_SYS_IBAT7L       (0)
 528 #define CONFIG_SYS_IBAT7U       (0)
 529 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 530 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 531 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 532 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 533 #endif /* CONFIG_PCI */
 534
 535 #if defined(CONFIG_CMD_KGDB)
 536 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 537 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 538 #endif
 539
 540 /*
 541  * Environment Configuration
 542  */
 543 #define CONFIG_ENV_OVERWRITE
 544
 545 #if defined(CONFIG_UEC_ETH)
 546 #define CONFIG_HAS_ETH0
 547 #define CONFIG_HAS_ETH1
 548 #define CONFIG_HAS_ETH2
 549 #define CONFIG_HAS_ETH3
 550 #endif
 551
 552 #define CONFIG_BAUDRATE 115200
 553
 554 #define CONFIG_LOADADDR a00000
 555 #define CONFIG_HOSTNAME mpc8360erdk
 556 #define CONFIG_BOOTFILE "uImage"
 557
 558 #define CONFIG_ROOTPATH         "/nfsroot/"
 559
 560 #define CONFIG_BOOTDELAY 2      /* -1 disables auto-boot */
 561 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 562
 563 #define CONFIG_EXTRA_ENV_SETTINGS \
 564         "netdev=eth0\0"                                                 \
 565         "consoledev=ttyS0\0"                                            \
 566         "loadaddr=a00000\0"                                             \
 567         "fdtaddr=900000\0"                                              \
 568         "fdtfile=mpc836x_rdk.dtb\0"                                     \
 569         "fsfile=fs\0"                                                   \
 570         "ubootfile=u-boot.bin\0"                                        \
 571         "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
 572                                                         "-(rootfs)\0"   \
 573         "setbootargs=setenv bootargs console=$consoledev,$baudrate "    \
 574                 "$mtdparts panic=1\0"                                   \
 575         "adddhcpargs=setenv bootargs $bootargs ip=on\0"                 \
 576         "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"    \
 577                 "$gatewayip:$netmask:$hostname:$netdev:off "            \
 578                 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"        \
 579         "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "    \
 580                 "rootfstype=jffs2 rw\0"                                 \
 581         "tftp_get_uboot=tftp 100000 $ubootfile\0"                       \
 582         "tftp_get_kernel=tftp $loadaddr $bootfile\0"                    \
 583         "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"                         \
 584         "tftp_get_fs=tftp c00000 $fsfile\0"                             \
 585         "nand_erase_kernel=nand erase 0 400000\0"                       \
 586         "nand_erase_dtb=nand erase 400000 20000\0"                      \
 587         "nand_erase_fs=nand erase 420000 3be0000\0"                     \
 588         "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"       \
 589         "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"       \
 590         "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"      \
 591         "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"         \
 592         "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"         \
 593         "nor_reflash=protect off ff800000 ff87ffff ; "                  \
 594                 "erase ff800000 ff87ffff ; "                            \
 595                 "cp.b 100000 ff800000 $filesize\0"                      \
 596         "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "    \
 597                 "nand_write_kernel\0"                                   \
 598         "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
 599         "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
 600         "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "        \
 601                 "nand_reflash_fs\0"                                     \
 602         "boot_m=bootm $loadaddr - $fdtaddr\0"                           \
 603         "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
 604         "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
 605                 "boot_m\0"                                              \
 606         "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
 607                 "boot_m\0"                                              \
 608         ""
 609
 610 #define CONFIG_BOOTCOMMAND "run dhcpboot"
 611
 612 #endif /* __CONFIG_H */