2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8548cds board configuration file
26 * Please refer to doc/README.mpc85xxcds for more info.
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36 #define CONFIG_MPC8548 1 /* MPC8548 specific */
37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
39 #define CONFIG_PCI /* enable any pci type devices */
40 #define CONFIG_PCI1 /* PCI controller 1 */
41 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
47 #define CONFIG_TSEC_ENET /* tsec ethernet support */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
50 #define CONFIG_DDR_DLL /* possible DLL fix needed */
51 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53 #define CONFIG_DDR_ECC /* only for ECC DDR module */
54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
60 #define CONFIG_FSL_VIA
61 #define CONFIG_FSL_CDS_EEPROM
64 * When initializing flash, if we cannot find the manufacturer ID,
65 * assume this is the AMD flash associated with the CDS board.
66 * This allows booting from a promjet.
68 #define CONFIG_ASSUME_AMD_FLASH
70 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
73 extern unsigned long get_clock_freq(void);
75 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
78 * These can be toggled for performance analysis, otherwise use default.
80 #define CONFIG_L2_CACHE /* toggle L2 cache */
81 #define CONFIG_BTB /* toggle branch predition */
82 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
83 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
86 * Only possible on E500 Version 2 or newer cores.
88 #define CONFIG_ENABLE_36BIT_PHYS 1
90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
92 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
93 #define CFG_MEMTEST_END 0x00400000
96 * Base addresses -- Note these are effective addresses where the
97 * actual resources get mapped (not physical addresses)
99 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
100 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
101 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
102 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
104 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
105 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
106 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
111 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
112 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
114 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
117 * Make sure required options are set
119 #ifndef CONFIG_SPD_EEPROM
120 #error ("CONFIG_SPD_EEPROM is required")
123 #undef CONFIG_CLOCKS_IN_MHZ
126 * Local Bus Definitions
130 * FLASH on the Local Bus
131 * Two banks, 8M each, using the CFI driver.
132 * Boot from BR0/OR0 bank at 0xff00_0000
133 * Alternate BR1/OR1 bank at 0xff80_0000
136 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
137 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
138 * Port Size = 16 bits = BRx[19:20] = 10
139 * Use GPCM = BRx[24:26] = 000
140 * Valid = BRx[31] = 1
142 * 0 4 8 12 16 20 24 28
143 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
144 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
147 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
148 * Reserved ORx[17:18] = 11, confusion here?
150 * ACS = half cycle delay = ORx[21:22] = 11
151 * SCY = 6 = ORx[24:27] = 0110
152 * TRLX = use relaxed timing = ORx[29] = 1
153 * EAD = use external address latch delay = OR[31] = 1
155 * 0 4 8 12 16 20 24 28
156 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
159 #define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
160 #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
162 #define CFG_BR0_PRELIM 0xff801001
163 #define CFG_BR1_PRELIM 0xff001001
165 #define CFG_OR0_PRELIM 0xff806e65
166 #define CFG_OR1_PRELIM 0xff806e65
168 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
169 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
170 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
171 #undef CFG_FLASH_CHECKSUM
172 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
175 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
177 #define CFG_FLASH_CFI_DRIVER
178 #define CFG_FLASH_CFI
179 #define CFG_FLASH_EMPTY_INFO
183 * SDRAM on the Local Bus
185 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
186 #define CFG_LBC_CACHE_SIZE 64
187 #define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
188 #define CFG_LBC_NONCACHE_SIZE 64
190 #define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
191 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
194 * Base Register 2 and Option Register 2 configure SDRAM.
195 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
198 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
199 * port-size = 32-bits = BR2[19:20] = 11
200 * no parity checking = BR2[21:22] = 00
201 * SDRAM for MSEL = BR2[24:26] = 011
204 * 0 4 8 12 16 20 24 28
205 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
207 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
208 * FIXME: the top 17 bits of BR2.
211 #define CFG_BR2_PRELIM 0xf0001861
214 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
217 * 64MB mask for AM, OR2[0:7] = 1111 1100
218 * XAM, OR2[17:18] = 11
219 * 9 columns OR2[19-21] = 010
220 * 13 rows OR2[23-25] = 100
221 * EAD set for extra time OR[31] = 1
223 * 0 4 8 12 16 20 24 28
224 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
227 #define CFG_OR2_PRELIM 0xfc006901
229 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
230 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
231 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
232 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
237 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
238 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
239 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
240 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
241 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
242 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
243 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
244 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
245 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
246 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
248 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
249 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
250 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
251 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
252 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
253 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
254 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
255 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
258 * Common settings for all Local Bus SDRAM commands.
259 * At run time, either BSMA1516 (for CPU 1.1)
260 * or BSMA1617 (for CPU 1.0) (old)
263 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
264 | CFG_LBC_LSDMR_PRETOACT7 \
265 | CFG_LBC_LSDMR_ACTTORW7 \
266 | CFG_LBC_LSDMR_BL8 \
267 | CFG_LBC_LSDMR_WRC4 \
268 | CFG_LBC_LSDMR_CL3 \
269 | CFG_LBC_LSDMR_RFEN \
273 * The CADMUS registers are connected to CS3 on CDS.
274 * The new memory map places CADMUS at 0xf8000000.
277 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
278 * port-size = 8-bits = BR[19:20] = 01
279 * no parity checking = BR[21:22] = 00
280 * GPMC for MSEL = BR[24:26] = 000
283 * 0 4 8 12 16 20 24 28
284 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
287 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
288 * disable buffer ctrl OR[19] = 0
292 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
296 * EAD extra time OR[31] = 1
298 * 0 4 8 12 16 20 24 28
299 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
302 #define CONFIG_FSL_CADMUS
304 #define CADMUS_BASE_ADDR 0xf8000000
305 #define CFG_BR3_PRELIM 0xf8000801
306 #define CFG_OR3_PRELIM 0xfff00ff7
308 #define CONFIG_L1_INIT_RAM
309 #define CFG_INIT_RAM_LOCK 1
310 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
311 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
313 #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
315 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
316 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
317 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
319 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
320 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
323 #define CONFIG_CONS_INDEX 2
324 #undef CONFIG_SERIAL_SOFTWARE_FIFO
326 #define CFG_NS16550_SERIAL
327 #define CFG_NS16550_REG_SIZE 1
328 #define CFG_NS16550_CLK get_bus_freq(0)
330 #define CFG_BAUDRATE_TABLE \
331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
333 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
334 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
336 /* Use the HUSH parser */
337 #define CFG_HUSH_PARSER
338 #ifdef CFG_HUSH_PARSER
339 #define CFG_PROMPT_HUSH_PS2 "> "
342 /* pass open firmware flat tree */
343 #define CONFIG_OF_LIBFDT 1
344 #define CONFIG_OF_BOARD_SETUP 1
345 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
350 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
351 #define CONFIG_HARD_I2C /* I2C with hardware support*/
352 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
353 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
354 #define CFG_I2C_EEPROM_ADDR 0x57
355 #define CFG_I2C_SLAVE 0x7F
356 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
357 #define CFG_I2C_OFFSET 0x3000
361 * Memory space is mapped 1-1, but I/O space must start from 0.
363 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
365 #define CFG_PCI1_MEM_BASE 0x80000000
366 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
367 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
368 #define CFG_PCI1_IO_BASE 0x00000000
369 #define CFG_PCI1_IO_PHYS 0xe2000000
370 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
373 #define CFG_PCI2_MEM_BASE 0xa0000000
374 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
375 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
376 #define CFG_PCI2_IO_BASE 0x00000000
377 #define CFG_PCI2_IO_PHYS 0xe2800000
378 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
382 #define CFG_PCIE1_MEM_BASE 0xa0000000
383 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
384 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
385 #define CFG_PCIE1_IO_BASE 0x00000000
386 #define CFG_PCIE1_IO_PHYS 0xe3000000
387 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
394 #define CFG_RIO_MEM_BASE 0xC0000000
395 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
406 #if defined(CONFIG_PCI)
408 #define CONFIG_NET_MULTI
409 #define CONFIG_PCI_PNP /* do pci plug-and-play */
411 #undef CONFIG_EEPRO100
414 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
416 /* PCI view of System Memory */
417 #define CFG_PCI_MEMORY_BUS 0x00000000
418 #define CFG_PCI_MEMORY_PHYS 0x00000000
419 #define CFG_PCI_MEMORY_SIZE 0x80000000
421 #endif /* CONFIG_PCI */
424 #if defined(CONFIG_TSEC_ENET)
426 #ifndef CONFIG_NET_MULTI
427 #define CONFIG_NET_MULTI 1
430 #define CONFIG_MII 1 /* MII PHY management */
431 #define CONFIG_TSEC1 1
432 #define CONFIG_TSEC1_NAME "eTSEC0"
433 #define CONFIG_TSEC2 1
434 #define CONFIG_TSEC2_NAME "eTSEC1"
435 #define CONFIG_TSEC3 1
436 #define CONFIG_TSEC3_NAME "eTSEC2"
438 #define CONFIG_TSEC4_NAME "eTSEC3"
439 #undef CONFIG_MPC85XX_FEC
441 #define TSEC1_PHY_ADDR 0
442 #define TSEC2_PHY_ADDR 1
443 #define TSEC3_PHY_ADDR 2
444 #define TSEC4_PHY_ADDR 3
446 #define TSEC1_PHYIDX 0
447 #define TSEC2_PHYIDX 0
448 #define TSEC3_PHYIDX 0
449 #define TSEC4_PHYIDX 0
450 #define TSEC1_FLAGS TSEC_GIGABIT
451 #define TSEC2_FLAGS TSEC_GIGABIT
452 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
453 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
455 /* Options are: eTSEC[0-3] */
456 #define CONFIG_ETHPRIME "eTSEC0"
457 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
458 #endif /* CONFIG_TSEC_ENET */
463 #define CFG_ENV_IS_IN_FLASH 1
464 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
465 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
466 #define CFG_ENV_SIZE 0x2000
468 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
469 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
474 #define CONFIG_BOOTP_BOOTFILESIZE
475 #define CONFIG_BOOTP_BOOTPATH
476 #define CONFIG_BOOTP_GATEWAY
477 #define CONFIG_BOOTP_HOSTNAME
481 * Command line configuration.
483 #include <config_cmd_default.h>
485 #define CONFIG_CMD_PING
486 #define CONFIG_CMD_I2C
487 #define CONFIG_CMD_MII
488 #define CONFIG_CMD_ELF
490 #if defined(CONFIG_PCI)
491 #define CONFIG_CMD_PCI
495 #undef CONFIG_WATCHDOG /* watchdog disabled */
498 * Miscellaneous configurable options
500 #define CFG_LONGHELP /* undef to save memory */
501 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
502 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
503 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
504 #if defined(CONFIG_CMD_KGDB)
505 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
507 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
509 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
510 #define CFG_MAXARGS 16 /* max number of command args */
511 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
512 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
515 * For booting Linux, the board info and command line data
516 * have to be in the first 8 MB of memory, since this is
517 * the maximum mapped by the Linux kernel during initialization.
519 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
522 * Internal Definitions
526 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
527 #define BOOTFLAG_WARM 0x02 /* Software reboot */
529 #if defined(CONFIG_CMD_KGDB)
530 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
531 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
535 * Environment Configuration
538 /* The mac addresses for all ethernet interface */
539 #if defined(CONFIG_TSEC_ENET)
540 #define CONFIG_HAS_ETH0
541 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
542 #define CONFIG_HAS_ETH1
543 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
544 #define CONFIG_HAS_ETH2
545 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
546 #define CONFIG_HAS_ETH3
547 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
550 #define CONFIG_IPADDR 192.168.1.253
552 #define CONFIG_HOSTNAME unknown
553 #define CONFIG_ROOTPATH /nfsroot
554 #define CONFIG_BOOTFILE 8548cds/uImage.uboot
555 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
557 #define CONFIG_SERVERIP 192.168.1.1
558 #define CONFIG_GATEWAYIP 192.168.1.1
559 #define CONFIG_NETMASK 255.255.255.0
561 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
563 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
564 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
566 #define CONFIG_BAUDRATE 115200
568 #define CONFIG_EXTRA_ENV_SETTINGS \
570 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
571 "tftpflash=tftpboot $loadaddr $uboot; " \
572 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
573 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
574 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
575 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
576 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
577 "consoledev=ttyS1\0" \
578 "ramdiskaddr=2000000\0" \
579 "ramdiskfile=ramdisk.uboot\0" \
581 "fdtfile=mpc8548cds.dtb\0"
583 #define CONFIG_NFSBOOTCOMMAND \
584 "setenv bootargs root=/dev/nfs rw " \
585 "nfsroot=$serverip:$rootpath " \
586 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
587 "console=$consoledev,$baudrate $othbootargs;" \
588 "tftp $loadaddr $bootfile;" \
589 "tftp $fdtaddr $fdtfile;" \
590 "bootm $loadaddr - $fdtaddr"
593 #define CONFIG_RAMBOOTCOMMAND \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $ramdiskaddr $ramdiskfile;" \
597 "tftp $loadaddr $bootfile;" \
598 "tftp $fdtaddr $fdtfile;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
601 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
603 #endif /* __CONFIG_H */