26897c69aff0635216b25f86dc4bb6a38f78a108
[karo-tx-uboot.git] / include / configs / MVBLM7.h
1 /*
2  * Copyright (C) Matrix Vision GmbH 2008
3  *
4  * Matrix Vision mvBlueLYNX-M7 configuration file
5  * based on Freescale's MPC8349ITX.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 #include <version.h>
31
32 /*
33  * High Level Configuration Options
34  */
35 #define CONFIG_E300     1
36 #define CONFIG_MPC83xx  1
37 #define CONFIG_MPC834x  1
38 #define CONFIG_MPC8343  1
39
40 #define CONFIG_SYS_IMMR         0xE0000000
41
42 #define CONFIG_PCI
43 #define CONFIG_PCI_SKIP_HOST_BRIDGE
44 #define CONFIG_HARD_I2C
45 #define CONFIG_TSEC_ENET
46 #define CONFIG_MPC8XXX_SPI
47 #define CONFIG_HARD_SPI
48 #define MVBLM7_MMC_CS   0x04000000
49 #define CONFIG_MISC_INIT_R
50
51 /* I2C */
52 #define CONFIG_FSL_I2C
53 #define CONFIG_I2C_MULTI_BUS
54 #define CONFIG_SYS_I2C_OFFSET           0x3000
55 #define CONFIG_SYS_I2C2_OFFSET          0x3100
56
57 #define CONFIG_SYS_I2C_SPEED            100000
58 #define CONFIG_SYS_I2C_SLAVE            0x7F
59
60 /*
61  * DDR Setup
62  */
63 #undef  CONFIG_SPD_EEPROM
64
65 #define CONFIG_SYS_DDR_BASE             0x00000000
66 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
67 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_83XX_DDR_USES_CS0    1
69 #define CONFIG_SYS_MEMTEST_START        (60<<20)
70 #define CONFIG_SYS_MEMTEST_END          (70<<20)
71 #define CONFIG_VERY_BIG_RAM
72
73 #define CONFIG_SYS_DDRCDR               0x22000001
74 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
75
76 #define CONFIG_SYS_DDR_SIZE             512
77
78 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
79
80 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
81
82 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
83 #define CONFIG_SYS_DDR_TIMING_1         0x3837c322
84 #define CONFIG_SYS_DDR_TIMING_2         0x0f9848c6
85 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
86
87 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43080008
88 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
89 #define CONFIG_SYS_DDR_INTERVAL         0x02000100
90
91 #define CONFIG_SYS_DDR_MODE             0x04040242
92 #define CONFIG_SYS_DDR_MODE2            0x00800000
93
94 /* Flash */
95 #define CONFIG_SYS_FLASH_CFI
96 #define CONFIG_FLASH_CFI_DRIVER
97 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
98
99 #define CONFIG_SYS_FLASH_BASE           0xFF800000
100 #define CONFIG_SYS_FLASH_SIZE           8
101 #define CONFIG_SYS_FLASH_SIZE_SHIFT     3
102 #define CONFIG_SYS_FLASH_EMPTY_INFO
103 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
104 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
105 #define CONFIG_SYS_MAX_FLASH_BANKS      1
106 #define CONFIG_SYS_MAX_FLASH_SECT       256
107
108 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
109 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
110                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
111                                 OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
112                                 OR_GPCM_EAD)
113 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
114 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
115
116 /*
117  * U-Boot memory configuration
118  */
119 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
120 #undef  CONFIG_SYS_RAMBOOT
121
122 #define CONFIG_SYS_INIT_RAM_LOCK
123 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
124 #define CONFIG_SYS_INIT_RAM_END 0x1000          /* End of used area in RAM*/
125
126 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
127 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
128 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
129
130 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
131 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
132 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
133
134 /*
135  * Local Bus LCRR and LBCR regs
136  *  LCRR:  DLL bypass, Clock divider is 4
137  * External Local Bus rate is
138  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
139  */
140 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
141 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
142 #define CONFIG_SYS_LBC_LBCR     0x00000000
143
144 /* LB sdram refresh timer, about 6us */
145 #define CONFIG_SYS_LBC_LSRT     0x32000000
146 /* LB refresh timer prescal, 266MHz/32*/
147 #define CONFIG_SYS_LBC_MRTPR    0x20000000
148
149 /*
150  * Serial Port
151  */
152 #define CONFIG_CONS_INDEX       1
153 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
154 #define CONFIG_SYS_NS16550
155 #define CONFIG_SYS_NS16550_SERIAL
156 #define CONFIG_SYS_NS16550_REG_SIZE     1
157 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
158
159 #define CONFIG_SYS_BAUDRATE_TABLE  \
160         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
161
162 #define CONFIG_CONSOLE          ttyS0
163 #define CONFIG_BAUDRATE         115200
164
165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
167
168 /* pass open firmware flat tree */
169 #define CONFIG_OF_LIBFDT                1
170 #define CONFIG_OF_BOARD_SETUP           1
171 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
172 #define MV_DTB_NAME     "mvblm7.dtb"
173
174 /*
175  * PCI
176  */
177 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
178 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
179 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000
180 #define CONFIG_SYS_PCI1_MMIO_BASE       (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
181 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
182 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000
183 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
184 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
185 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
186
187 #define CONFIG_NET_MULTI        1
188 #define CONFIG_NET_RETRY_COUNT  3
189
190 #define PCI_66M
191 #define CONFIG_83XX_CLKIN       66666667
192 #define CONFIG_PCI_PNP
193 #define CONFIG_PCI_SCAN_SHOW
194
195 /* TSEC */
196 #define CONFIG_GMII
197 #define CONFIG_SYS_VSC8601_SKEWFIX
198 #define CONFIG_SYS_VSC8601_SKEW_TX      3
199 #define CONFIG_SYS_VSC8601_SKEW_RX      3
200
201 #define CONFIG_TSEC1
202 #define CONFIG_TSEC2
203
204 #define CONFIG_HAS_ETH0
205 #define CONFIG_TSEC1_NAME       "TSEC0"
206 #define CONFIG_FEC1_PHY_NORXERR
207 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
208 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
209 #define TSEC1_PHY_ADDR          0x10
210 #define TSEC1_PHYIDX            0
211 #define TSEC1_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
212
213 #define CONFIG_HAS_ETH1
214 #define CONFIG_TSEC2_NAME       "TSEC1"
215 #define CONFIG_FEC2_PHY_NORXERR
216 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
217 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
218 #define TSEC2_PHY_ADDR          0x11
219 #define TSEC2_PHYIDX            0
220 #define TSEC2_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
221
222 #define CONFIG_ETHPRIME         "TSEC0"
223
224 #define CONFIG_BOOTP_VENDOREX
225 #define CONFIG_BOOTP_SUBNETMASK
226 #define CONFIG_BOOTP_GATEWAY
227 #define CONFIG_BOOTP_DNS
228 #define CONFIG_BOOTP_DNS2
229 #define CONFIG_BOOTP_HOSTNAME
230 #define CONFIG_BOOTP_BOOTFILESIZE
231 #define CONFIG_BOOTP_BOOTPATH
232 #define CONFIG_BOOTP_NTPSERVER
233 #define CONFIG_BOOTP_RANDOM_DELAY
234 #define CONFIG_BOOTP_SEND_HOSTNAME
235
236 /* USB */
237 #define CONFIG_HAS_FSL_DR_USB
238
239 /*
240  * Environment
241  */
242 #undef  CONFIG_SYS_FLASH_PROTECTION
243 #define CONFIG_ENV_OVERWRITE
244
245 #define CONFIG_ENV_IS_IN_FLASH  1
246 #define CONFIG_ENV_ADDR         0xFF800000
247 #define CONFIG_ENV_SIZE         0x2000
248 #define CONFIG_ENV_SECT_SIZE    0x2000
249 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
250 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
251
252 #define CONFIG_LOADS_ECHO
253 #define CONFIG_SYS_LOADS_BAUD_CHANGE
254
255 /*
256  * Command line configuration.
257  */
258 #include <config_cmd_default.h>
259
260 #define CONFIG_CMD_CACHE
261 #define CONFIG_CMD_IRQ
262 #define CONFIG_CMD_NET
263 #define CONFIG_CMD_MII
264 #define CONFIG_CMD_PING
265 #define CONFIG_CMD_DHCP
266 #define CONFIG_CMD_SDRAM
267 #define CONFIG_CMD_PCI
268 #define CONFIG_CMD_I2C
269 #define CONFIG_CMD_FPGA
270
271 #undef CONFIG_WATCHDOG
272
273 /*
274  * Miscellaneous configurable options
275  */
276 #define CONFIG_SYS_LONGHELP
277 #define CONFIG_CMDLINE_EDITING
278 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
279 #define CONFIG_SYS_HUSH_PARSER
280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
281
282 /* default load address */
283 #define CONFIG_SYS_LOAD_ADDR    0x2000000
284 /* default location for tftp and bootm */
285 #define CONFIG_LOADADDR 0x200000
286
287 #define CONFIG_SYS_PROMPT       "mvBL-M7> "
288 #define CONFIG_SYS_CBSIZE       256
289
290 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
291 #define CONFIG_SYS_MAXARGS      16
292 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
293 #define CONFIG_SYS_HZ           1000
294
295 /*
296  * For booting Linux, the board info and command line data
297  * have to be in the first 8 MB of memory, since this is
298  * the maximum mapped by the Linux kernel during initialization.
299  */
300 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
301
302 #define CONFIG_SYS_HRCW_LOW     0x0
303 #define CONFIG_SYS_HRCW_HIGH    0x0
304
305 /*
306  * System performance
307  */
308 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
309 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
310 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
311 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
312
313 /* clocking */
314 #define CONFIG_SYS_SCCR_ENCCM           0
315 #define CONFIG_SYS_SCCR_USBMPHCM        0
316 #define CONFIG_SYS_SCCR_USBDRCM 2
317 #define CONFIG_SYS_SCCR_TSEC1CM 1
318 #define CONFIG_SYS_SCCR_TSEC2CM 1
319
320 #define CONFIG_SYS_SICRH        0x1fff8003
321 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
322
323 #define CONFIG_SYS_HID0_INIT    0x000000000
324 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
325                                  HID0_ENABLE_INSTRUCTION_CACHE)
326
327 #define CONFIG_SYS_HID2 HID2_HBE
328 #define CONFIG_HIGH_BATS        1
329
330 /* DDR  */
331 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
332 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
333
334 /* PCI  */
335 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
336 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
337 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
338                                 BATL_GUARDEDSTORAGE)
339 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
340
341 /* no PCI2 */
342 #define CONFIG_SYS_IBAT3L       0
343 #define CONFIG_SYS_IBAT3U       0
344 #define CONFIG_SYS_IBAT4L       0
345 #define CONFIG_SYS_IBAT4U       0
346
347 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
348 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
349                                 BATL_GUARDEDSTORAGE)
350 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
351
352 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
353 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
354                                  BATL_GUARDEDSTORAGE)
355 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
356 #define CONFIG_SYS_IBAT7L       0
357 #define CONFIG_SYS_IBAT7U       0
358
359 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
360 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
361 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
362 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
363 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
364 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
365 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
366 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
367 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
368 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
369 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
370 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
371 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
372 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
373 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
374 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
375
376 /*
377  * Internal Definitions
378  *
379  * Boot Flags
380  */
381 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
382 #define BOOTFLAG_WARM   0x02    /* Software reboot */
383
384
385 /*
386  * Environment Configuration
387  */
388 #define CONFIG_ENV_OVERWRITE
389
390 #define CONFIG_NETDEV           eth0
391
392 /* Default path and filenames */
393 #define CONFIG_BOOTDELAY                5
394 #define CONFIG_AUTOBOOT_KEYED
395 #define CONFIG_AUTOBOOT_STOP_STR        "s"
396 #define CONFIG_ZERO_BOOTDELAY_CHECK
397 #define CONFIG_RESET_TO_RETRY           1000
398
399 #define MV_CI                   mvBL-M7
400 #define MV_VCI                  mvBL-M7
401 #define MV_FPGA_DATA            0xfff40000
402 #define MV_FPGA_SIZE            0
403 #define MV_KERNEL_ADDR          0xff810000
404 #define MV_INITRD_ADDR          0xffb00000
405 #define MV_SCRIPT_ADDR          0xff804000
406 #define MV_SCRIPT_ADDR2         0xff806000
407 #define MV_DTB_ADDR             0xff808000
408 #define MV_INITRD_LENGTH        0x00400000
409
410 #define CONFIG_SHOW_BOOT_PROGRESS 1
411
412 #define MV_KERNEL_ADDR_RAM      0x00100000
413 #define MV_DTB_ADDR_RAM         0x00600000
414 #define MV_INITRD_ADDR_RAM      0x01000000
415
416 #define CONFIG_BOOTCOMMAND      "if imi ${script_addr}; \
417                                         then source ${script_addr};  \
418                                         else source ${script_addr2}; \
419                                 fi;"
420 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
421
422 #define CONFIG_EXTRA_ENV_SETTINGS                               \
423         "console_nr=0\0"                                        \
424         "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"                \
425         "stdin=serial\0"                                        \
426         "stdout=serial\0"                                       \
427         "stderr=serial\0"                                       \
428         "fpga=0\0"                                              \
429         "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"                   \
430         "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"               \
431         "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"              \
432         "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0"            \
433         "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"           \
434         "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"   \
435         "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"           \
436         "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"   \
437         "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"       \
438         "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"                 \
439         "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"         \
440         "dtb_name=" MK_STR(MV_DTB_NAME) "\0"                    \
441         "mv_version=" U_BOOT_VERSION "\0"                       \
442         "dhcp_client_id=" MK_STR(MV_CI) "\0"                    \
443         "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"     \
444         "netretry=no\0"                                         \
445         "use_static_ipaddr=no\0"                                \
446         "static_ipaddr=192.168.90.10\0"                         \
447         "static_netmask=255.255.255.0\0"                        \
448         "static_gateway=0.0.0.0\0"                              \
449         "initrd_name=uInitrd.mvBL-M7-rfs\0"                     \
450         "zcip=no\0"                                             \
451         "netboot=yes\0"                                         \
452         "mvtest=Ff\0"                                           \
453         "tried_bootfromflash=no\0"                              \
454         "tried_bootfromnet=no\0"                                \
455         "bootfile=mvblm72625.boot\0"                            \
456         "use_dhcp=yes\0"                                        \
457         "gev_start=yes\0"                                       \
458         "mvbcdma_debug=0\0"                                     \
459         "mvbcia_debug=0\0"                                      \
460         "propdev_debug=0\0"                                     \
461         "gevss_debug=0\0"                                       \
462         "watchdog=0\0"                                          \
463         "usb_dr_mode=host\0"                                    \
464         "sensor_cnt=2\0"                                        \
465         ""
466
467 #define CONFIG_FPGA_COUNT       1
468 #define CONFIG_FPGA             CONFIG_SYS_ALTERA_CYCLON2
469 #define CONFIG_FPGA_ALTERA
470 #define CONFIG_FPGA_CYCLON2
471
472 #endif