freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}
[karo-tx-uboot.git] / include / configs / T1040QDS.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25
26 /*
27  * T1040 QDS board configuration file
28  */
29 #define CONFIG_T1040QDS
30 #define CONFIG_PHYS_64BIT
31
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
34 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
37 #endif
38
39 /* High Level Configuration Options */
40 #define CONFIG_BOOKE
41 #define CONFIG_E500                     /* BOOKE e500 family */
42 #define CONFIG_E500MC                   /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
44 #define CONFIG_MP                       /* support multiple processors */
45
46 #ifndef CONFIG_SYS_TEXT_BASE
47 #define CONFIG_SYS_TEXT_BASE    0xeff40000
48 #endif
49
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
52 #endif
53
54 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
55 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
56 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
57 #define CONFIG_PCI                      /* Enable PCI/PCIE */
58 #define CONFIG_PCI_INDIRECT_BRIDGE
59 #define CONFIG_PCIE1                    /* PCIE controler 1 */
60 #define CONFIG_PCIE2                    /* PCIE controler 2 */
61 #define CONFIG_PCIE3                    /* PCIE controler 3 */
62 #define CONFIG_PCIE4                    /* PCIE controler 4 */
63
64 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
66
67 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
68
69 #define CONFIG_ENV_OVERWRITE
70
71 #ifdef CONFIG_SYS_NO_FLASH
72 #define CONFIG_ENV_IS_NOWHERE
73 #else
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
77 #endif
78
79 #ifndef CONFIG_SYS_NO_FLASH
80 #if defined(CONFIG_SPIFLASH)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_IS_IN_SPI_FLASH
83 #define CONFIG_ENV_SPI_BUS              0
84 #define CONFIG_ENV_SPI_CS               0
85 #define CONFIG_ENV_SPI_MAX_HZ           10000000
86 #define CONFIG_ENV_SPI_MODE             0
87 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
88 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
89 #define CONFIG_ENV_SECT_SIZE            0x10000
90 #elif defined(CONFIG_SDCARD)
91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_ENV_IS_IN_MMC
93 #define CONFIG_SYS_MMC_ENV_DEV          0
94 #define CONFIG_ENV_SIZE                 0x2000
95 #define CONFIG_ENV_OFFSET               (512 * 1658)
96 #elif defined(CONFIG_NAND)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_NAND
99 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
100 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #else
102 #define CONFIG_ENV_IS_IN_FLASH
103 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
104 #define CONFIG_ENV_SIZE         0x2000
105 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
106 #endif
107 #else /* CONFIG_SYS_NO_FLASH */
108 #define CONFIG_ENV_SIZE                0x2000
109 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
110 #endif
111
112 #ifndef __ASSEMBLY__
113 unsigned long get_board_sys_clk(void);
114 unsigned long get_board_ddr_clk(void);
115 #endif
116
117 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
118 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
119
120 /*
121  * These can be toggled for performance analysis, otherwise use default.
122  */
123 #define CONFIG_SYS_CACHE_STASHING
124 #define CONFIG_BACKSIDE_L2_CACHE
125 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
126 #define CONFIG_BTB                      /* toggle branch predition */
127 #define CONFIG_DDR_ECC
128 #ifdef CONFIG_DDR_ECC
129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
130 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
131 #endif
132
133 #define CONFIG_ENABLE_36BIT_PHYS
134
135 #define CONFIG_ADDR_MAP
136 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
137
138 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END          0x00400000
140 #define CONFIG_SYS_ALT_MEMTEST
141 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
142
143 /*
144  *  Config the L3 Cache as L3 SRAM
145  */
146 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
147
148 #define CONFIG_SYS_DCSRBAR              0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
150
151 /* EEPROM */
152 #define CONFIG_ID_EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
159
160 /*
161  * DDR Setup
162  */
163 #define CONFIG_VERY_BIG_RAM
164 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
165 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
166
167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
168 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
169 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
170
171 #define CONFIG_DDR_SPD
172 #define CONFIG_SYS_FSL_DDR3
173 #define CONFIG_FSL_DDR_INTERACTIVE
174
175 #define CONFIG_SYS_SPD_BUS_NUM  0
176 #define SPD_EEPROM_ADDRESS      0x51
177
178 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
179
180 /*
181  * IFC Definitions
182  */
183 #define CONFIG_SYS_FLASH_BASE   0xe0000000
184 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
185
186 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
187 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
188                                 + 0x8000000) | \
189                                 CSPR_PORT_SIZE_16 | \
190                                 CSPR_MSEL_NOR | \
191                                 CSPR_V)
192 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
193 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
194                                 CSPR_PORT_SIZE_16 | \
195                                 CSPR_MSEL_NOR | \
196                                 CSPR_V)
197 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
198 /* NOR Flash Timing Params */
199 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
200 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
201                                 FTIM0_NOR_TEADC(0x5) | \
202                                 FTIM0_NOR_TEAHC(0x5))
203 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
204                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
205                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
206 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
207                                 FTIM2_NOR_TCH(0x4) | \
208                                 FTIM2_NOR_TWPH(0x0E) | \
209                                 FTIM2_NOR_TWP(0x1c))
210 #define CONFIG_SYS_NOR_FTIM3    0x0
211
212 #define CONFIG_SYS_FLASH_QUIET_TEST
213 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
214
215 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
217 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
218 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
219
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
222                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
223 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
224 #define QIXIS_BASE              0xffdf0000
225 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
226 #define QIXIS_LBMAP_SWITCH              0x06
227 #define QIXIS_LBMAP_MASK                0x0f
228 #define QIXIS_LBMAP_SHIFT               0
229 #define QIXIS_LBMAP_DFLTBANK            0x00
230 #define QIXIS_LBMAP_ALTBANK             0x04
231 #define QIXIS_RST_CTL_RESET             0x31
232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
233 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
235 #define QIXIS_RST_FORCE_MEM             0x01
236
237 #define CONFIG_SYS_CSPR3_EXT    (0xf)
238 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
239                                 | CSPR_PORT_SIZE_8 \
240                                 | CSPR_MSEL_GPCM \
241                                 | CSPR_V)
242 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
243 #define CONFIG_SYS_CSOR3        0x0
244 /* QIXIS Timing parameters for IFC CS3 */
245 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
246                                         FTIM0_GPCM_TEADC(0x0e) | \
247                                         FTIM0_GPCM_TEAHC(0x0e))
248 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
249                                         FTIM1_GPCM_TRAD(0x3f))
250 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
251                                         FTIM2_GPCM_TCH(0x8) | \
252                                         FTIM2_GPCM_TWP(0x1f))
253 #define CONFIG_SYS_CS3_FTIM3            0x0
254
255 #define CONFIG_NAND_FSL_IFC
256 #define CONFIG_SYS_NAND_BASE            0xff800000
257 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
258
259 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
260 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
261                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
262                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
263                                 | CSPR_V)
264 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
265
266 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
267                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
268                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
269                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
270                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
271                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
272                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
273
274 #define CONFIG_SYS_NAND_ONFI_DETECTION
275
276 /* ONFI NAND Flash mode0 Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
278                                         FTIM0_NAND_TWP(0x18)   | \
279                                         FTIM0_NAND_TWCHT(0x07) | \
280                                         FTIM0_NAND_TWH(0x0a))
281 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
282                                         FTIM1_NAND_TWBE(0x39)  | \
283                                         FTIM1_NAND_TRR(0x0e)   | \
284                                         FTIM1_NAND_TRP(0x18))
285 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
286                                         FTIM2_NAND_TREH(0x0a) | \
287                                         FTIM2_NAND_TWHRE(0x1e))
288 #define CONFIG_SYS_NAND_FTIM3           0x0
289
290 #define CONFIG_SYS_NAND_DDR_LAW         11
291 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
292 #define CONFIG_SYS_MAX_NAND_DEVICE      1
293 #define CONFIG_MTD_NAND_VERIFY_WRITE
294 #define CONFIG_CMD_NAND
295
296 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
297
298 #if defined(CONFIG_NAND)
299 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
323 #else
324 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
325 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
326 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
340 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
348 #endif
349
350 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
351
352 #if defined(CONFIG_RAMBOOT_PBL)
353 #define CONFIG_SYS_RAMBOOT
354 #endif
355
356 #define CONFIG_BOARD_EARLY_INIT_R
357 #define CONFIG_MISC_INIT_R
358
359 #define CONFIG_HWCONFIG
360
361 /* define to use L1 as initial stack */
362 #define CONFIG_L1_INIT_RAM
363 #define CONFIG_SYS_INIT_RAM_LOCK
364 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
367 /* The assembler doesn't like typecast */
368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
369         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
370           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
371 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
372
373 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
374                                         GENERATED_GBL_DATA_SIZE)
375 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
376
377 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
378 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
379
380 /* Serial Port - controlled on board with jumper J8
381  * open - index 2
382  * shorted - index 1
383  */
384 #define CONFIG_CONS_INDEX       1
385 #define CONFIG_SYS_NS16550
386 #define CONFIG_SYS_NS16550_SERIAL
387 #define CONFIG_SYS_NS16550_REG_SIZE     1
388 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
389
390 #define CONFIG_SYS_BAUDRATE_TABLE       \
391         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
392
393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
397 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
399
400 /* Use the HUSH parser */
401 #define CONFIG_SYS_HUSH_PARSER
402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
403
404 /* Video */
405 #define CONFIG_FSL_DIU_FB
406 #ifdef CONFIG_FSL_DIU_FB
407 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
408 #define CONFIG_VIDEO
409 #define CONFIG_CMD_BMP
410 #define CONFIG_CFB_CONSOLE
411 #define CONFIG_VIDEO_SW_CURSOR
412 #define CONFIG_VGA_AS_SINGLE_DEVICE
413 #define CONFIG_VIDEO_LOGO
414 #define CONFIG_VIDEO_BMP_LOGO
415 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
416 /*
417  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
418  * disable empty flash sector detection, which is I/O-intensive.
419  */
420 #undef CONFIG_SYS_FLASH_EMPTY_INFO
421 #endif
422
423 /* pass open firmware flat tree */
424 #define CONFIG_OF_LIBFDT
425 #define CONFIG_OF_BOARD_SETUP
426 #define CONFIG_OF_STDOUT_VIA_ALIAS
427
428 /* new uImage format support */
429 #define CONFIG_FIT
430 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
431
432 /* I2C */
433 #define CONFIG_SYS_I2C
434 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
435 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
436 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
437 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
438 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
439 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
440 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
441
442 #define I2C_MUX_PCA_ADDR                0x77
443 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
444
445
446 /* I2C bus multiplexer */
447 #define I2C_MUX_CH_DEFAULT      0x8
448 #define I2C_MUX_CH_DIU          0xC
449
450 /* LDI/DVI Encoder for display */
451 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
452 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
453
454 /*
455  * RTC configuration
456  */
457 #define RTC
458 #define CONFIG_RTC_DS3231               1
459 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
460
461 /*
462  * eSPI - Enhanced SPI
463  */
464 #define CONFIG_FSL_ESPI
465 #define CONFIG_SPI_FLASH
466 #define CONFIG_SPI_FLASH_STMICRO
467 #define CONFIG_SPI_FLASH_SST
468 #define CONFIG_SPI_FLASH_EON
469 #define CONFIG_CMD_SF
470 #define CONFIG_SF_DEFAULT_SPEED         10000000
471 #define CONFIG_SF_DEFAULT_MODE          0
472
473 /*
474  * General PCI
475  * Memory space is mapped 1-1, but I/O space must start from 0.
476  */
477
478 #ifdef CONFIG_PCI
479 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
480 #ifdef CONFIG_PCIE1
481 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
482 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
483 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
484 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
485 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
486 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
487 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
488 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
489 #endif
490
491 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
492 #ifdef CONFIG_PCIE2
493 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
494 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
495 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
496 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
497 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
498 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
499 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
500 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
501 #endif
502
503 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
504 #ifdef CONFIG_PCIE3
505 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
506 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
507 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
508 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
509 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
510 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
511 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
512 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
513 #endif
514
515 /* controller 4, Base address 203000 */
516 #ifdef CONFIG_PCIE4
517 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
518 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
519 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
520 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
521 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
522 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
523 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
524 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
525 #endif
526
527 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
528 #define CONFIG_E1000
529
530 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
531 #define CONFIG_DOS_PARTITION
532 #endif  /* CONFIG_PCI */
533
534 /* SATA */
535 #define CONFIG_FSL_SATA_V2
536 #ifdef CONFIG_FSL_SATA_V2
537 #define CONFIG_LIBATA
538 #define CONFIG_FSL_SATA
539
540 #define CONFIG_SYS_SATA_MAX_DEVICE      2
541 #define CONFIG_SATA1
542 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
543 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
544 #define CONFIG_SATA2
545 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
546 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
547
548 #define CONFIG_LBA48
549 #define CONFIG_CMD_SATA
550 #define CONFIG_DOS_PARTITION
551 #define CONFIG_CMD_EXT2
552 #endif
553
554 /*
555 * USB
556 */
557 #define CONFIG_HAS_FSL_DR_USB
558
559 #ifdef CONFIG_HAS_FSL_DR_USB
560 #define CONFIG_USB_EHCI
561
562 #ifdef CONFIG_USB_EHCI
563 #define CONFIG_CMD_USB
564 #define CONFIG_USB_STORAGE
565 #define CONFIG_USB_EHCI_FSL
566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
567 #define CONFIG_CMD_EXT2
568 #endif
569 #endif
570
571 #define CONFIG_MMC
572
573 #ifdef CONFIG_MMC
574 #define CONFIG_FSL_ESDHC
575 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
576 #define CONFIG_CMD_MMC
577 #define CONFIG_GENERIC_MMC
578 #define CONFIG_CMD_EXT2
579 #define CONFIG_CMD_FAT
580 #define CONFIG_DOS_PARTITION
581 #endif
582
583 /* Qman/Bman */
584 #ifndef CONFIG_NOBQFMAN
585 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
586 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
587 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
588 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
589 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
590 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
591 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
592 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
593 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
594
595 #define CONFIG_SYS_DPAA_FMAN
596 #define CONFIG_SYS_DPAA_PME
597
598 /* Default address of microcode for the Linux Fman driver */
599 #if defined(CONFIG_SPIFLASH)
600 /*
601  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
602  * env, so we got 0x110000.
603  */
604 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
605 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
606 #elif defined(CONFIG_SDCARD)
607 /*
608  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
609  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
610  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
611  */
612 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
613 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1680)
614 #elif defined(CONFIG_NAND)
615 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
616 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
617 #else
618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
619 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEFF00000
620 #endif
621 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
622 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
623 #endif /* CONFIG_NOBQFMAN */
624
625 #ifdef CONFIG_SYS_DPAA_FMAN
626 #define CONFIG_FMAN_ENET
627 #define CONFIG_PHYLIB_10G
628 #define CONFIG_PHY_VITESSE
629 #define CONFIG_PHY_REALTEK
630 #define CONFIG_PHY_TERANETICS
631 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
632 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
633 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
634 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
635 #endif
636
637 #ifdef CONFIG_FMAN_ENET
638 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
639 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
640
641 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
642 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
643 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
644 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
645
646 #define CONFIG_MII              /* MII PHY management */
647 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
648 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
649 #endif
650
651 /*
652  * Environment
653  */
654 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
655 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
656
657 /*
658  * Command line configuration.
659  */
660 #include <config_cmd_default.h>
661
662 #define CONFIG_CMD_DATE
663 #define CONFIG_CMD_DHCP
664 #define CONFIG_CMD_EEPROM
665 #define CONFIG_CMD_ELF
666 #define CONFIG_CMD_ERRATA
667 #define CONFIG_CMD_GREPENV
668 #define CONFIG_CMD_IRQ
669 #define CONFIG_CMD_I2C
670 #define CONFIG_CMD_MII
671 #define CONFIG_CMD_PING
672 #define CONFIG_CMD_REGINFO
673 #define CONFIG_CMD_SETEXPR
674
675 #ifdef CONFIG_PCI
676 #define CONFIG_CMD_PCI
677 #define CONFIG_CMD_NET
678 #endif
679
680 /*
681  * Miscellaneous configurable options
682  */
683 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
684 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
685 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
686 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
687 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
688 #ifdef CONFIG_CMD_KGDB
689 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
690 #else
691 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
692 #endif
693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
694 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
695 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
696
697 /*
698  * For booting Linux, the board info and command line data
699  * have to be in the first 64 MB of memory, since this is
700  * the maximum mapped by the Linux kernel during initialization.
701  */
702 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
703 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
704
705 #ifdef CONFIG_CMD_KGDB
706 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
707 #endif
708
709 /*
710  * Environment Configuration
711  */
712 #define CONFIG_ROOTPATH         "/opt/nfsroot"
713 #define CONFIG_BOOTFILE         "uImage"
714 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
715
716 /* default location for tftp and bootm */
717 #define CONFIG_LOADADDR         1000000
718
719 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
720
721 #define CONFIG_BAUDRATE 115200
722
723 #define __USB_PHY_TYPE  utmi
724
725 #define CONFIG_EXTRA_ENV_SETTINGS                               \
726         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
727         "bank_intlv=cs0_cs1;"                                   \
728         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
729         "netdev=eth0\0"                                         \
730         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
731         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
732         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
733         "tftpflash=tftpboot $loadaddr $uboot && "               \
734         "protect off $ubootaddr +$filesize && "                 \
735         "erase $ubootaddr +$filesize && "                       \
736         "cp.b $loadaddr $ubootaddr $filesize && "               \
737         "protect on $ubootaddr +$filesize && "                  \
738         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
739         "consoledev=ttyS0\0"                                    \
740         "ramdiskaddr=2000000\0"                                 \
741         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
742         "fdtaddr=c00000\0"                                      \
743         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
744         "bdev=sda3\0"                                           \
745         "c=ffe\0"
746
747 #define CONFIG_LINUX                       \
748         "setenv bootargs root=/dev/ram rw "            \
749         "console=$consoledev,$baudrate $othbootargs;"  \
750         "setenv ramdiskaddr 0x02000000;"               \
751         "setenv fdtaddr 0x00c00000;"                   \
752         "setenv loadaddr 0x1000000;"                   \
753         "bootm $loadaddr $ramdiskaddr $fdtaddr"
754
755 #define CONFIG_HDBOOT                                   \
756         "setenv bootargs root=/dev/$bdev rw "           \
757         "console=$consoledev,$baudrate $othbootargs;"   \
758         "tftp $loadaddr $bootfile;"                     \
759         "tftp $fdtaddr $fdtfile;"                       \
760         "bootm $loadaddr - $fdtaddr"
761
762 #define CONFIG_NFSBOOTCOMMAND                   \
763         "setenv bootargs root=/dev/nfs rw "     \
764         "nfsroot=$serverip:$rootpath "          \
765         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
766         "console=$consoledev,$baudrate $othbootargs;"   \
767         "tftp $loadaddr $bootfile;"             \
768         "tftp $fdtaddr $fdtfile;"               \
769         "bootm $loadaddr - $fdtaddr"
770
771 #define CONFIG_RAMBOOTCOMMAND                           \
772         "setenv bootargs root=/dev/ram rw "             \
773         "console=$consoledev,$baudrate $othbootargs;"   \
774         "tftp $ramdiskaddr $ramdiskfile;"               \
775         "tftp $loadaddr $bootfile;"                     \
776         "tftp $fdtaddr $fdtfile;"                       \
777         "bootm $loadaddr $ramdiskaddr $fdtaddr"
778
779 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
780
781 #ifdef CONFIG_SECURE_BOOT
782 #include <asm/fsl_secure_boot.h>
783 #endif
784
785 #endif  /* __CONFIG_H */