freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}
[karo-tx-uboot.git] / include / configs / T208xRDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T2080 RDB/PCIe board configuration file
9  */
10
11 #ifndef __T2080RDB_H
12 #define __T2080RDB_H
13
14 #define CONFIG_T2080RDB
15 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
16 #define CONFIG_MMC
17 #define CONFIG_SPI_FLASH
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
20
21 /* High Level Configuration Options */
22 #define CONFIG_PHYS_64BIT
23 #define CONFIG_BOOKE
24 #define CONFIG_E500             /* BOOKE e500 family */
25 #define CONFIG_E500MC           /* BOOKE e500mc family */
26 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
27 #define CONFIG_MP               /* support multiple processors */
28 #define CONFIG_ENABLE_36BIT_PHYS
29
30 #ifdef CONFIG_PHYS_64BIT
31 #define CONFIG_ADDR_MAP 1
32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
33 #endif
34
35 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
36 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
37 #define CONFIG_FSL_IFC          /* Enable IFC Support */
38 #define CONFIG_FSL_LAW          /* Use common FSL init code */
39 #define CONFIG_ENV_OVERWRITE
40
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
43 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
46 #endif
47
48 #define CONFIG_SRIO_PCIE_BOOT_MASTER
49 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
50 /* Set 1M boot space */
51 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
53                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
54 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
55 #define CONFIG_SYS_NO_FLASH
56 #endif
57
58 #ifndef CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_TEXT_BASE    0xeff40000
60 #endif
61
62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
63 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
64 #endif
65
66 /*
67  * These can be toggled for performance analysis, otherwise use default.
68  */
69 #define CONFIG_SYS_CACHE_STASHING
70 #define CONFIG_BTB              /* toggle branch predition */
71 #define CONFIG_DDR_ECC
72 #ifdef CONFIG_DDR_ECC
73 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
74 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
75 #endif
76
77 #ifdef CONFIG_SYS_NO_FLASH
78 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
79 #define CONFIG_ENV_IS_NOWHERE
80 #endif
81 #else
82 #define CONFIG_FLASH_CFI_DRIVER
83 #define CONFIG_SYS_FLASH_CFI
84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
85 #endif
86
87 #if defined(CONFIG_SPIFLASH)
88 #define CONFIG_SYS_EXTRA_ENV_RELOC
89 #define CONFIG_ENV_IS_IN_SPI_FLASH
90 #define CONFIG_ENV_SPI_BUS      0
91 #define CONFIG_ENV_SPI_CS       0
92 #define CONFIG_ENV_SPI_MAX_HZ   10000000
93 #define CONFIG_ENV_SPI_MODE     0
94 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
95 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
96 #define CONFIG_ENV_SECT_SIZE    0x10000
97 #elif defined(CONFIG_SDCARD)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_IS_IN_MMC
100 #define CONFIG_SYS_MMC_ENV_DEV  0
101 #define CONFIG_ENV_SIZE         0x2000
102 #define CONFIG_ENV_OFFSET       (512 * 1658)
103 #elif defined(CONFIG_NAND)
104 #define CONFIG_SYS_EXTRA_ENV_RELOC
105 #define CONFIG_ENV_IS_IN_NAND
106 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
107 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
108 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
109 #define CONFIG_ENV_IS_IN_REMOTE
110 #define CONFIG_ENV_ADDR         0xffe20000
111 #define CONFIG_ENV_SIZE         0x2000
112 #elif defined(CONFIG_ENV_IS_NOWHERE)
113 #define CONFIG_ENV_SIZE         0x2000
114 #else
115 #define CONFIG_ENV_IS_IN_FLASH
116 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
117 #define CONFIG_ENV_SIZE         0x2000
118 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
119 #endif
120
121 #ifndef __ASSEMBLY__
122 unsigned long get_board_sys_clk(void);
123 unsigned long get_board_ddr_clk(void);
124 #endif
125
126 #define CONFIG_SYS_CLK_FREQ     66660000
127 #define CONFIG_DDR_CLK_FREQ     133330000
128
129 /*
130  * Config the L3 Cache as L3 SRAM
131  */
132 #define CONFIG_SYS_INIT_L3_ADDR  CONFIG_RAMBOOT_TEXT_BASE
133
134 #define CONFIG_SYS_DCSRBAR      0xf0000000
135 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
136
137 /* EEPROM */
138 #define CONFIG_ID_EEPROM
139 #define CONFIG_SYS_I2C_EEPROM_NXID
140 #define CONFIG_SYS_EEPROM_BUS_NUM       0
141 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
143
144 /*
145  * DDR Setup
146  */
147 #define CONFIG_VERY_BIG_RAM
148 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
149 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
150 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
152 #define CONFIG_DDR_SPD
153 #define CONFIG_SYS_FSL_DDR3
154 #undef CONFIG_FSL_DDR_INTERACTIVE
155 #define CONFIG_SYS_SPD_BUS_NUM  0
156 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
157 #define SPD_EEPROM_ADDRESS1     0x51
158 #define SPD_EEPROM_ADDRESS2     0x52
159 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
160 #define CTRL_INTLV_PREFERED     cacheline
161
162 /*
163  * IFC Definitions
164  */
165 #define CONFIG_SYS_FLASH_BASE           0xe8000000
166 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
167 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
168 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
169                                 CSPR_PORT_SIZE_16 | \
170                                 CSPR_MSEL_NOR | \
171                                 CSPR_V)
172 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
173
174 /* NOR Flash Timing Params */
175 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
176
177 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
178                                 FTIM0_NOR_TEADC(0x5) | \
179                                 FTIM0_NOR_TEAHC(0x5))
180 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
181                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
182                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
183 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
184                                 FTIM2_NOR_TCH(0x4) | \
185                                 FTIM2_NOR_TWPH(0x0E) | \
186                                 FTIM2_NOR_TWP(0x1c))
187 #define CONFIG_SYS_NOR_FTIM3    0x0
188
189 #define CONFIG_SYS_FLASH_QUIET_TEST
190 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
191
192 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
193 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
194 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
195 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
198
199 /* CPLD on IFC */
200 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
201 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
202 #define CONFIG_SYS_CSPR2_EXT    (0xf)
203 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
204                                 | CSPR_PORT_SIZE_8 \
205                                 | CSPR_MSEL_GPCM \
206                                 | CSPR_V)
207 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
208 #define CONFIG_SYS_CSOR2        0x0
209
210 /* CPLD Timing parameters for IFC CS2 */
211 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
212                                         FTIM0_GPCM_TEADC(0x0e) | \
213                                         FTIM0_GPCM_TEAHC(0x0e))
214 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
215                                         FTIM1_GPCM_TRAD(0x1f))
216 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
217                                         FTIM2_GPCM_TCH(0x0) | \
218                                         FTIM2_GPCM_TWP(0x1f))
219 #define CONFIG_SYS_CS2_FTIM3            0x0
220
221 /* NAND Flash on IFC */
222 #define CONFIG_NAND_FSL_IFC
223 #define CONFIG_SYS_NAND_BASE            0xff800000
224 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
225
226 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
227 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
228                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
229                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
230                                 | CSPR_V)
231 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
232
233 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
234                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
235                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
236                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
237                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
238                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
239                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
240
241 #define CONFIG_SYS_NAND_ONFI_DETECTION
242
243 /* ONFI NAND Flash mode0 Timing Params */
244 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
245                                         FTIM0_NAND_TWP(0x18)    | \
246                                         FTIM0_NAND_TWCHT(0x07)  | \
247                                         FTIM0_NAND_TWH(0x0a))
248 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
249                                         FTIM1_NAND_TWBE(0x39)   | \
250                                         FTIM1_NAND_TRR(0x0e)    | \
251                                         FTIM1_NAND_TRP(0x18))
252 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
253                                         FTIM2_NAND_TREH(0x0a)   | \
254                                         FTIM2_NAND_TWHRE(0x1e))
255 #define CONFIG_SYS_NAND_FTIM3           0x0
256
257 #define CONFIG_SYS_NAND_DDR_LAW         11
258 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
259 #define CONFIG_SYS_MAX_NAND_DEVICE      1
260 #define CONFIG_MTD_NAND_VERIFY_WRITE
261 #define CONFIG_CMD_NAND
262 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
263
264 #if defined(CONFIG_NAND)
265 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
266 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
267 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
268 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
269 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
273 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
281 #else
282 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
284 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
291 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
292 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
293 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
294 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
295 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
296 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
297 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
298 #endif
299
300 #if defined(CONFIG_RAMBOOT_PBL)
301 #define CONFIG_SYS_RAMBOOT
302 #endif
303
304 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE
305 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
306 #define CONFIG_MISC_INIT_R
307 #define CONFIG_HWCONFIG
308
309 /* define to use L1 as initial stack */
310 #define CONFIG_L1_INIT_RAM
311 #define CONFIG_SYS_INIT_RAM_LOCK
312 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
315 /* The assembler doesn't like typecast */
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
317                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
318                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
319 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
320 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
321                                                 GENERATED_GBL_DATA_SIZE)
322 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
323 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
324 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
325
326 /*
327  * Serial Port
328  */
329 #define CONFIG_CONS_INDEX               1
330 #define CONFIG_SYS_NS16550
331 #define CONFIG_SYS_NS16550_SERIAL
332 #define CONFIG_SYS_NS16550_REG_SIZE     1
333 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
334 #define CONFIG_SYS_BAUDRATE_TABLE       \
335         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
340
341 /* Use the HUSH parser */
342 #define CONFIG_SYS_HUSH_PARSER
343 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
344
345 /* pass open firmware flat tree */
346 #define CONFIG_OF_LIBFDT
347 #define CONFIG_OF_BOARD_SETUP
348 #define CONFIG_OF_STDOUT_VIA_ALIAS
349
350 /* new uImage format support */
351 #define CONFIG_FIT
352 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
353
354 /*
355  * I2C
356  */
357 #define CONFIG_SYS_I2C
358 #define CONFIG_SYS_I2C_FSL
359 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
360 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
361 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
362 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
363 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
364 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
365 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
366 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
367 #define CONFIG_SYS_FSL_I2C_SPEED   100000
368 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
369 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
370 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
371 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
372 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
373 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
374 #define I2C_MUX_CH_DEFAULT      0x8
375
376
377 /*
378  * RapidIO
379  */
380 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
381 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
382 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
383 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
384 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
385 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
386 /*
387  * for slave u-boot IMAGE instored in master memory space,
388  * PHYS must be aligned based on the SIZE
389  */
390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
391 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
392 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
393 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
394 /*
395  * for slave UCODE and ENV instored in master memory space,
396  * PHYS must be aligned based on the SIZE
397  */
398 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
399 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
400 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
401
402 /* slave core release by master*/
403 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
404 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
405
406 /*
407  * SRIO_PCIE_BOOT - SLAVE
408  */
409 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
410 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
411 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
412                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
413 #endif
414
415 /*
416  * eSPI - Enhanced SPI
417  */
418 #ifdef CONFIG_SPI_FLASH
419 #define CONFIG_FSL_ESPI
420 #define CONFIG_SPI_FLASH_STMICRO
421 #define CONFIG_SPI_FLASH_BAR
422 #define CONFIG_CMD_SF
423 #define CONFIG_SF_DEFAULT_SPEED  10000000
424 #define CONFIG_SF_DEFAULT_MODE    0
425 #endif
426
427 /*
428  * General PCI
429  * Memory space is mapped 1-1, but I/O space must start from 0.
430  */
431 #define CONFIG_PCI              /* Enable PCI/PCIE */
432 #define CONFIG_PCIE1            /* PCIE controler 1 */
433 #define CONFIG_PCIE2            /* PCIE controler 2 */
434 #define CONFIG_PCIE3            /* PCIE controler 3 */
435 #define CONFIG_PCIE4            /* PCIE controler 4 */
436 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
437 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
438 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
439 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
440 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
441 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
442 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
443 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
444 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
445 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
446 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
447
448 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
449 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
450 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
452 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
453 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
454 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
455 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
456 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
457
458 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
459 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
460 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
461 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
462 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
463 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
464 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
465 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
466 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
467
468 /* controller 4, Base address 203000 */
469 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
470 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
471 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
472 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
473 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
474 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
475 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
476
477 #ifdef CONFIG_PCI
478 #define CONFIG_PCI_INDIRECT_BRIDGE
479 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
480 #define CONFIG_NET_MULTI
481 #define CONFIG_E1000
482 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
483 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
484 #define CONFIG_DOS_PARTITION
485 #endif
486
487 /* Qman/Bman */
488 #ifndef CONFIG_NOBQFMAN
489 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
490 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
491 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
492 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
493 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
494 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
495 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
496 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
497 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
498
499 #define CONFIG_SYS_DPAA_FMAN
500 #define CONFIG_SYS_DPAA_PME
501 #define CONFIG_SYS_PMAN
502 #define CONFIG_SYS_DPAA_DCE
503 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
504 #define CONFIG_SYS_INTERLAKEN
505
506 /* Default address of microcode for the Linux Fman driver */
507 #if defined(CONFIG_SPIFLASH)
508 /*
509  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
510  * env, so we got 0x110000.
511  */
512 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
513 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
514 #define CONFIG_CORTINA_FW_ADDR          0x120000
515
516 #elif defined(CONFIG_SDCARD)
517 /*
518  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
519  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
520  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
521  */
522 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
523 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1680)
524 #define CONFIG_CORTINA_FW_ADDR          (512 * 1808)
525
526 #elif defined(CONFIG_NAND)
527 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
529 #define CONFIG_CORTINA_FW_ADDR          (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
530 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
531 /*
532  * Slave has no ucode locally, it can fetch this from remote. When implementing
533  * in two corenet boards, slave's ucode could be stored in master's memory
534  * space, the address can be mapped from slave TLB->slave LAW->
535  * slave SRIO or PCIE outbound window->master inbound window->
536  * master LAW->the ucode address in master's memory space.
537  */
538 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
539 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
540 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
541 #else
542 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
543 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEFF00000
544 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
545 #endif
546 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
547 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
548 #endif /* CONFIG_NOBQFMAN */
549
550 #ifdef CONFIG_SYS_DPAA_FMAN
551 #define CONFIG_FMAN_ENET
552 #define CONFIG_PHYLIB_10G
553 #define CONFIG_PHY_CORTINA
554 #define CONFIG_PHY_AQ1202
555 #define CONFIG_PHY_REALTEK
556 #define CONFIG_CORTINA_FW_LENGTH        0x40000
557 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
558 #define RGMII_PHY2_ADDR         0x02
559 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
560 #define CORTINA_PHY_ADDR2       0x0d
561 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
562 #define FM1_10GEC4_PHY_ADDR     0x01
563 #endif
564
565
566 #ifdef CONFIG_FMAN_ENET
567 #define CONFIG_MII              /* MII PHY management */
568 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
569 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
570 #endif
571
572 /*
573  * SATA
574  */
575 #ifdef CONFIG_FSL_SATA_V2
576 #define CONFIG_LIBATA
577 #define CONFIG_FSL_SATA
578 #define CONFIG_SYS_SATA_MAX_DEVICE      2
579 #define CONFIG_SATA1
580 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
581 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
582 #define CONFIG_SATA2
583 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
584 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
585 #define CONFIG_LBA48
586 #define CONFIG_CMD_SATA
587 #define CONFIG_DOS_PARTITION
588 #define CONFIG_CMD_EXT2
589 #endif
590
591 /*
592  * USB
593  */
594 #ifdef CONFIG_USB_EHCI
595 #define CONFIG_CMD_USB
596 #define CONFIG_USB_STORAGE
597 #define CONFIG_USB_EHCI_FSL
598 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
599 #define CONFIG_CMD_EXT2
600 #define CONFIG_HAS_FSL_DR_USB
601 #endif
602
603 /*
604  * SDHC
605  */
606 #ifdef CONFIG_MMC
607 #define CONFIG_CMD_MMC
608 #define CONFIG_FSL_ESDHC
609 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
610 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
611 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
612 #define CONFIG_GENERIC_MMC
613 #define CONFIG_CMD_EXT2
614 #define CONFIG_CMD_FAT
615 #define CONFIG_DOS_PARTITION
616 #endif
617
618 /*
619  * Environment
620  */
621
622 /*
623  * Command line configuration.
624  */
625 #include <config_cmd_default.h>
626
627 #define CONFIG_CMD_DHCP
628 #define CONFIG_CMD_ELF
629 #define CONFIG_CMD_MII
630 #define CONFIG_CMD_I2C
631 #define CONFIG_CMD_PING
632 #define CONFIG_CMD_ECHO
633 #define CONFIG_CMD_SETEXPR
634 #define CONFIG_CMD_REGINFO
635 #define CONFIG_CMD_BDI
636
637 #ifdef CONFIG_PCI
638 #define CONFIG_CMD_PCI
639 #define CONFIG_CMD_NET
640 #endif
641
642 /*
643  * Miscellaneous configurable options
644  */
645 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
646 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
647 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
648 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
649 #define CONFIG_SYS_PROMPT       "=> "     /* Monitor Command Prompt */
650 #ifdef CONFIG_CMD_KGDB
651 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
652 #else
653 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
654 #endif
655 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
656 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
657 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
658 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks*/
659
660 /*
661  * For booting Linux, the board info and command line data
662  * have to be in the first 64 MB of memory, since this is
663  * the maximum mapped by the Linux kernel during initialization.
664  */
665 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
666 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
667
668 #ifdef CONFIG_CMD_KGDB
669 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
670 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
671 #endif
672
673 /*
674  * Environment Configuration
675  */
676 #define CONFIG_ROOTPATH  "/opt/nfsroot"
677 #define CONFIG_BOOTFILE  "uImage"
678 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
679
680 /* default location for tftp and bootm */
681 #define CONFIG_LOADADDR         1000000
682 #define CONFIG_BAUDRATE         115200
683 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
684 #define __USB_PHY_TYPE          utmi
685
686 #define CONFIG_EXTRA_ENV_SETTINGS                               \
687         "hwconfig=fsl_ddr:"                                     \
688         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
689         "bank_intlv=auto;"                                      \
690         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
691         "netdev=eth0\0"                                         \
692         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
693         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
694         "tftpflash=tftpboot $loadaddr $uboot && "               \
695         "protect off $ubootaddr +$filesize && "                 \
696         "erase $ubootaddr +$filesize && "                       \
697         "cp.b $loadaddr $ubootaddr $filesize && "               \
698         "protect on $ubootaddr +$filesize && "                  \
699         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
700         "consoledev=ttyS0\0"                                    \
701         "ramdiskaddr=2000000\0"                                 \
702         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
703         "fdtaddr=c00000\0"                                      \
704         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
705         "bdev=sda3\0"                                           \
706         "c=ffe\0"
707
708 /*
709  * For emulation this causes u-boot to jump to the start of the
710  * proof point app code automatically
711  */
712 #define CONFIG_PROOF_POINTS                             \
713         "setenv bootargs root=/dev/$bdev rw "           \
714         "console=$consoledev,$baudrate $othbootargs;"   \
715         "cpu 1 release 0x29000000 - - -;"               \
716         "cpu 2 release 0x29000000 - - -;"               \
717         "cpu 3 release 0x29000000 - - -;"               \
718         "cpu 4 release 0x29000000 - - -;"               \
719         "cpu 5 release 0x29000000 - - -;"               \
720         "cpu 6 release 0x29000000 - - -;"               \
721         "cpu 7 release 0x29000000 - - -;"               \
722         "go 0x29000000"
723
724 #define CONFIG_HVBOOT                           \
725         "setenv bootargs config-addr=0x60000000; "      \
726         "bootm 0x01000000 - 0x00f00000"
727
728 #define CONFIG_ALU                              \
729         "setenv bootargs root=/dev/$bdev rw "           \
730         "console=$consoledev,$baudrate $othbootargs;"   \
731         "cpu 1 release 0x01000000 - - -;"               \
732         "cpu 2 release 0x01000000 - - -;"               \
733         "cpu 3 release 0x01000000 - - -;"               \
734         "cpu 4 release 0x01000000 - - -;"               \
735         "cpu 5 release 0x01000000 - - -;"               \
736         "cpu 6 release 0x01000000 - - -;"               \
737         "cpu 7 release 0x01000000 - - -;"               \
738         "go 0x01000000"
739
740 #define CONFIG_LINUX                            \
741         "setenv bootargs root=/dev/ram rw "             \
742         "console=$consoledev,$baudrate $othbootargs;"   \
743         "setenv ramdiskaddr 0x02000000;"                \
744         "setenv fdtaddr 0x00c00000;"                    \
745         "setenv loadaddr 0x1000000;"                    \
746         "bootm $loadaddr $ramdiskaddr $fdtaddr"
747
748 #define CONFIG_HDBOOT                                   \
749         "setenv bootargs root=/dev/$bdev rw "           \
750         "console=$consoledev,$baudrate $othbootargs;"   \
751         "tftp $loadaddr $bootfile;"                     \
752         "tftp $fdtaddr $fdtfile;"                       \
753         "bootm $loadaddr - $fdtaddr"
754
755 #define CONFIG_NFSBOOTCOMMAND                   \
756         "setenv bootargs root=/dev/nfs rw "     \
757         "nfsroot=$serverip:$rootpath "          \
758         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
759         "console=$consoledev,$baudrate $othbootargs;"   \
760         "tftp $loadaddr $bootfile;"             \
761         "tftp $fdtaddr $fdtfile;"               \
762         "bootm $loadaddr - $fdtaddr"
763
764 #define CONFIG_RAMBOOTCOMMAND                           \
765         "setenv bootargs root=/dev/ram rw "             \
766         "console=$consoledev,$baudrate $othbootargs;"   \
767         "tftp $ramdiskaddr $ramdiskfile;"               \
768         "tftp $loadaddr $bootfile;"                     \
769         "tftp $fdtaddr $fdtfile;"                       \
770         "bootm $loadaddr $ramdiskaddr $fdtaddr"
771
772 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
773
774 #ifdef CONFIG_SECURE_BOOT
775 #include <asm/fsl_secure_boot.h>
776 #undef CONFIG_CMD_USB
777 #endif
778
779 #endif  /* __T2080RDB_H */