at91sam9263ek: add mmc support
[karo-tx-uboot.git] / include / configs / at91sam9263ek.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9263EK board.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15  * SoC must be defined first, before hardware.h is included.
16  * In this case SoC is defined in boards.cfg.
17  */
18 #include <asm/hardware.h>
19
20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
21 #define CONFIG_SYS_TEXT_BASE            0x21F00000
22 #else
23 #define CONFIG_SYS_TEXT_BASE            0x0000000
24 #endif
25
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_MAIN_CLOCK      16367660 /* 16.367 MHz crystal */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
29
30 #define CONFIG_AT91SAM9263EK    1       /* It's an AT91SAM9263EK Board */
31
32 #define CONFIG_ARCH_CPU_INIT
33
34 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36 #define CONFIG_INITRD_TAG       1
37
38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
39 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #else
41 #define CONFIG_SYS_USE_NORFLASH
42 #endif
43
44 #define CONFIG_BOARD_EARLY_INIT_F
45
46 #define CONFIG_DISPLAY_CPUINFO
47
48 #define CONFIG_CMD_BOOTZ
49 #define CONFIG_OF_LIBFDT
50
51 /*
52  * Hardware drivers
53  */
54 #define CONFIG_ATMEL_LEGACY
55 #define CONFIG_AT91_GPIO                1
56 #define CONFIG_AT91_GPIO_PULLUP         1
57
58 /* serial console */
59 #define CONFIG_ATMEL_USART
60 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
61 #define CONFIG_USART_ID                 ATMEL_ID_SYS
62 #define CONFIG_BAUDRATE                 115200
63
64 /* LCD */
65 #define CONFIG_LCD                      1
66 #define LCD_BPP                         LCD_COLOR8
67 #define CONFIG_LCD_LOGO                 1
68 #undef LCD_TEST_PATTERN
69 #define CONFIG_LCD_INFO                 1
70 #define CONFIG_LCD_INFO_BELOW_LOGO      1
71 #define CONFIG_SYS_WHITE_ON_BLACK       1
72 #define CONFIG_ATMEL_LCD                1
73 #define CONFIG_ATMEL_LCD_BGR555         1
74 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
75
76 /* LED */
77 #define CONFIG_AT91_LED
78 #define CONFIG_RED_LED          AT91_PIN_PB7    /* the power led */
79 #define CONFIG_GREEN_LED        AT91_PIN_PB8    /* the user1 led */
80 #define CONFIG_YELLOW_LED       AT91_PIN_PC29   /* the user2 led */
81
82 #define CONFIG_BOOTDELAY        3
83
84 /*
85  * BOOTP options
86  */
87 #define CONFIG_BOOTP_BOOTFILESIZE       1
88 #define CONFIG_BOOTP_BOOTPATH           1
89 #define CONFIG_BOOTP_GATEWAY            1
90 #define CONFIG_BOOTP_HOSTNAME           1
91
92 /*
93  * Command line configuration.
94  */
95 #include <config_cmd_default.h>
96 #undef CONFIG_CMD_BDI
97 #undef CONFIG_CMD_FPGA
98 #undef CONFIG_CMD_IMI
99 #undef CONFIG_CMD_IMLS
100 #undef CONFIG_CMD_LOADS
101 #undef CONFIG_CMD_SOURCE
102
103 #define CONFIG_CMD_PING         1
104 #define CONFIG_CMD_DHCP         1
105 #define CONFIG_CMD_NAND         1
106 #define CONFIG_CMD_MMC
107 #define CONFIG_CMD_USB          1
108
109 /* SDRAM */
110 #define CONFIG_NR_DRAM_BANKS            1
111 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS1
112 #define CONFIG_SYS_SDRAM_SIZE           0x04000000
113
114 #define CONFIG_SYS_INIT_SP_ADDR \
115         (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
116
117 /* DataFlash */
118 #define CONFIG_ATMEL_DATAFLASH_SPI
119 #define CONFIG_HAS_DATAFLASH            1
120 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
121 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
122 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
123 #define AT91_SPI_CLK                    15000000
124 #define DATAFLASH_TCSS                  (0x1a << 16)
125 #define DATAFLASH_TCHS                  (0x1 << 24)
126
127 /* MMC */
128 #ifdef CONFIG_CMD_MMC
129 #define CONFIG_MMC
130 #define CONFIG_GENERIC_MMC
131 #define CONFIG_GENERIC_ATMEL_MCI
132 #endif
133
134 /* FAT */
135 #ifdef CONFIG_CMD_FAT
136 #define CONFIG_DOS_PARTITION
137 #endif
138
139 /* NOR flash, if populated */
140 #ifdef CONFIG_SYS_USE_NORFLASH
141 #define CONFIG_SYS_FLASH_CFI                    1
142 #define CONFIG_FLASH_CFI_DRIVER                 1
143 #define PHYS_FLASH_1                            0x10000000
144 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
145 #define CONFIG_SYS_MAX_FLASH_SECT               256
146 #define CONFIG_SYS_MAX_FLASH_BANKS              1
147
148 #define CONFIG_SYS_MONITOR_SEC  1:0-3
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
150 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
151 #define CONFIG_ENV_IS_IN_FLASH  1
152 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x007E0000)
153 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
154
155 /* Address and size of Primary Environment Sector */
156 #define CONFIG_ENV_SIZE         0x10000
157
158 #define CONFIG_EXTRA_ENV_SETTINGS       \
159         "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
160         "update=" \
161                 "protect off ${monitor_base} +${filesize};" \
162                 "erase ${monitor_base} +${filesize};" \
163                 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
164                 "protect on ${monitor_base} +${filesize}\0"
165
166 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
167 #define MASTER_PLL_MUL          171
168 #define MASTER_PLL_DIV          14
169 #define MASTER_PLL_OUT          3
170
171 /* clocks */
172 #define CONFIG_SYS_MOR_VAL                                              \
173                 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
174 #define CONFIG_SYS_PLLAR_VAL                                    \
175         (AT91_PMC_PLLAR_29 |                                    \
176         AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
177         AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
178         AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
179         AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
180
181 /* PCK/2 = MCK Master Clock from PLLA */
182 #define CONFIG_SYS_MCKR1_VAL            \
183         (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
184          AT91_PMC_MCKR_MDIV_2)
185
186 /* PCK/2 = MCK Master Clock from PLLA */
187 #define CONFIG_SYS_MCKR2_VAL            \
188         (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
189         AT91_PMC_MCKR_MDIV_2)
190
191 /* define PDC[31:16] as DATA[31:16] */
192 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
193 /* no pull-up for D[31:16] */
194 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
195 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
196 #define CONFIG_SYS_MATRIX_EBICSA_VAL                                    \
197         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
198          AT91_MATRIX_CSA_EBI_CS1A)
199
200 /* SDRAM */
201 /* SDRAMC_MR Mode register */
202 #define CONFIG_SYS_SDRC_MR_VAL1         0
203 /* SDRAMC_TR - Refresh Timer register */
204 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
205 /* SDRAMC_CR - Configuration register*/
206 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
207                 (AT91_SDRAMC_NC_9 |                                             \
208                  AT91_SDRAMC_NR_13 |                                            \
209                  AT91_SDRAMC_NB_4 |                                             \
210                  AT91_SDRAMC_CAS_3 |                                            \
211                  AT91_SDRAMC_DBW_32 |                                           \
212                  (1 <<  8) |            /* Write Recovery Delay */              \
213                  (7 << 12) |            /* Row Cycle Delay */                   \
214                  (2 << 16) |            /* Row Precharge Delay */               \
215                  (2 << 20) |            /* Row to Column Delay */               \
216                  (5 << 24) |            /* Active to Precharge Delay */         \
217                  (1 << 28))             /* Exit Self Refresh to Active Delay */
218
219 /* Memory Device Register -> SDRAM */
220 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
221 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
222 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
223 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
224 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
225 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
226 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
227 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
228 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
229 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
230 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
231 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
232 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
233 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
234 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
235 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
236 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
237 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
238
239 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
240 #define CONFIG_SYS_SMC0_SETUP0_VAL                              \
241         (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
242          AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
243 #define CONFIG_SYS_SMC0_PULSE0_VAL                              \
244         (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
245          AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
246 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
247         (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
248 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
249         (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
250          AT91_SMC_MODE_DBW_16 |                                 \
251          AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
252
253 /* user reset enable */
254 #define CONFIG_SYS_RSTC_RMR_VAL                 \
255                 (AT91_RSTC_KEY |                \
256                 AT91_RSTC_MR_URSTEN |           \
257                 AT91_RSTC_MR_ERSTL(15))
258
259 /* Disable Watchdog */
260 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
261                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
262                  AT91_WDT_MR_WDV(0xfff) |                       \
263                  AT91_WDT_MR_WDDIS |                            \
264                  AT91_WDT_MR_WDD(0xfff))
265
266 #endif
267
268 #else
269 #define CONFIG_SYS_NO_FLASH                     1
270 #endif
271
272 /* NAND flash */
273 #ifdef CONFIG_CMD_NAND
274 #define CONFIG_NAND_ATMEL
275 #define CONFIG_SYS_MAX_NAND_DEVICE              1
276 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
277 #define CONFIG_SYS_NAND_DBW_8                   1
278 /* our ALE is AD21 */
279 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
280 /* our CLE is AD22 */
281 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
282 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PD15
283 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PA22
284 #endif
285
286 /* Ethernet */
287 #define CONFIG_MACB                     1
288 #define CONFIG_RMII                     1
289 #define CONFIG_NET_RETRY_COUNT          20
290 #define CONFIG_RESET_PHY_R              1
291 #define CONFIG_AT91_WANTS_COMMON_PHY
292
293 /* USB */
294 #define CONFIG_USB_ATMEL
295 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
296 #define CONFIG_USB_OHCI_NEW             1
297 #define CONFIG_DOS_PARTITION            1
298 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
299 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
300 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
301 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
302 #define CONFIG_USB_STORAGE              1
303 #define CONFIG_CMD_FAT                  1
304
305 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
306
307 #define CONFIG_SYS_MEMTEST_START                CONFIG_SYS_SDRAM_BASE
308 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
309
310 #ifdef CONFIG_SYS_USE_DATAFLASH
311
312 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
313 #define CONFIG_ENV_IS_IN_DATAFLASH      1
314 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
315 #define CONFIG_ENV_OFFSET               0x4200
316 #define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
317 #define CONFIG_ENV_SIZE         0x4200
318 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0084000 0x22000000 0x210000; bootm"
319 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
320                                 "root=/dev/mtdblock0 " \
321                                 "mtdparts=atmel_nand:-(root) "\
322                                 "rw rootfstype=jffs2"
323
324 #elif CONFIG_SYS_USE_NANDFLASH
325
326 /* bootstrap + u-boot + env + linux in nandflash */
327 #define CONFIG_ENV_IS_IN_NAND           1
328 #define CONFIG_ENV_OFFSET               0xc0000
329 #define CONFIG_ENV_OFFSET_REDUND        0x100000
330 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
331 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0x200000 0x300000; bootm"
332 #define CONFIG_BOOTARGS                                                 \
333         "console=ttyS0,115200 earlyprintk "                             \
334         "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"          \
335         "256k(env),256k(env_redundant),256k(spare),"                    \
336         "512k(dtb),6M(kernel)ro,-(rootfs) "                             \
337         "root=/dev/mtdblock7 rw rootfstype=jffs2"
338 #endif
339
340 #define CONFIG_SYS_PROMPT               "U-Boot> "
341 #define CONFIG_SYS_CBSIZE               256
342 #define CONFIG_SYS_MAXARGS              16
343 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
344 #define CONFIG_SYS_LONGHELP             1
345 #define CONFIG_CMDLINE_EDITING          1
346 #define CONFIG_AUTO_COMPLETE
347 #define CONFIG_SYS_HUSH_PARSER
348
349 /*
350  * Size of malloc() pool
351  */
352 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
353
354 #endif