ARM: pxa: Fix CONFIG_SYS_HZ on PXA
[karo-tx-uboot.git] / include / configs / balloon3.h
1 /*
2  * Balloon3 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Board Configuration Options
14  */
15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
16 #define CONFIG_BALLOON3         1       /* Balloon3 board */
17
18 /*
19  * Environment settings
20  */
21 #define CONFIG_ENV_OVERWRITE
22 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
23 #define CONFIG_ARCH_CPU_INIT
24 #define CONFIG_BOOTCOMMAND                                              \
25         "fpga load 0x0 0x50000 0x62638; "                               \
26         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
27                 "bootm 0xa4000000; "                                    \
28         "fi; "                                                          \
29         "bootm 0xd0000;"
30 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS2,115200"
31 #define CONFIG_TIMESTAMP
32 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
33 #define CONFIG_CMDLINE_TAG
34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_SYS_TEXT_BASE            0x0
36 #define CONFIG_LZMA                     /* LZMA compression support */
37
38 /*
39  * Serial Console Configuration
40  */
41 #define CONFIG_PXA_SERIAL
42 #define CONFIG_STUART                   1
43 #define CONFIG_CONS_INDEX               2
44 #define CONFIG_BAUDRATE                 115200
45
46 /*
47  * Bootloader Components Configuration
48  */
49 #include <config_cmd_default.h>
50
51 #undef  CONFIG_CMD_NET
52 #undef  CONFIG_CMD_NFS
53 #undef  CONFIG_CMD_ENV
54 #undef  CONFIG_CMD_IMLS
55 #define CONFIG_CMD_USB
56 #define CONFIG_CMD_FPGA
57 #undef  CONFIG_LCD
58
59 /*
60  * KGDB
61  */
62 #ifdef  CONFIG_CMD_KGDB
63 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
64 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
65 #endif
66
67 /*
68  * HUSH Shell Configuration
69  */
70 #define CONFIG_SYS_HUSH_PARSER          1
71
72 #define CONFIG_SYS_LONGHELP
73 #ifdef  CONFIG_SYS_HUSH_PARSER
74 #define CONFIG_SYS_PROMPT               "$ "
75 #else
76 #endif
77 #define CONFIG_SYS_CBSIZE               256
78 #define CONFIG_SYS_PBSIZE               \
79         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
80 #define CONFIG_SYS_MAXARGS              16
81 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
82 #define CONFIG_SYS_DEVICE_NULLDEV       1
83
84 /*
85  * Clock Configuration
86  */
87 #undef  CONFIG_SYS_CLKS_IN_HZ
88 #define CONFIG_SYS_HZ                   1000
89 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
90
91 /*
92  * DRAM Map
93  */
94 #define CONFIG_NR_DRAM_BANKS            3               /* 2 banks of DRAM */
95 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
96 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
97 #define PHYS_SDRAM_2                    0xb0000000      /* SDRAM Bank #2 */
98 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
99 #define PHYS_SDRAM_3                    0x80000000      /* SDRAM Bank #2 */
100 #define PHYS_SDRAM_3_SIZE               0x08000000      /* 128 MB */
101
102 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
103 #define CONFIG_SYS_DRAM_SIZE            0x18000000      /* 384 MB DRAM */
104
105 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
106 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
107
108 #define CONFIG_SYS_LOAD_ADDR            0xa1000000
109
110 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
111 #define CONFIG_SYS_INIT_SP_ADDR         \
112         (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
113
114 /*
115  * NOR FLASH
116  */
117 #ifdef  CONFIG_CMD_FLASH
118 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
119 #define PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
120 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
121
122 #define CONFIG_SYS_FLASH_CFI
123 #define CONFIG_FLASH_CFI_DRIVER         1
124 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
125
126 #define CONFIG_SYS_MAX_FLASH_BANKS      1
127 #define CONFIG_SYS_MAX_FLASH_SECT       256
128
129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
130
131 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
132 #define CONFIG_SYS_FLASH_WRITE_TOUT     240000
133 #define CONFIG_SYS_FLASH_LOCK_TOUT      240000
134 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
135 #define CONFIG_SYS_FLASH_PROTECTION
136 #define CONFIG_ENV_IS_IN_FLASH
137 #else
138 #define CONFIG_SYS_NO_FLASH
139 #define CONFIG_SYS_ENV_IS_NOWHERE
140 #endif
141
142 #define CONFIG_SYS_MONITOR_BASE         0x000000
143 #define CONFIG_SYS_MONITOR_LEN          0x40000
144
145 #define CONFIG_ENV_SIZE                 0x2000
146 #define CONFIG_ENV_ADDR                 0x40000
147 #define CONFIG_ENV_SECT_SIZE            0x10000
148
149 /*
150  * GPIO settings
151  */
152 #define CONFIG_SYS_GPSR0_VAL    0x307dc7fd
153 #define CONFIG_SYS_GPSR1_VAL    0x03cffa4e
154 #define CONFIG_SYS_GPSR2_VAL    0x7131c000
155 #define CONFIG_SYS_GPSR3_VAL    0x01e1f3ff
156
157 #define CONFIG_SYS_GPCR0_VAL    0x0
158 #define CONFIG_SYS_GPCR1_VAL    0x0
159 #define CONFIG_SYS_GPCR2_VAL    0x0
160 #define CONFIG_SYS_GPCR3_VAL    0x0
161
162 #define CONFIG_SYS_GPDR0_VAL    0xc0f98e02
163 #define CONFIG_SYS_GPDR1_VAL    0xfcffa8b7
164 #define CONFIG_SYS_GPDR2_VAL    0x22e3ffff
165 #define CONFIG_SYS_GPDR3_VAL    0x000201fe
166
167 #define CONFIG_SYS_GAFR0_L_VAL  0x96c00000
168 #define CONFIG_SYS_GAFR0_U_VAL  0xa5e5459b
169 #define CONFIG_SYS_GAFR1_L_VAL  0x699b759a
170 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a5aa
171 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
172 #define CONFIG_SYS_GAFR2_U_VAL  0x01f9a6aa
173 #define CONFIG_SYS_GAFR3_L_VAL  0x54510003
174 #define CONFIG_SYS_GAFR3_U_VAL  0x00001599
175
176 #define CONFIG_SYS_PSSR_VAL     0x30
177
178 /*
179  * Clock settings
180  */
181 #define CONFIG_SYS_CKEN         0xffffffff
182 #define CONFIG_SYS_CCCR         0x00000290
183
184 /*
185  * Memory settings
186  */
187 #define CONFIG_SYS_MSC0_VAL     0x7ff07ff8
188 #define CONFIG_SYS_MSC1_VAL     0x7ff07ff0
189 #define CONFIG_SYS_MSC2_VAL     0x74a42491
190 #define CONFIG_SYS_MDCNFG_VAL   0x89d309d3
191 #define CONFIG_SYS_MDREFR_VAL   0x001d8018
192 #define CONFIG_SYS_MDMRS_VAL    0x00220022
193 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
194 #define CONFIG_SYS_SXCNFG_VAL   0x00000000
195 #define CONFIG_SYS_MEM_BUF_IMP  0x0f
196
197 /*
198  * PCMCIA and CF Interfaces
199  */
200 #define CONFIG_SYS_MECR_VAL     0x00000000
201 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
202 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
203 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
204 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
205 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
206 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
207
208 /*
209  * LCD
210  */
211 #ifdef  CONFIG_LCD
212 #define CONFIG_BALLOON3LCD
213 #define CONFIG_VIDEO_LOGO
214 #define CONFIG_CMD_BMP
215 #define CONFIG_SPLASH_SCREEN
216 #define CONFIG_SPLASH_SCREEN_ALIGN
217 #define CONFIG_VIDEO_BMP_GZIP
218 #define CONFIG_VIDEO_BMP_RLE8
219 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
220 #endif
221
222 /*
223  * USB
224  */
225 #ifdef  CONFIG_CMD_USB
226 #define CONFIG_USB_OHCI_NEW
227 #define CONFIG_SYS_USB_OHCI_CPU_INIT
228 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
229 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
230 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
231 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "balloon3"
232 #define CONFIG_USB_STORAGE
233 #define CONFIG_DOS_PARTITION
234 #define CONFIG_CMD_FAT
235 #define CONFIG_CMD_EXT2
236 #endif
237
238 /*
239  * FPGA
240  */
241 #ifdef  CONFIG_CMD_FPGA
242 #define CONFIG_FPGA
243 #define CONFIG_FPGA_XILINX
244 #define CONFIG_FPGA_SPARTAN3
245 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
246 #define CONFIG_SYS_FPGA_WAIT    1000
247 #define CONFIG_MAX_FPGA_DEVICES 1
248 #endif
249
250 #endif  /* __CONFIG_H */