72432e4bde5291779e74cecfe84956708b000b8a
[karo-tx-uboot.git] / include / configs / corenet_ds.h
1 /*
2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * Corenet DS style board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include "../board/freescale/common/ics307_clk.h"
14
15 #ifdef CONFIG_RAMBOOT_PBL
16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
19 #if defined(CONFIG_P3041DS)
20 #define CONFIG_SYS_FSL_PBL_RCW \
21                         $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
22 #elif defined(CONFIG_P4080DS)
23 #define CONFIG_SYS_FSL_PBL_RCW \
24                         $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
25 #elif defined(CONFIG_P5020DS)
26 #define CONFIG_SYS_FSL_PBL_RCW \
27                         $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
28 #elif defined(CONFIG_P5040DS)
29 #define CONFIG_SYS_FSL_PBL_RCW \
30                         $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
31 #endif
32 #endif
33
34 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
35 /* Set 1M boot space */
36 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
37 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
38                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
39 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
40 #define CONFIG_SYS_NO_FLASH
41 #endif
42
43 /* High Level Configuration Options */
44 #define CONFIG_BOOKE
45 #define CONFIG_E500                     /* BOOKE e500 family */
46 #define CONFIG_E500MC                   /* BOOKE e500mc family */
47 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
48 #define CONFIG_MP                       /* support multiple processors */
49
50 #ifndef CONFIG_SYS_TEXT_BASE
51 #define CONFIG_SYS_TEXT_BASE    0xeff40000
52 #endif
53
54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
55 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
56 #endif
57
58 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
59 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
60 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
61 #define CONFIG_PCI                      /* Enable PCI/PCIE */
62 #define CONFIG_PCIE1                    /* PCIE controler 1 */
63 #define CONFIG_PCIE2                    /* PCIE controler 2 */
64 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
66
67 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
68
69 #define CONFIG_ENV_OVERWRITE
70
71 #ifdef CONFIG_SYS_NO_FLASH
72 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
73 #define CONFIG_ENV_IS_NOWHERE
74 #endif
75 #else
76 #define CONFIG_FLASH_CFI_DRIVER
77 #define CONFIG_SYS_FLASH_CFI
78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
79 #endif
80
81 #if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS              0
85 #define CONFIG_ENV_SPI_CS               0
86 #define CONFIG_ENV_SPI_MAX_HZ           10000000
87 #define CONFIG_ENV_SPI_MODE             0
88 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
89 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE            0x10000
91 #elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_FSL_FIXED_MMC_LOCATION
95 #define CONFIG_SYS_MMC_ENV_DEV          0
96 #define CONFIG_ENV_SIZE                 0x2000
97 #define CONFIG_ENV_OFFSET               (512 * 1658)
98 #elif defined(CONFIG_NAND)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_NAND
101 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
102 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
104 #define CONFIG_ENV_IS_IN_REMOTE
105 #define CONFIG_ENV_ADDR         0xffe20000
106 #define CONFIG_ENV_SIZE         0x2000
107 #elif defined(CONFIG_ENV_IS_NOWHERE)
108 #define CONFIG_ENV_SIZE         0x2000
109 #else
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
112 #define CONFIG_ENV_SIZE         0x2000
113 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
114 #endif
115
116 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
117
118 /*
119  * These can be toggled for performance analysis, otherwise use default.
120  */
121 #define CONFIG_SYS_CACHE_STASHING
122 #define CONFIG_BACKSIDE_L2_CACHE
123 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
124 #define CONFIG_BTB                      /* toggle branch predition */
125 #define CONFIG_DDR_ECC
126 #ifdef CONFIG_DDR_ECC
127 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
128 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
129 #endif
130
131 #define CONFIG_ENABLE_36BIT_PHYS
132
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_ADDR_MAP
135 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
136 #endif
137
138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
139 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END          0x00400000
141 #define CONFIG_SYS_ALT_MEMTEST
142 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
143
144 /*
145  *  Config the L3 Cache as L3 SRAM
146  */
147 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
148 #ifdef CONFIG_PHYS_64BIT
149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
150 #else
151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
152 #endif
153 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
155
156 #ifdef CONFIG_PHYS_64BIT
157 #define CONFIG_SYS_DCSRBAR              0xf0000000
158 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
159 #endif
160
161 /* EEPROM */
162 #define CONFIG_ID_EEPROM
163 #define CONFIG_SYS_I2C_EEPROM_NXID
164 #define CONFIG_SYS_EEPROM_BUS_NUM       0
165 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
167
168 /*
169  * DDR Setup
170  */
171 #define CONFIG_VERY_BIG_RAM
172 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
173 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
174
175 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
176 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
177
178 #define CONFIG_DDR_SPD
179 #define CONFIG_SYS_FSL_DDR3
180
181 #define CONFIG_SYS_SPD_BUS_NUM  1
182 #define SPD_EEPROM_ADDRESS1     0x51
183 #define SPD_EEPROM_ADDRESS2     0x52
184 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
185 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
186
187 /*
188  * Local Bus Definitions
189  */
190
191 /* Set the local bus clock 1/8 of platform clock */
192 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
193
194 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
195 #ifdef CONFIG_PHYS_64BIT
196 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
197 #else
198 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
199 #endif
200
201 #define CONFIG_SYS_FLASH_BR_PRELIM \
202                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
203                  | BR_PS_16 | BR_V)
204 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
205                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
206
207 #define CONFIG_SYS_BR1_PRELIM \
208         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
209 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
210
211 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
212 #ifdef CONFIG_PHYS_64BIT
213 #define PIXIS_BASE_PHYS         0xfffdf0000ull
214 #else
215 #define PIXIS_BASE_PHYS         PIXIS_BASE
216 #endif
217
218 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
219 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
220
221 #define PIXIS_LBMAP_SWITCH      7
222 #define PIXIS_LBMAP_MASK        0xf0
223 #define PIXIS_LBMAP_SHIFT       4
224 #define PIXIS_LBMAP_ALTBANK     0x40
225
226 #define CONFIG_SYS_FLASH_QUIET_TEST
227 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
228
229 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
230 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
231 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
233
234 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
235
236 #if defined(CONFIG_RAMBOOT_PBL)
237 #define CONFIG_SYS_RAMBOOT
238 #endif
239
240 /* Nand Flash */
241 #ifdef CONFIG_NAND_FSL_ELBC
242 #define CONFIG_SYS_NAND_BASE            0xffa00000
243 #ifdef CONFIG_PHYS_64BIT
244 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
245 #else
246 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
247 #endif
248
249 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
250 #define CONFIG_SYS_MAX_NAND_DEVICE      1
251 #define CONFIG_MTD_NAND_VERIFY_WRITE
252 #define CONFIG_CMD_NAND
253 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
254
255 /* NAND flash config */
256 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
257                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
258                                | BR_PS_8               /* Port Size = 8 bit */ \
259                                | BR_MS_FCM             /* MSEL = FCM */ \
260                                | BR_V)                 /* valid */
261 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
262                                | OR_FCM_PGS            /* Large Page*/ \
263                                | OR_FCM_CSCT \
264                                | OR_FCM_CST \
265                                | OR_FCM_CHT \
266                                | OR_FCM_SCY_1 \
267                                | OR_FCM_TRLX \
268                                | OR_FCM_EHTR)
269
270 #ifdef CONFIG_NAND
271 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
272 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
273 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
274 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
275 #else
276 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
277 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
278 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
279 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
280 #endif
281 #else
282 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
283 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
284 #endif /* CONFIG_NAND_FSL_ELBC */
285
286 #define CONFIG_SYS_FLASH_EMPTY_INFO
287 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
288 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
289
290 #define CONFIG_BOARD_EARLY_INIT_F
291 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
292 #define CONFIG_MISC_INIT_R
293
294 #define CONFIG_HWCONFIG
295
296 /* define to use L1 as initial stack */
297 #define CONFIG_L1_INIT_RAM
298 #define CONFIG_SYS_INIT_RAM_LOCK
299 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
300 #ifdef CONFIG_PHYS_64BIT
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
303 /* The assembler doesn't like typecast */
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
305         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
306           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
307 #else
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
311 #endif
312 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
313
314 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
315 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
316
317 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
318 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
319
320 /* Serial Port - controlled on board with jumper J8
321  * open - index 2
322  * shorted - index 1
323  */
324 #define CONFIG_CONS_INDEX       1
325 #define CONFIG_SYS_NS16550
326 #define CONFIG_SYS_NS16550_SERIAL
327 #define CONFIG_SYS_NS16550_REG_SIZE     1
328 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
329
330 #define CONFIG_SYS_BAUDRATE_TABLE       \
331         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
332
333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
335 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
336 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
337
338 /* Use the HUSH parser */
339 #define CONFIG_SYS_HUSH_PARSER
340
341 /* pass open firmware flat tree */
342 #define CONFIG_OF_LIBFDT
343 #define CONFIG_OF_BOARD_SETUP
344 #define CONFIG_OF_STDOUT_VIA_ALIAS
345
346 /* new uImage format support */
347 #define CONFIG_FIT
348 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
349
350 /* I2C */
351 #define CONFIG_SYS_I2C
352 #define CONFIG_SYS_I2C_FSL
353 #define CONFIG_SYS_FSL_I2C_SPEED        400000
354 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
355 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
356 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
357 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
358 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
359
360 /*
361  * RapidIO
362  */
363 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
364 #ifdef CONFIG_PHYS_64BIT
365 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
366 #else
367 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
368 #endif
369 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
370
371 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
372 #ifdef CONFIG_PHYS_64BIT
373 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
374 #else
375 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
376 #endif
377 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
378
379 /*
380  * for slave u-boot IMAGE instored in master memory space,
381  * PHYS must be aligned based on the SIZE
382  */
383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000        /* 512K */
386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
387 /*
388  * for slave UCODE and ENV instored in master memory space,
389  * PHYS must be aligned based on the SIZE
390  */
391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
392 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
393 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
394
395 /* slave core release by master*/
396 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
397 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
398
399 /*
400  * SRIO_PCIE_BOOT - SLAVE
401  */
402 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
403 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
404 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
405                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
406 #endif
407
408 /*
409  * eSPI - Enhanced SPI
410  */
411 #define CONFIG_FSL_ESPI
412 #define CONFIG_SPI_FLASH
413 #define CONFIG_SPI_FLASH_SPANSION
414 #define CONFIG_CMD_SF
415 #define CONFIG_SF_DEFAULT_SPEED         10000000
416 #define CONFIG_SF_DEFAULT_MODE          0
417
418 /*
419  * General PCI
420  * Memory space is mapped 1-1, but I/O space must start from 0.
421  */
422
423 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
424 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
427 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
428 #else
429 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
430 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
431 #endif
432 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
433 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
434 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
437 #else
438 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
439 #endif
440 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
441
442 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
443 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
446 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
447 #else
448 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
449 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
450 #endif
451 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
452 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
453 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
456 #else
457 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
458 #endif
459 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
460
461 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
462 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
463 #ifdef CONFIG_PHYS_64BIT
464 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
465 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
466 #else
467 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
468 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
469 #endif
470 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
471 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
472 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
475 #else
476 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
477 #endif
478 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
479
480 /* controller 4, Base address 203000 */
481 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
482 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
483 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
484 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
485 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
486 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
487
488 /* Qman/Bman */
489 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
490 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
491 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
492 #ifdef CONFIG_PHYS_64BIT
493 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
494 #else
495 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
496 #endif
497 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
498 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
499 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
502 #else
503 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
504 #endif
505 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
506
507 #define CONFIG_SYS_DPAA_FMAN
508 #define CONFIG_SYS_DPAA_PME
509 /* Default address of microcode for the Linux Fman driver */
510 #if defined(CONFIG_SPIFLASH)
511 /*
512  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
513  * env, so we got 0x110000.
514  */
515 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
516 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
517 #elif defined(CONFIG_SDCARD)
518 /*
519  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
520  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
521  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
522  */
523 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
524 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1680)
525 #elif defined(CONFIG_NAND)
526 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
527 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
528 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
529 /*
530  * Slave has no ucode locally, it can fetch this from remote. When implementing
531  * in two corenet boards, slave's ucode could be stored in master's memory
532  * space, the address can be mapped from slave TLB->slave LAW->
533  * slave SRIO or PCIE outbound window->master inbound window->
534  * master LAW->the ucode address in master's memory space.
535  */
536 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
537 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
538 #else
539 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
540 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEFF00000
541 #endif
542 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
543 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
544
545 #ifdef CONFIG_SYS_DPAA_FMAN
546 #define CONFIG_FMAN_ENET
547 #define CONFIG_PHYLIB_10G
548 #define CONFIG_PHY_VITESSE
549 #define CONFIG_PHY_TERANETICS
550 #endif
551
552 #ifdef CONFIG_PCI
553 #define CONFIG_PCI_INDIRECT_BRIDGE
554 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
555 #define CONFIG_E1000
556
557 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
558 #define CONFIG_DOS_PARTITION
559 #endif  /* CONFIG_PCI */
560
561 /* SATA */
562 #ifdef CONFIG_FSL_SATA_V2
563 #define CONFIG_LIBATA
564 #define CONFIG_FSL_SATA
565
566 #define CONFIG_SYS_SATA_MAX_DEVICE      2
567 #define CONFIG_SATA1
568 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
569 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
570 #define CONFIG_SATA2
571 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
572 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
573
574 #define CONFIG_LBA48
575 #define CONFIG_CMD_SATA
576 #define CONFIG_DOS_PARTITION
577 #define CONFIG_CMD_EXT2
578 #endif
579
580 #ifdef CONFIG_FMAN_ENET
581 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
582 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
583 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
584 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
585 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
586
587 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
588 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
589 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
590 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
591 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
592
593 #define CONFIG_SYS_TBIPA_VALUE  8
594 #define CONFIG_MII              /* MII PHY management */
595 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
596 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
597 #endif
598
599 /*
600  * Environment
601  */
602 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
603 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
604
605 /*
606  * Command line configuration.
607  */
608 #include <config_cmd_default.h>
609
610 #define CONFIG_CMD_DHCP
611 #define CONFIG_CMD_ELF
612 #define CONFIG_CMD_ERRATA
613 #define CONFIG_CMD_GREPENV
614 #define CONFIG_CMD_IRQ
615 #define CONFIG_CMD_I2C
616 #define CONFIG_CMD_MII
617 #define CONFIG_CMD_PING
618 #define CONFIG_CMD_SETEXPR
619 #define CONFIG_CMD_REGINFO
620
621 #ifdef CONFIG_PCI
622 #define CONFIG_CMD_PCI
623 #define CONFIG_CMD_NET
624 #endif
625
626 /*
627 * USB
628 */
629 #define CONFIG_HAS_FSL_DR_USB
630 #define CONFIG_HAS_FSL_MPH_USB
631
632 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
633 #define CONFIG_CMD_USB
634 #define CONFIG_USB_STORAGE
635 #define CONFIG_USB_EHCI
636 #define CONFIG_USB_EHCI_FSL
637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
638 #define CONFIG_CMD_EXT2
639 #endif
640
641 #ifdef CONFIG_MMC
642 #define CONFIG_FSL_ESDHC
643 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645 #define CONFIG_CMD_MMC
646 #define CONFIG_GENERIC_MMC
647 #define CONFIG_CMD_EXT2
648 #define CONFIG_CMD_FAT
649 #define CONFIG_DOS_PARTITION
650 #endif
651
652 /*
653  * Miscellaneous configurable options
654  */
655 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
656 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
657 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
658 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
659 #ifdef CONFIG_CMD_KGDB
660 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
661 #else
662 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
663 #endif
664 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
665 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
666 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
667
668 /*
669  * For booting Linux, the board info and command line data
670  * have to be in the first 64 MB of memory, since this is
671  * the maximum mapped by the Linux kernel during initialization.
672  */
673 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
674 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
675
676 #ifdef CONFIG_CMD_KGDB
677 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
678 #endif
679
680 /*
681  * Environment Configuration
682  */
683 #define CONFIG_ROOTPATH         "/opt/nfsroot"
684 #define CONFIG_BOOTFILE         "uImage"
685 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
686
687 /* default location for tftp and bootm */
688 #define CONFIG_LOADADDR         1000000
689
690 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
691
692 #define CONFIG_BAUDRATE 115200
693
694 #ifdef CONFIG_P4080DS
695 #define __USB_PHY_TYPE  ulpi
696 #else
697 #define __USB_PHY_TYPE  utmi
698 #endif
699
700 #define CONFIG_EXTRA_ENV_SETTINGS                               \
701         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
702         "bank_intlv=cs0_cs1;"                                   \
703         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
704         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
705         "netdev=eth0\0"                                         \
706         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
707         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
708         "tftpflash=tftpboot $loadaddr $uboot && "               \
709         "protect off $ubootaddr +$filesize && "                 \
710         "erase $ubootaddr +$filesize && "                       \
711         "cp.b $loadaddr $ubootaddr $filesize && "               \
712         "protect on $ubootaddr +$filesize && "                  \
713         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
714         "consoledev=ttyS0\0"                                    \
715         "ramdiskaddr=2000000\0"                                 \
716         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
717         "fdtaddr=c00000\0"                                      \
718         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
719         "bdev=sda3\0"                                           \
720         "c=ffe\0"
721
722 #define CONFIG_HDBOOT                                   \
723         "setenv bootargs root=/dev/$bdev rw "           \
724         "console=$consoledev,$baudrate $othbootargs;"   \
725         "tftp $loadaddr $bootfile;"                     \
726         "tftp $fdtaddr $fdtfile;"                       \
727         "bootm $loadaddr - $fdtaddr"
728
729 #define CONFIG_NFSBOOTCOMMAND                   \
730         "setenv bootargs root=/dev/nfs rw "     \
731         "nfsroot=$serverip:$rootpath "          \
732         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
733         "console=$consoledev,$baudrate $othbootargs;"   \
734         "tftp $loadaddr $bootfile;"             \
735         "tftp $fdtaddr $fdtfile;"               \
736         "bootm $loadaddr - $fdtaddr"
737
738 #define CONFIG_RAMBOOTCOMMAND                           \
739         "setenv bootargs root=/dev/ram rw "             \
740         "console=$consoledev,$baudrate $othbootargs;"   \
741         "tftp $ramdiskaddr $ramdiskfile;"               \
742         "tftp $loadaddr $bootfile;"                     \
743         "tftp $fdtaddr $fdtfile;"                       \
744         "bootm $loadaddr $ramdiskaddr $fdtaddr"
745
746 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
747
748 #include <asm/fsl_secure_boot.h>
749
750 #endif  /* __CONFIG_H */