include/configs/km/km8309-common.h

   1 /*
   2  * Copyright (C) 2012 Keymile AG
   3  *                    Gerlando Falauto <gerlando.falauto@keymile.com>
   4  *
   5  * Based on km8321-common.h, see respective copyright notice for credits
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_KM8309_COMMON_H
  11 #define __CONFIG_KM8309_COMMON_H
  12
  13 #define CONFIG_SYS_GENERIC_BOARD
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_E300             1       /* E300 family */
  20 #define CONFIG_QE               1       /* Has QE */
  21 #define CONFIG_MPC830x          1       /* MPC830x family */
  22 #define CONFIG_MPC8309          1       /* MPC8309 CPU specific */
  23
  24 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  25 #define CONFIG_CMD_DIAG         1
  26
  27 /* include common defines/options for all 83xx Keymile boards */
  28 #include "km83xx-common.h"
  29
  30 /* QE microcode/firmware address */
  31 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  32 /* at end of uboot partition, before env */
  33 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  34
  35 /*
  36  * System IO Config
  37  */
  38 /* 0x14000180 SICR_1 */
  39 #define CONFIG_SYS_SICRL (0                     \
  40                 | SICR_1_UART1_UART1RTS         \
  41                 | SICR_1_I2C_CKSTOP             \
  42                 | SICR_1_IRQ_A_IRQ              \
  43                 | SICR_1_IRQ_B_IRQ              \
  44                 | SICR_1_GPIO_A_GPIO            \
  45                 | SICR_1_GPIO_B_GPIO            \
  46                 | SICR_1_GPIO_C_GPIO            \
  47                 | SICR_1_GPIO_D_GPIO            \
  48                 | SICR_1_GPIO_E_GPIO            \
  49                 | SICR_1_GPIO_F_GPIO            \
  50                 | SICR_1_USB_A_UART2S           \
  51                 | SICR_1_USB_B_UART2RTS         \
  52                 | SICR_1_FEC1_FEC1              \
  53                 | SICR_1_FEC2_FEC2              \
  54                 )
  55
  56 /* 0x00080400 SICR_2 */
  57 #define CONFIG_SYS_SICRH (0                     \
  58                 | SICR_2_FEC3_FEC3              \
  59                 | SICR_2_HDLC1_A_HDLC1          \
  60                 | SICR_2_ELBC_A_LA              \
  61                 | SICR_2_ELBC_B_LCLK            \
  62                 | SICR_2_HDLC2_A_HDLC2          \
  63                 | SICR_2_USB_D_GPIO             \
  64                 | SICR_2_PCI_PCI                \
  65                 | SICR_2_HDLC1_B_HDLC1          \
  66                 | SICR_2_HDLC1_C_HDLC1          \
  67                 | SICR_2_HDLC2_B_GPIO           \
  68                 | SICR_2_HDLC2_C_HDLC2          \
  69                 | SICR_2_QUIESCE_B              \
  70                 )
  71
  72 /* GPR_1 */
  73 #define CONFIG_SYS_GPR1  0x50008060
  74
  75 #define CONFIG_SYS_GP1DIR 0x00000000
  76 #define CONFIG_SYS_GP1ODR 0x00000000
  77 #define CONFIG_SYS_GP2DIR 0xFF000000
  78 #define CONFIG_SYS_GP2ODR 0x00000000
  79
  80 /*
  81  * Hardware Reset Configuration Word
  82  */
  83 #define CONFIG_SYS_HRCW_LOW (\
  84         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  85         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  86         HRCWL_CSB_TO_CLKIN_2X1 | \
  87         HRCWL_CORE_TO_CSB_2X1 | \
  88         HRCWL_CE_PLL_VCO_DIV_2 | \
  89         HRCWL_CE_TO_PLL_1X3)
  90
  91 #define CONFIG_SYS_HRCW_HIGH (\
  92         HRCWH_PCI_AGENT | \
  93         HRCWH_PCI_ARBITER_DISABLE | \
  94         HRCWH_CORE_ENABLE | \
  95         HRCWH_FROM_0X00000100 | \
  96         HRCWH_BOOTSEQ_DISABLE | \
  97         HRCWH_SW_WATCHDOG_DISABLE | \
  98         HRCWH_ROM_LOC_LOCAL_16BIT | \
  99         HRCWH_BIG_ENDIAN | \
 100         HRCWH_LALE_NORMAL)
 101
 102 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 103 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 104                                          SDRAM_CFG_32_BE | \
 105                                          SDRAM_CFG_SREN | \
 106                                          SDRAM_CFG_HSE)
 107
 108 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 109 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 110 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 111                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 112
 113 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 114                                          CSCONFIG_ODT_RD_NEVER | \
 115                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 116                                          CSCONFIG_ROW_BIT_13 | \
 117                                          CSCONFIG_COL_BIT_10)
 118
 119 #define CONFIG_SYS_DDR_MODE     0x47860242
 120 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 121
 122 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 123                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 124                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 125                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 126                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 127                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 128                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 129                                  (0 << TIMING_CFG0_RWT_SHIFT))
 130
 131 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 132                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 133                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 134                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 135                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 136                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 137                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 138                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 139
 140 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 141                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 142                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 143                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 144                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 145                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 146                                  (5 << TIMING_CFG2_CPO_SHIFT))
 147
 148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 149
 150 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 151 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 152
 153 /* EEprom support */
 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 155
 156 /*
 157  * Local Bus Configuration & Clock Setup
 158  */
 159 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 160 #define CONFIG_SYS_LCRR_EADC    0x00010000
 161 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 162
 163 #define CONFIG_SYS_LBC_LBCR     0x00000000
 164
 165 /*
 166  * MMU Setup
 167  */
 168 #define CONFIG_SYS_IBAT7L       (0)
 169 #define CONFIG_SYS_IBAT7U       (0)
 170 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 171 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 172
 173 #endif /* __CONFIG_KM8309_COMMON_H */