include/configs/km82xx.h

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC8247
  33 /* MGCOGE */
  34 #if defined(CONFIG_MGCOGE)
  35 #define CONFIG_HOSTNAME         mgcoge
  36 #define CONFIG_KM_BOARD_EXTRA_ENV       ""
  37
  38 /* MGCOGE3NE */
  39 #elif defined(CONFIG_MGCOGE3NE)
  40 #define CONFIG_HOSTNAME         mgcoge3ne
  41 #define CONFIG_KM_82XX
  42 #define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
  43
  44 #else
  45 #error ("Board unsupported")
  46 #endif
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  49
  50 /* include common defines/options for all Keymile boards */
  51 #include "km/keymile-common.h"
  52 #include "km/km-powerpc.h"
  53
  54 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  55 #define CONFIG_SYS_FLASH_BASE           0xFE000000
  56 #define CONFIG_SYS_FLASH_SIZE           32
  57 #define CONFIG_SYS_FLASH_CFI
  58 #define CONFIG_FLASH_CFI_DRIVER
  59
  60 /* MGCOGE */
  61 #if defined(CONFIG_MGCOGE)
  62 #define CONFIG_SYS_MAX_FLASH_BANKS      3
  63 /* max num of sects on one chip */
  64 #define CONFIG_SYS_MAX_FLASH_SECT       512
  65
  66 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  67 #define CONFIG_SYS_FLASH_SIZE_1 32
  68 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
  69 #define CONFIG_SYS_FLASH_SIZE_2 32
  70
  71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  72                                         CONFIG_SYS_FLASH_BASE_1, \
  73                                         CONFIG_SYS_FLASH_BASE_2 }
  74 #define MTDIDS_DEFAULT          "nor3=app"
  75
  76 /*
  77  * Bank 1 - 60x bus SDRAM
  78  */
  79 #define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
  80 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
  81
  82 /* SDRAM initialization values
  83 */
  84
  85 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  86                            ORxS_SDAM_MSK)               |\
  87                         ORxS_BPD_8                      |\
  88                         ORxS_ROWST_PBI0_A7              |\
  89                         ORxS_NUMR_13)
  90
  91 #define CONFIG_SYS_PSDMR (                              \
  92                         PSDMR_SDAM_A14_IS_A5            |\
  93                         PSDMR_BSMA_A14_A16              |\
  94                         PSDMR_SDA10_PBI0_A9             |\
  95                         PSDMR_RFRC_5_CLK                |\
  96                         PSDMR_PRETOACT_2W               |\
  97                         PSDMR_ACTTORW_2W                |\
  98                         PSDMR_LDOTOPRE_1C               |\
  99                         PSDMR_WRC_1C                    |\
 100                         PSDMR_CL_2)
 101
 102 /* MGCOGE3NE */
 103 #elif defined(CONFIG_MGCOGE3NE)
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
 106                                                  * max num of sects on one
 107                                                  * chip
 108                                                  */
 109
 110 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
 111 #define CONFIG_SYS_FLASH_SIZE_1 128
 112
 113 #define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
 114
 115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 116                                         CONFIG_SYS_FLASH_BASE_1 }
 117
 118 #define MTDIDS_DEFAULT          "nor2=app"
 119
 120 /*
 121  * Bank 1 - 60x bus SDRAM
 122  * mgcoge3ne has 256MB
 123  * mgcoge2ne has 128MB
 124  */
 125 #define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
 126 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
 127
 128 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
 129                            ORxS_SDAM_MSK)               |\
 130                         ORxS_BPD_4                      |\
 131                         ORxS_NUMR_13)
 132
 133 #define CONFIG_SYS_PSDMR (                              \
 134                         PSDMR_PBI                       |\
 135                         PSDMR_BSMA_A13_A15              |\
 136                         PSDMR_RFRC_5_CLK                |\
 137                         PSDMR_PRETOACT_2W               |\
 138                         PSDMR_ACTTORW_2W                |\
 139                         PSDMR_LDOTOPRE_1C               |\
 140                         PSDMR_WRC_2C                    |\
 141                         PSDMR_CL_2)
 142
 143 #define CONFIG_SYS_SDRAM_LIST   {                                       \
 144         {       .size   = 256 << 20,                                    \
 145                 .or1    = ORxS_ROWST_PBI1_A4,                           \
 146                 .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
 147         },                                                              \
 148         {       .size   = 128 << 20,                                    \
 149                 .or1    = ORxS_ROWST_PBI1_A5,                           \
 150                 .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
 151         },                                                              \
 152 }
 153 #endif /* defined(CONFIG_MGCOGE3NE) */
 154
 155 /* include further common stuff for all keymile 82xx boards */
 156 /*
 157  * Select serial console configuration
 158  *
 159  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 160  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 161  * for SCC).
 162  */
 163 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
 164 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
 165 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
 166 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
 167 #define CONFIG_SYS_SMC_RXBUFLEN 128
 168 #define CONFIG_SYS_MAXIDLE      10
 169
 170 /*
 171  * Select ethernet configuration
 172  *
 173  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 174  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 175  * SCC, 1-3 for FCC)
 176  *
 177  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 178  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 179  * must be unset.
 180  */
 181 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
 182 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
 183 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
 184
 185 #define CONFIG_ETHER_INDEX      4
 186 #define CONFIG_HAS_ETH0
 187 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
 188
 189 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 190
 191 #ifndef CONFIG_8260_CLKIN
 192 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 193 #endif
 194
 195 #define BOOTFLASH_START         0xFE000000
 196
 197 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
 198
 199 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 200         "app:"                                                          \
 201                 "768k(u-boot),"                                         \
 202                 "128k(env),"                                            \
 203                 "128k(envred),"                                         \
 204                 "3072k(free),"                                          \
 205                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 206
 207 /*
 208  * Default environment settings
 209  */
 210 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 211         CONFIG_KM_BOARD_EXTRA_ENV                                       \
 212         CONFIG_KM_DEF_ENV                                               \
 213         "EEprom_ivm=pca9544a:70:4 \0"                                   \
 214         "unlock=yes\0"                                                  \
 215         "newenv="                                                       \
 216                 "prot off 0xFE0C0000 +0x40000 && "                      \
 217                 "era 0xFE0C0000 +0x40000\0"                             \
 218         "arch=ppc_82xx\0"                                       \
 219         ""
 220
 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 223 #define CONFIG_SYS_RAMBOOT
 224 #endif
 225
 226 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 227
 228 #define CONFIG_ENV_IS_IN_FLASH
 229
 230 #ifdef CONFIG_ENV_IS_IN_FLASH
 231 #define CONFIG_ENV_SECT_SIZE    0x20000
 232 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 233                                         CONFIG_SYS_MONITOR_LEN)
 234 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 235
 236 /* Address and size of Redundant Environment Sector     */
 237 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 238                                                 CONFIG_ENV_SECT_SIZE)
 239 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 240 #endif /* CONFIG_ENV_IS_IN_FLASH */
 241
 242 /* enable I2C and select the hardware/software driver */
 243 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 244 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 245 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed */
 246 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address */
 247
 248 /*
 249  * Software (bit-bang) I2C driver configuration
 250  */
 251
 252 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 253 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 254 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 255 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 256 #define I2C_SDA(bit)    do { \
 257                                 if (bit) \
 258                                         iop->pdat |=  0x00010000; \
 259                                 else \
 260                                         iop->pdat &= ~0x00010000; \
 261                         } while (0)
 262 #define I2C_SCL(bit)    do { \
 263                                 if (bit) \
 264                                         iop->pdat |=  0x00020000; \
 265                                 else \
 266                                         iop->pdat &= ~0x00020000; \
 267                         } while (0)
 268 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 269
 270 #ifndef __ASSEMBLY__
 271 void set_sda(int state);
 272 void set_scl(int state);
 273 int get_sda(void);
 274 int get_scl(void);
 275 #endif
 276
 277 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 278 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 279 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 280 #define CONFIG_SYS_DTT_MAX_TEMP 70
 281 #define CONFIG_SYS_DTT_LOW_TEMP -30
 282 #define CONFIG_SYS_DTT_HYSTERESIS       3
 283 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 284
 285 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 286
 287 #define CONFIG_SYS_IMMR         0xF0000000
 288
 289 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 290 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 291 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 292                                                 GENERATED_GBL_DATA_SIZE)
 293 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 294
 295 /* Hard reset configuration word */
 296 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 297
 298 /* No slaves */
 299 #define CONFIG_SYS_HRCW_SLAVE1          0
 300 #define CONFIG_SYS_HRCW_SLAVE2          0
 301 #define CONFIG_SYS_HRCW_SLAVE3          0
 302 #define CONFIG_SYS_HRCW_SLAVE4          0
 303 #define CONFIG_SYS_HRCW_SLAVE5          0
 304 #define CONFIG_SYS_HRCW_SLAVE6          0
 305 #define CONFIG_SYS_HRCW_SLAVE7          0
 306
 307 /* Initial Memory map for Linux */
 308 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 309
 310 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 311 #if defined(CONFIG_CMD_KGDB)
 312 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 313 #endif
 314
 315 #define CONFIG_SYS_HID0_INIT            0
 316 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 317
 318 #define CONFIG_SYS_HID2         0
 319
 320 #define CONFIG_SYS_SIUMCR               0x4020c200
 321 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 322 #define CONFIG_SYS_BCR                  0x10000000
 323 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 324
 325 /*
 326  *-----------------------------------------------------------------------
 327  * RMR - Reset Mode Register                                     5-5
 328  *-----------------------------------------------------------------------
 329  * turn on Checkstop Reset Enable
 330  */
 331 #define CONFIG_SYS_RMR         0
 332
 333 /*
 334  *-----------------------------------------------------------------------
 335  * TMCNTSC - Time Counter Status and Control                     4-40
 336  *-----------------------------------------------------------------------
 337  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 338  * and enable Time Counter
 339  */
 340 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 341
 342 /*
 343  *-----------------------------------------------------------------------
 344  * PISCR - Periodic Interrupt Status and Control                 4-42
 345  *-----------------------------------------------------------------------
 346  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 347  * Periodic timer
 348  */
 349 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 350
 351 /*
 352  *-----------------------------------------------------------------------
 353  * RCCR - RISC Controller Configuration                         13-7
 354  *-----------------------------------------------------------------------
 355  */
 356 #define CONFIG_SYS_RCCR        0
 357
 358 /*
 359  * Init Memory Controller:
 360  *
 361  * Bank Bus     Machine PortSz  Device
 362  * ---- ---     ------- ------  ------
 363  *  0   60x     GPCM     8 bit  FLASH
 364  *  1   60x     SDRAM   32 bit  SDRAM
 365  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 366  *  5   60x     GPCM    16 bit  CFG-Flash
 367  *
 368  */
 369 /* Bank 0 - FLASH
 370  */
 371 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 372                          BRx_PS_8                       |\
 373                          BRx_MS_GPCM_P                  |\
 374                          BRx_V)
 375
 376 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 377                          ORxG_CSNT                      |\
 378                          ORxG_ACS_DIV2                  |\
 379                          ORxG_SCY_5_CLK                 |\
 380                          ORxG_TRLX)
 381
 382 #define CONFIG_SYS_MPTPR       0x1800
 383
 384 /*
 385  *-----------------------------------------------------------------------------
 386  * Address for Mode Register Set (MRS) command
 387  *-----------------------------------------------------------------------------
 388  */
 389 #define CONFIG_SYS_MRS_OFFS     0x00000110
 390 #define CONFIG_SYS_PSRT        0x0e
 391
 392 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 393                          BRx_PS_64              |\
 394                          BRx_MS_SDRAM_P         |\
 395                          BRx_V)
 396
 397 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 398
 399 /*
 400  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 401  */
 402 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 403 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 404
 405 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 406                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 407
 408 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 409                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 410                          ORxG_SCY_3_CLK | ORxG_TRLX)
 411
 412 /*
 413  * BFTICU board FPGA on CS4 initialization values
 414  */
 415 #define CONFIG_SYS_FPGA_BASE    0x40000000
 416 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 417
 418 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 419                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 420
 421 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 422                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 423                          ORxG_SCY_3_CLK | ORxG_TRLX)
 424
 425 /*
 426  * CFG-Flash on CS5 initialization values
 427  */
 428 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 429                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 430
 431 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 432                                  CONFIG_SYS_FLASH_SIZE_2) |\
 433                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 434                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 435
 436 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 437
 438 /* pass open firmware flat tree */
 439 #define CONFIG_FIT              1
 440 #define CONFIG_OF_LIBFDT        1
 441 #define CONFIG_OF_BOARD_SETUP   1
 442
 443 #define OF_TBCLK                (bd->bi_busfreq / 4)
 444 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 445
 446 #endif /* __CONFIG_H */