include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <config_cmd_default.h>
  11
  12 #define CONFIG_LS102XA
  13
  14 #define CONFIG_SYS_GENERIC_BOARD
  15
  16 #define CONFIG_DISPLAY_CPUINFO
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20 #define CONFIG_BOARD_EARLY_INIT_F
  21
  22 /*
  23  * Size of malloc() pool
  24  */
  25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  29
  30 /*
  31  * Generic Timer Definitions
  32  */
  33 #define GENERIC_TIMER_CLK               12500000
  34
  35 #define CONFIG_SYS_CLK_FREQ             100000000
  36 #define CONFIG_DDR_CLK_FREQ             100000000
  37
  38 #ifdef CONFIG_RAMBOOT_PBL
  39 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  40 #endif
  41
  42 #ifdef CONFIG_SD_BOOT
  43 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
  44 #define CONFIG_SPL_FRAMEWORK
  45 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  46 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  47 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  48 #define CONFIG_SPL_ENV_SUPPORT
  49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  50 #define CONFIG_SPL_I2C_SUPPORT
  51 #define CONFIG_SPL_WATCHDOG_SUPPORT
  52 #define CONFIG_SPL_SERIAL_SUPPORT
  53 #define CONFIG_SPL_MMC_SUPPORT
  54 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  55 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
  56
  57 #define CONFIG_SPL_TEXT_BASE            0x10000000
  58 #define CONFIG_SPL_MAX_SIZE             0x1a000
  59 #define CONFIG_SPL_STACK                0x1001d000
  60 #define CONFIG_SPL_PAD_TO               0x1c000
  61 #define CONFIG_SYS_TEXT_BASE            0x82000000
  62
  63 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  64 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  65 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  66 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  67 #define CONFIG_SYS_MONITOR_LEN          0x80000
  68 #endif
  69
  70 #ifndef CONFIG_SYS_TEXT_BASE
  71 #define CONFIG_SYS_TEXT_BASE            0x67f80000
  72 #endif
  73
  74 #define CONFIG_NR_DRAM_BANKS            1
  75 #define PHYS_SDRAM                      0x80000000
  76 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  77
  78 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  79 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 #define CONFIG_SYS_HAS_SERDES
  82
  83 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
  84
  85 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
  86         !defined(CONFIG_QSPI_BOOT)
  87 #define CONFIG_U_QE
  88 #endif
  89
  90 /*
  91  * IFC Definitions
  92  */
  93 #define CONFIG_FSL_IFC
  94 #define CONFIG_SYS_FLASH_BASE           0x60000000
  95 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  96
  97 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  98 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  99                                 CSPR_PORT_SIZE_16 | \
 100                                 CSPR_MSEL_NOR | \
 101                                 CSPR_V)
 102 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 103
 104 /* NOR Flash Timing Params */
 105 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 106                                         CSOR_NOR_TRHZ_80)
 107 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 108                                         FTIM0_NOR_TEADC(0x5) | \
 109                                         FTIM0_NOR_TAVDS(0x0) | \
 110                                         FTIM0_NOR_TEAHC(0x5))
 111 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 112                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 113                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 114 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 115                                         FTIM2_NOR_TCH(0x4) | \
 116                                         FTIM2_NOR_TWP(0x1c) | \
 117                                         FTIM2_NOR_TWPH(0x0e))
 118 #define CONFIG_SYS_NOR_FTIM3            0
 119
 120 #define CONFIG_FLASH_CFI_DRIVER
 121 #define CONFIG_SYS_FLASH_CFI
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 123 #define CONFIG_SYS_FLASH_QUIET_TEST
 124 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 125
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 128 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 129 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 130
 131 #define CONFIG_SYS_FLASH_EMPTY_INFO
 132 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 133
 134 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 135 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 136
 137 /* CPLD */
 138
 139 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 140 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 141
 142 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 143 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 144                                         CSPR_PORT_SIZE_8 | \
 145                                         CSPR_MSEL_GPCM | \
 146                                         CSPR_V)
 147 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 148 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 149                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 150                                         CSOR_NOR_TRHZ_80)
 151
 152 /* CPLD Timing parameters for IFC GPCM */
 153 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 154                                         FTIM0_GPCM_TEADC(0xf) | \
 155                                         FTIM0_GPCM_TEAHC(0xf))
 156 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 157                                         FTIM1_GPCM_TRAD(0x3f))
 158 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 159                                         FTIM2_GPCM_TCH(0xf) | \
 160                                         FTIM2_GPCM_TWP(0xff))
 161 #define CONFIG_SYS_FPGA_FTIM3           0x0
 162 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 163 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 164 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 165 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 166 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 167 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 168 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 169 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 170 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 171 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 172 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 173 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 174 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 175 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 176 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 177 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 178
 179 /*
 180  * Serial Port
 181  */
 182 #define CONFIG_CONS_INDEX               1
 183 #define CONFIG_SYS_NS16550
 184 #define CONFIG_SYS_NS16550_SERIAL
 185 #define CONFIG_SYS_NS16550_REG_SIZE     1
 186 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 187
 188 #define CONFIG_BAUDRATE                 115200
 189
 190 /*
 191  * I2C
 192  */
 193 #define CONFIG_CMD_I2C
 194 #define CONFIG_SYS_I2C
 195 #define CONFIG_SYS_I2C_MXC
 196
 197 /* EEPROM */
 198 #ifndef CONFIG_SD_BOOT
 199 #define CONFIG_ID_EEPROM
 200 #define CONFIG_SYS_I2C_EEPROM_NXID
 201 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 202 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 203 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 204 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 206 #endif
 207
 208 /*
 209  * MMC
 210  */
 211 #define CONFIG_MMC
 212 #define CONFIG_CMD_MMC
 213 #define CONFIG_FSL_ESDHC
 214 #define CONFIG_GENERIC_MMC
 215
 216 #define CONFIG_CMD_FAT
 217 #define CONFIG_DOS_PARTITION
 218
 219 /*
 220  * Video
 221  */
 222 #define CONFIG_FSL_DCU_FB
 223
 224 #ifdef CONFIG_FSL_DCU_FB
 225 #define CONFIG_VIDEO
 226 #define CONFIG_CMD_BMP
 227 #define CONFIG_CFB_CONSOLE
 228 #define CONFIG_VGA_AS_SINGLE_DEVICE
 229 #define CONFIG_VIDEO_LOGO
 230 #define CONFIG_VIDEO_BMP_LOGO
 231
 232 #define CONFIG_FSL_DCU_SII9022A
 233 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 234 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 235 #endif
 236
 237 /*
 238  * eTSEC
 239  */
 240 #define CONFIG_TSEC_ENET
 241
 242 #ifdef CONFIG_TSEC_ENET
 243 #define CONFIG_MII
 244 #define CONFIG_MII_DEFAULT_TSEC         1
 245 #define CONFIG_TSEC1                    1
 246 #define CONFIG_TSEC1_NAME               "eTSEC1"
 247 #define CONFIG_TSEC2                    1
 248 #define CONFIG_TSEC2_NAME               "eTSEC2"
 249 #define CONFIG_TSEC3                    1
 250 #define CONFIG_TSEC3_NAME               "eTSEC3"
 251
 252 #define TSEC1_PHY_ADDR                  2
 253 #define TSEC2_PHY_ADDR                  0
 254 #define TSEC3_PHY_ADDR                  1
 255
 256 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 257 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 258 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 259
 260 #define TSEC1_PHYIDX                    0
 261 #define TSEC2_PHYIDX                    0
 262 #define TSEC3_PHYIDX                    0
 263
 264 #define CONFIG_ETHPRIME                 "eTSEC1"
 265
 266 #define CONFIG_PHY_GIGE
 267 #define CONFIG_PHYLIB
 268 #define CONFIG_PHY_ATHEROS
 269
 270 #define CONFIG_HAS_ETH0
 271 #define CONFIG_HAS_ETH1
 272 #define CONFIG_HAS_ETH2
 273 #endif
 274
 275 /* PCIe */
 276 #define CONFIG_PCI              /* Enable PCI/PCIE */
 277 #define CONFIG_PCIE1            /* PCIE controler 1 */
 278 #define CONFIG_PCIE2            /* PCIE controler 2 */
 279 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 280 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 281
 282 #define CONFIG_CMD_PING
 283 #define CONFIG_CMD_DHCP
 284 #define CONFIG_CMD_MII
 285 #define CONFIG_CMD_NET
 286
 287 #define CONFIG_CMDLINE_TAG
 288 #define CONFIG_CMDLINE_EDITING
 289
 290 #define CONFIG_CMD_IMLS
 291
 292 #define CONFIG_HWCONFIG
 293 #define HWCONFIG_BUFFER_SIZE            128
 294
 295 #define CONFIG_BOOTDELAY                3
 296
 297 #define CONFIG_EXTRA_ENV_SETTINGS       \
 298         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 299         "initrd_high=0xcfffffff\0"      \
 300         "fdt_high=0xcfffffff\0"
 301
 302 /*
 303  * Miscellaneous configurable options
 304  */
 305 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 306 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 307 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 308 #define CONFIG_AUTO_COMPLETE
 309 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 310 #define CONFIG_SYS_PBSIZE               \
 311                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 312 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 313 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 314
 315 #define CONFIG_CMD_ENV_EXISTS
 316 #define CONFIG_CMD_GREPENV
 317 #define CONFIG_CMD_MEMINFO
 318 #define CONFIG_CMD_MEMTEST
 319 #define CONFIG_SYS_MEMTEST_START        0x80000000
 320 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 321
 322 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 323
 324 /*
 325  * Stack sizes
 326  * The stack sizes are set up in start.S using the settings below
 327  */
 328 #define CONFIG_STACKSIZE                (30 * 1024)
 329
 330 #define CONFIG_SYS_INIT_SP_OFFSET \
 331         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 332 #define CONFIG_SYS_INIT_SP_ADDR \
 333         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 334
 335 #ifdef CONFIG_SPL_BUILD
 336 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 337 #else
 338 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 339 #endif
 340
 341 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 342
 343 /*
 344  * Environment
 345  */
 346 #define CONFIG_ENV_OVERWRITE
 347
 348 #if defined(CONFIG_SD_BOOT)
 349 #define CONFIG_ENV_OFFSET               0x100000
 350 #define CONFIG_ENV_IS_IN_MMC
 351 #define CONFIG_SYS_MMC_ENV_DEV          0
 352 #define CONFIG_ENV_SIZE                 0x20000
 353 #else
 354 #define CONFIG_ENV_IS_IN_FLASH
 355 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 356 #define CONFIG_ENV_SIZE                 0x20000
 357 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 358 #endif
 359
 360 #define CONFIG_OF_LIBFDT
 361 #define CONFIG_OF_BOARD_SETUP
 362 #define CONFIG_CMD_BOOTZ
 363
 364 #define CONFIG_MISC_INIT_R
 365
 366 /* Hash command with SHA acceleration supported in hardware */
 367 #define CONFIG_CMD_HASH
 368 #define CONFIG_SHA_HW_ACCEL
 369
 370 #ifdef CONFIG_SECURE_BOOT
 371 #define CONFIG_CMD_BLOB
 372 #endif
 373
 374 #endif