2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
5 * Alex Bounine , Tundra Semiconductor Corp.
6 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board specific configuration options for Freescale
29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
36 /* Board Configuration Definitions */
37 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
39 #define CONFIG_MPC7448HPC2
42 #define CONFIG_HIGH_BATS /* High BATs supported */
43 #define CONFIG_ALTIVEC /* undef to disable */
45 #define CONFIG_SYS_TEXT_BASE 0xFF000000
47 #define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
48 #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
50 #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
51 #define CONFIG_SYS_BUS_CLK 133000000
53 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
55 #undef CONFIG_ECC /* disable ECC support */
58 #include <galileo/core.h>
61 /* Board-specific Initialization Functions to be called */
62 #define CONFIG_SYS_BOARD_ASM_INIT
63 #define CONFIG_BOARD_EARLY_INIT_F
64 #define CONFIG_BOARD_EARLY_INIT_R
65 #define CONFIG_MISC_INIT_R
67 #define CONFIG_HAS_ETH0
68 #define CONFIG_HAS_ETH1
70 #define CONFIG_ENV_OVERWRITE
73 * High Level Configuration Options
77 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
79 /*#define CONFIG_SYS_HUSH_PARSER */
80 #undef CONFIG_SYS_HUSH_PARSER
82 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
84 /* Pass open firmware flat tree */
85 #define CONFIG_OF_LIBFDT 1
86 #define CONFIG_OF_BOARD_SETUP 1
88 #define OF_TSI "tsi108@c0000000"
89 #define OF_TBCLK (bd->bi_busfreq / 8)
90 #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
93 * The following defines let you select what serial you want to use
94 * for your console driver.
97 * If you have hacked a serial cable onto the second DUART channel,
98 * change the CONFIG_SYS_DUART port from 1 to 0 below.
102 #define CONFIG_CONS_INDEX 1
103 #define CONFIG_SYS_NS16550
104 #define CONFIG_SYS_NS16550_SERIAL
105 #define CONFIG_SYS_NS16550_REG_SIZE 1
106 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
108 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
109 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
111 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
112 #define CONFIG_ZERO_BOOTDELAY_CHECK
114 #undef CONFIG_BOOTARGS
115 /* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
117 #if (CONFIG_BOOTDELAY >= 0)
118 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
119 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
120 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
122 #define CONFIG_BOOTARGS "console=ttyS0,115200"
125 #undef CONFIG_EXTRA_ENV_SETTINGS
127 #define CONFIG_SERIAL "No. 1"
129 /* Networking Configuration */
131 #define CONFIG_TSI108_ETH
132 #define CONFIG_TSI108_ETH_NUM_PORTS 2
135 #define CONFIG_BOOTFILE "zImage.initrd.elf"
136 #define CONFIG_LOADADDR 0x400000
138 /*-------------------------------------------------------------------------- */
140 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
141 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
143 #undef CONFIG_WATCHDOG /* watchdog disabled */
148 #define CONFIG_BOOTP_SUBNETMASK
149 #define CONFIG_BOOTP_GATEWAY
150 #define CONFIG_BOOTP_HOSTNAME
151 #define CONFIG_BOOTP_BOOTPATH
152 #define CONFIG_BOOTP_BOOTFILESIZE
156 * Command line configuration.
158 #include <config_cmd_default.h>
160 #define CONFIG_CMD_ASKENV
161 #define CONFIG_CMD_CACHE
162 #define CONFIG_CMD_PCI
163 #define CONFIG_CMD_I2C
164 #define CONFIG_CMD_SDRAM
165 #define CONFIG_CMD_EEPROM
166 #define CONFIG_CMD_FLASH
167 #define CONFIG_CMD_SAVEENV
168 #define CONFIG_CMD_BSP
169 #define CONFIG_CMD_DHCP
170 #define CONFIG_CMD_PING
171 #define CONFIG_CMD_DATE
174 /*set date in u-boot*/
175 #define CONFIG_RTC_M48T35A
176 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
177 #define CONFIG_SYS_NVRAM_SIZE 0x8000
179 * Miscellaneous configurable options
181 #define CONFIG_VERSION_VARIABLE 1
182 #define CONFIG_TSI108_I2C
183 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
185 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
186 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
188 #define CONFIG_SYS_LONGHELP /* undef to save memory */
189 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
191 #if defined(CONFIG_CMD_KGDB)
192 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
193 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
195 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
198 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
199 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
200 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
202 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
203 #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
205 #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
207 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
210 * Low Level Configuration Settings
211 * (address mappings, register initial values, etc.)
212 * You should know what you are doing if you make changes here.
215 /*-----------------------------------------------------------------------
216 * Definitions for initial stack pointer and data area
220 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
221 * To an unused memory region. The stack will remain in cache until RAM
224 #undef CONFIG_SYS_INIT_RAM_LOCK
225 #define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
226 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */
228 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
230 /*-----------------------------------------------------------------------
231 * Start addresses for the final memory configuration
232 * (Set up by the startup code)
233 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
236 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
237 #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
239 #define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
240 #define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
242 #define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
244 #define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
246 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
248 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
249 #define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
251 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
253 #define PCI0_IO_BASE_BOOTM 0xfd000000
255 #define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
256 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */
258 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
260 /* Peripheral Device section */
263 * Resources on the Tsi108
266 #define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
267 #define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
269 #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
278 #define CONFIG_PCI /* include pci support */
279 #define CONFIG_TSI108_PCI /* include tsi108 pci support */
281 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
282 #define PCI_HOST_FORCE 1 /* configure as pci host */
283 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
285 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
286 #define CONFIG_PCI_PNP /* do pci plug-and-play */
288 /* PCI MEMORY MAP section */
290 /* PCI view of System Memory */
291 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
292 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
293 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
295 /* PCI Memory Space */
296 #define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
297 #define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
298 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
301 #define CONFIG_SYS_PCI_IO_BUS 0x00000000
302 #define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
304 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
306 /* PCI Config Space mapping */
307 #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
308 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
310 #define CONFIG_SYS_IBAT0U 0xFE0003FF
311 #define CONFIG_SYS_IBAT0L 0xFE000002
313 #define CONFIG_SYS_IBAT1U 0x00007FFF
314 #define CONFIG_SYS_IBAT1L 0x00000012
316 #define CONFIG_SYS_IBAT2U 0x80007FFF
317 #define CONFIG_SYS_IBAT2L 0x80000022
319 #define CONFIG_SYS_IBAT3U 0x00000000
320 #define CONFIG_SYS_IBAT3L 0x00000000
322 #define CONFIG_SYS_IBAT4U 0x00000000
323 #define CONFIG_SYS_IBAT4L 0x00000000
325 #define CONFIG_SYS_IBAT5U 0x00000000
326 #define CONFIG_SYS_IBAT5L 0x00000000
328 #define CONFIG_SYS_IBAT6U 0x00000000
329 #define CONFIG_SYS_IBAT6L 0x00000000
331 #define CONFIG_SYS_IBAT7U 0x00000000
332 #define CONFIG_SYS_IBAT7L 0x00000000
334 #define CONFIG_SYS_DBAT0U 0xE0003FFF
335 #define CONFIG_SYS_DBAT0L 0xE000002A
337 #define CONFIG_SYS_DBAT1U 0x00007FFF
338 #define CONFIG_SYS_DBAT1L 0x00000012
340 #define CONFIG_SYS_DBAT2U 0x00000000
341 #define CONFIG_SYS_DBAT2L 0x00000000
343 #define CONFIG_SYS_DBAT3U 0xC0000003
344 #define CONFIG_SYS_DBAT3L 0xC000002A
346 #define CONFIG_SYS_DBAT4U 0x00000000
347 #define CONFIG_SYS_DBAT4L 0x00000000
349 #define CONFIG_SYS_DBAT5U 0x00000000
350 #define CONFIG_SYS_DBAT5L 0x00000000
352 #define CONFIG_SYS_DBAT6U 0x00000000
353 #define CONFIG_SYS_DBAT6L 0x00000000
355 #define CONFIG_SYS_DBAT7U 0x00000000
356 #define CONFIG_SYS_DBAT7L 0x00000000
358 /* I2C addresses for the two DIMM SPD chips */
359 #define DIMM0_I2C_ADDR 0x51
360 #define DIMM1_I2C_ADDR 0x52
363 * For booting Linux, the board info and command line data
364 * have to be in the first 8 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
367 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
369 /*-----------------------------------------------------------------------
372 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
373 #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
374 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
376 #define CONFIG_FLASH_CFI_DRIVER
377 #define CONFIG_SYS_FLASH_CFI
378 #define CONFIG_SYS_WRITE_SWAPPED_DATA
380 #define PHYS_FLASH_SIZE 0x01000000
381 #define CONFIG_SYS_MAX_FLASH_SECT (128)
383 #define CONFIG_ENV_IS_IN_NVRAM
384 #define CONFIG_ENV_ADDR 0xFC000000
386 #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
387 #define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
389 /*-----------------------------------------------------------------------
390 * Cache Configuration
392 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
393 #if defined(CONFIG_CMD_KGDB)
394 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
397 /*-----------------------------------------------------------------------
398 * L2CR setup -- make sure this is right for your board!
399 * look in include/mpc74xx.h for the defines used here
404 #define L2_ENABLE (L2_INIT | L2CR_L2E)
405 #define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
406 #endif /* __CONFIG_H */