661101ccb689acc20c6876d6b88231f92a746c9f
[karo-tx-uboot.git] / include / configs / palmtc.h
1 /*
2  * Palm Tungsten|C configuration file
3  *
4  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #include <asm/arch/pxa-regs.h>
13
14 /*
15  * High Level Board Configuration Options
16  */
17 #define CONFIG_CPU_PXA25X                       1       /* Intel PXA255 CPU */
18 #define CONFIG_PALMTC                   1       /* Palm Tungsten|C board */
19
20 /* we will never enable dcache, because we have to setup MMU first */
21 #define CONFIG_SYS_DCACHE_OFF
22
23 /*
24  * Environment settings
25  */
26 #define CONFIG_ENV_OVERWRITE
27 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
28 #define CONFIG_SYS_TEXT_BASE    0x0
29
30 #define CONFIG_BOOTCOMMAND                                              \
31         "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then "  \
32                 "source 0xa0000000; "                                   \
33         "else "                                                         \
34                 "bootm 0x80000; "                                       \
35         "fi; "
36 #define CONFIG_BOOTARGS                                                 \
37         "console=tty0 console=ttyS0,115200"
38 #define CONFIG_TIMESTAMP
39 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
40 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS
42
43 #define CONFIG_LZMA                     /* LZMA compression support */
44
45 /*
46  * Serial Console Configuration
47  * STUART - the lower serial port on Colibri board
48  */
49 #define CONFIG_PXA_SERIAL
50 #define CONFIG_FFUART                   1
51 #define CONFIG_CONS_INDEX               3
52 #define CONFIG_BAUDRATE                 115200
53
54 /*
55  * Bootloader Components Configuration
56  */
57 #include <config_cmd_default.h>
58
59 #undef  CONFIG_CMD_NET
60 #undef  CONFIG_CMD_NFS
61 #define CONFIG_CMD_ENV
62 #define CONFIG_CMD_MMC
63 #define CONFIG_LCD
64 #define CONFIG_PXA_LCD
65
66 /*
67  * MMC Card Configuration
68  */
69 #ifdef  CONFIG_CMD_MMC
70 #define CONFIG_MMC
71 #define CONFIG_GENERIC_MMC
72 #define CONFIG_PXA_MMC_GENERIC
73 #define CONFIG_SYS_MMC_BASE             0xF0000000
74 #define CONFIG_CMD_FAT
75 #define CONFIG_CMD_EXT2
76 #define CONFIG_DOS_PARTITION
77 #endif
78
79 /*
80  * LCD
81  */
82 #ifdef  CONFIG_LCD
83 #define CONFIG_ACX517AKN
84 #define CONFIG_VIDEO_LOGO
85 #define CONFIG_CMD_BMP
86 #define CONFIG_SPLASH_SCREEN
87 #define CONFIG_SPLASH_SCREEN_ALIGN
88 #define CONFIG_VIDEO_BMP_GZIP
89 #define CONFIG_VIDEO_BMP_RLE8
90 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
91 #endif
92
93 /*
94  * KGDB
95  */
96 #ifdef  CONFIG_CMD_KGDB
97 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
98 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
99 #endif
100
101 /*
102  * HUSH Shell Configuration
103  */
104 #define CONFIG_SYS_HUSH_PARSER          1
105
106 #define CONFIG_SYS_LONGHELP
107 #ifdef  CONFIG_SYS_HUSH_PARSER
108 #define CONFIG_SYS_PROMPT               "$ "
109 #endif
110 #define CONFIG_SYS_CBSIZE               256
111 #define CONFIG_SYS_PBSIZE               \
112         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
113 #define CONFIG_SYS_MAXARGS              16
114 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
115 #define CONFIG_SYS_DEVICE_NULLDEV       1
116
117 /*
118  * Clock Configuration
119  */
120 #undef  CONFIG_SYS_CLKS_IN_HZ
121 #define CONFIG_SYS_HZ                   3686400         /* Timer @ 3686400 Hz */
122 #define CONFIG_SYS_CPUSPEED             0x161           /* 400MHz;L=1 M=3 T=1 */
123
124 /*
125  * DRAM Map
126  */
127 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
128 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
129 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
130
131 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
132 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
133
134 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
135 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
136
137 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
138
139 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
140 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
141
142 /*
143  * NOR FLASH
144  */
145 #ifdef  CONFIG_CMD_FLASH
146 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
147 #define PHYS_FLASH_SIZE                 0x01000000      /* 16 MB */
148 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
149
150 #define CONFIG_SYS_FLASH_CFI
151 #define CONFIG_FLASH_CFI_DRIVER         1
152 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
153
154 #define CONFIG_SYS_MAX_FLASH_BANKS      1
155 #define CONFIG_SYS_MAX_FLASH_SECT       64
156
157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
158
159 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
160 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
161 #define CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
162 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
163 #define CONFIG_SYS_FLASH_PROTECTION
164
165 #define CONFIG_ENV_IS_IN_FLASH          1
166 #define CONFIG_ENV_SECT_SIZE            0x40000
167 #else
168 #define CONFIG_SYS_NO_FLASH
169 #define CONFIG_ENV_IS_NOWHERE
170 #endif
171
172 #define CONFIG_SYS_MONITOR_BASE         0x0
173 #define CONFIG_SYS_MONITOR_LEN          0x40000
174
175 #define CONFIG_ENV_SIZE                 0x4000
176 #define CONFIG_ENV_ADDR                 0x40000
177
178 /*
179  * GPIO settings
180  */
181 #define CONFIG_SYS_GAFR0_L_VAL  0x00011004
182 #define CONFIG_SYS_GAFR0_U_VAL  0xa5000008
183 #define CONFIG_SYS_GAFR1_L_VAL  0x60888050
184 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50aaa
185 #define CONFIG_SYS_GAFR2_L_VAL  0x0aaaaaaa
186 #define CONFIG_SYS_GAFR2_U_VAL  0x00000000
187 #define CONFIG_SYS_GPCR0_VAL    0x0
188 #define CONFIG_SYS_GPCR1_VAL    0x0
189 #define CONFIG_SYS_GPCR2_VAL    0x0
190 #define CONFIG_SYS_GPDR0_VAL    0xcfff8140
191 #define CONFIG_SYS_GPDR1_VAL    0xfcbfbef3
192 #define CONFIG_SYS_GPDR2_VAL    0x0001ffff
193 #define CONFIG_SYS_GPSR0_VAL    0x00010f8f
194 #define CONFIG_SYS_GPSR1_VAL    0x00bf5de5
195 #define CONFIG_SYS_GPSR2_VAL    0x03fe0800
196
197 #define CONFIG_SYS_PSSR_VAL     PSSR_RDH
198
199 /* Clock setup:
200  * CKEN[1] - PWM1 ; CKEN[6] - FFUART
201  * CKEN[12] - MMC ; CKEN[16] - LCD
202  */
203 #define CONFIG_SYS_CKEN         0x00011042
204 #define CONFIG_SYS_CCCR         0x00000161
205
206 /*
207  * Memory settings
208  */
209 #define CONFIG_SYS_MSC0_VAL     0x800092c2
210 #define CONFIG_SYS_MSC1_VAL     0x80008000
211 #define CONFIG_SYS_MSC2_VAL     0x80008000
212 #define CONFIG_SYS_MDCNFG_VAL   0x00001ac9
213 #define CONFIG_SYS_MDREFR_VAL   0x00118018
214 #define CONFIG_SYS_MDMRS_VAL    0x00220032
215 #define CONFIG_SYS_FLYCNFG_VAL  0x01fe01fe
216 #define CONFIG_SYS_SXCNFG_VAL   0x00000000
217
218 /*
219  * PCMCIA and CF Interfaces
220  */
221 #define CONFIG_SYS_MECR_VAL     0x00000000
222 #define CONFIG_SYS_MCMEM0_VAL   0x00010504
223 #define CONFIG_SYS_MCMEM1_VAL   0x00010504
224 #define CONFIG_SYS_MCATT0_VAL   0x00010504
225 #define CONFIG_SYS_MCATT1_VAL   0x00010504
226 #define CONFIG_SYS_MCIO0_VAL    0x00010e04
227 #define CONFIG_SYS_MCIO1_VAL    0x00010e04
228
229 #endif  /* __CONFIG_H */