2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #define CONFIG_SYS_GENERIC_BOARD
9 /* Virtual target or real hardware */
11 #define CONFIG_SYS_THUMB_BUILD
15 * High level configuration
17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_ARCH_EARLY_INIT_R
21 #define CONFIG_SYS_NO_FLASH
25 #define CONFIG_OF_LIBFDT
26 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
31 * Memory configurations
33 #define CONFIG_NR_DRAM_BANKS 1
34 #define PHYS_SDRAM_1 0x0
35 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
36 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
37 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
39 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
40 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
41 #define CONFIG_SYS_INIT_SP_ADDR \
42 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
43 GENERATED_GBL_DATA_SIZE)
45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
46 #define CONFIG_SYS_TEXT_BASE 0x08000040
48 #define CONFIG_SYS_TEXT_BASE 0x01000040
52 * U-Boot general configurations
54 #define CONFIG_SYS_LONGHELP
55 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
56 #define CONFIG_SYS_PBSIZE \
57 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
58 /* Print buffer size */
59 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
60 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
61 /* Boot argument buffer size */
62 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
63 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
64 #define CONFIG_CMDLINE_EDITING /* Command history etc */
65 #define CONFIG_SYS_HUSH_PARSER
70 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
71 #define CONFIG_SYS_CACHELINE_SIZE 32
72 #define CONFIG_SYS_L2_PL310
73 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
76 * EPCS/EPCQx1 Serial Flash Controller
78 #ifdef CONFIG_ALTERA_SPI
79 #define CONFIG_CMD_SPI
81 #define CONFIG_SF_DEFAULT_SPEED 30000000
82 #define CONFIG_SPI_FLASH
83 #define CONFIG_SPI_FLASH_STMICRO
84 #define CONFIG_SPI_FLASH_BAR
86 * The base address is configurable in QSys, each board must specify the
87 * base address based on it's particular FPGA configuration. Please note
88 * that the address here is incremented by 0x400 from the Base address
89 * selected in QSys, since the SPI registers are at offset +0x400.
90 * #define CONFIG_SYS_SPI_BASE 0xff240400
95 * Ethernet on SoC (EMAC)
97 #define CONFIG_DESIGNWARE_ETH
98 #define CONFIG_NET_MULTI
99 #define CONFIG_DW_ALTDESCRIPTOR
101 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
102 #define CONFIG_PHYLIB
103 #define CONFIG_PHY_GIGE
109 #ifdef CONFIG_CMD_FPGA
111 #define CONFIG_FPGA_ALTERA
112 #define CONFIG_FPGA_SOCFPGA
113 #define CONFIG_FPGA_COUNT 1
119 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
120 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
121 #define CONFIG_SYS_TIMER_COUNTS_DOWN
122 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
123 #define CONFIG_SYS_TIMER_RATE 2400000
125 #define CONFIG_SYS_TIMER_RATE 25000000
131 #ifdef CONFIG_HW_WATCHDOG
132 #define CONFIG_DESIGNWARE_WATCHDOG
133 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
134 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
135 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
141 #ifdef CONFIG_CMD_MMC
143 #define CONFIG_BOUNCE_BUFFER
144 #define CONFIG_GENERIC_MMC
147 /* using smaller max blk cnt to avoid flooding the limited stack we have */
148 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
154 #define CONFIG_SYS_I2C
155 #define CONFIG_SYS_I2C_DW
156 #define CONFIG_SYS_I2C_BUS_MAX 4
157 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
158 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
159 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
160 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
161 /* Using standard mode which the speed up to 100Kb/s */
162 #define CONFIG_SYS_I2C_SPEED 100000
163 #define CONFIG_SYS_I2C_SPEED1 100000
164 #define CONFIG_SYS_I2C_SPEED2 100000
165 #define CONFIG_SYS_I2C_SPEED3 100000
166 /* Address of device when used as slave */
167 #define CONFIG_SYS_I2C_SLAVE 0x02
168 #define CONFIG_SYS_I2C_SLAVE1 0x02
169 #define CONFIG_SYS_I2C_SLAVE2 0x02
170 #define CONFIG_SYS_I2C_SLAVE3 0x02
172 /* Clock supplied to I2C controller in unit of MHz */
173 unsigned int cm_get_l4_sp_clk_hz(void);
174 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
176 #define CONFIG_CMD_I2C
181 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
182 #define CONFIG_CMD_DM
184 #define CONFIG_DM_SPI
185 #define CONFIG_DM_SPI_FLASH
186 #define CONFIG_CADENCE_QSPI
187 /* Enable multiple SPI NOR flash manufacturers */
188 #define CONFIG_SPI_FLASH /* SPI flash subsystem */
189 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
190 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
191 #define CONFIG_SPI_FLASH_MTD
192 /* QSPI reference clock */
194 unsigned int cm_get_qspi_controller_clk_hz(void);
195 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
197 #define CONFIG_CQSPI_DECODER 0
198 #define CONFIG_CMD_SF
201 #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
202 #define CONFIG_CMD_DM
204 #define CONFIG_DM_SPI
205 #define CONFIG_DESIGNWARE_SPI
206 #define CONFIG_CMD_SPI
212 #define CONFIG_SYS_NS16550
213 #define CONFIG_SYS_NS16550_SERIAL
214 #define CONFIG_SYS_NS16550_REG_SIZE -4
215 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
216 #define CONFIG_SYS_NS16550_CLK 1000000
218 #define CONFIG_SYS_NS16550_CLK 100000000
220 #define CONFIG_CONS_INDEX 1
221 #define CONFIG_BAUDRATE 115200
226 #ifdef CONFIG_CMD_USB
227 #define CONFIG_USB_DWC2
228 #define CONFIG_USB_STORAGE
230 * NOTE: User must define either of the following to select which
231 * of the two USB controllers available on SoCFPGA to use.
232 * The DWC2 driver doesn't support multiple USB controllers.
233 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
234 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
239 * USB Gadget (DFU, UMS)
241 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
242 #define CONFIG_USB_GADGET
243 #define CONFIG_USB_GADGET_S3C_UDC_OTG
244 #define CONFIG_USB_GADGET_DUALSPEED
245 #define CONFIG_USB_GADGET_VBUS_DRAW 2
247 /* USB Composite download gadget - g_dnl */
248 #define CONFIG_USBDOWNLOAD_GADGET
249 #define CONFIG_USB_GADGET_MASS_STORAGE
251 #define CONFIG_DFU_FUNCTION
252 #define CONFIG_DFU_MMC
253 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
254 #define DFU_DEFAULT_POLL_TIMEOUT 300
257 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
258 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
259 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
260 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
261 #ifndef CONFIG_G_DNL_MANUFACTURER
262 #define CONFIG_G_DNL_MANUFACTURER "Altera"
269 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
270 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
271 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
272 #define CONFIG_ENV_IS_NOWHERE
273 #define CONFIG_ENV_SIZE 4096
278 * SRAM Memory layout:
280 * 0xFFFF_0000 ...... Start of SRAM
281 * 0xFFFF_xxxx ...... Top of stack (grows down)
282 * 0xFFFF_yyyy ...... Malloc area
283 * 0xFFFF_zzzz ...... Global Data
284 * 0xFFFF_FF00 ...... End of SRAM
286 #define CONFIG_SPL_FRAMEWORK
287 #define CONFIG_SPL_BOARD_INIT
288 #define CONFIG_SPL_RAM_DEVICE
289 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
290 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
291 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
293 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
294 #define CONFIG_CRC32_VERIFY
296 /* Linker script for SPL */
297 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
299 #define CONFIG_SPL_LIBCOMMON_SUPPORT
300 #define CONFIG_SPL_LIBGENERIC_SUPPORT
301 #define CONFIG_SPL_WATCHDOG_SUPPORT
302 #define CONFIG_SPL_SERIAL_SUPPORT
304 #ifdef CONFIG_SPL_BUILD
305 #undef CONFIG_PARTITIONS