tricorder: enable hw assisted BCH8 in SPL and u-boot
[karo-tx-uboot.git] / include / configs / tricorder.h
1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Syed Mohammed Khasim <x0khasim@ti.com>
6  *
7  * (C) Copyright 2012
8  * Corscience GmbH & Co. KG
9  * Thomas Weber <weber@corscience.de>
10  *
11  * Configuration settings for the Tricorder board.
12  *
13  * See file CREDITS for list of people who contributed to this
14  * project.
15  *
16  * This program is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License as
18  * published by the Free Software Foundation; either version 2 of
19  * the License, or (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29  * MA 02111-1307 USA
30  */
31
32 #ifndef __CONFIG_H
33 #define __CONFIG_H
34
35 /* High Level Configuration Options */
36 #define CONFIG_OMAP                     /* in a TI OMAP core */
37 #define CONFIG_OMAP34XX                 /* which is a 34XX */
38
39 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
40 /*
41  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
42  * 64 bytes before this address should be set aside for u-boot.img's
43  * header. That is 0x800FFFC0--0x80100000 should not be used for any
44  * other needs.
45  */
46 #define CONFIG_SYS_TEXT_BASE            0x80100000
47
48 #define CONFIG_SDRC                     /* The chip has SDRC controller */
49
50 #include <asm/arch/cpu.h>               /* get chip and board defs */
51 #include <asm/arch/omap3.h>
52
53 /* Display CPU and Board information */
54 #define CONFIG_DISPLAY_CPUINFO
55 #define CONFIG_DISPLAY_BOARDINFO
56
57 /* Clock Defines */
58 #define V_OSCK                          26000000 /* Clock output from T2 */
59 #define V_SCLK                          (V_OSCK >> 1)
60
61 #define CONFIG_MISC_INIT_R
62
63 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
64 #define CONFIG_SETUP_MEMORY_TAGS
65 #define CONFIG_INITRD_TAG
66 #define CONFIG_REVISION_TAG
67
68 #define CONFIG_OF_LIBFDT
69
70 /* Size of malloc() pool */
71 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
72                                                 /* Sector */
73 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
74
75 /* Hardware drivers */
76
77 /* NS16550 Configuration */
78 #define CONFIG_SYS_NS16550
79 #define CONFIG_SYS_NS16550_SERIAL
80 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
81 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
82
83 /* select serial console configuration */
84 #define CONFIG_CONS_INDEX               3
85 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
86 #define CONFIG_SERIAL3                  3
87 #define CONFIG_BAUDRATE                 115200
88 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
89                                         115200}
90
91 /* MMC */
92 #define CONFIG_GENERIC_MMC
93 #define CONFIG_MMC
94 #define CONFIG_OMAP_HSMMC
95 #define CONFIG_DOS_PARTITION
96
97 /* I2C */
98 #define CONFIG_HARD_I2C
99 #define CONFIG_SYS_I2C_SPEED            100000
100 #define CONFIG_SYS_I2C_SLAVE            1
101 #define CONFIG_DRIVER_OMAP34XX_I2C      1
102
103 /* TWL4030 */
104 #define CONFIG_TWL4030_POWER
105 #define CONFIG_TWL4030_LED
106
107 /* Board NAND Info */
108 #define CONFIG_SYS_NO_FLASH             /* no NOR flash */
109 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
110 #define MTDIDS_DEFAULT                  "nand0=nand"
111 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
112                                                 "512k(u-boot-spl)," \
113                                                 "1920k(u-boot)," \
114                                                 "128k(u-boot-env)," \
115                                                 "4m(kernel)," \
116                                                 "-(fs)"
117
118 #define CONFIG_NAND_OMAP_GPMC
119 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
120                                                         /* to access nand */
121 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
122                                                         /* to access nand at */
123                                                         /* CS0 */
124 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
125
126 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
127                                                         /* devices */
128 #define CONFIG_NAND_OMAP_BCH8
129 #define CONFIG_BCH
130
131 /* commands to include */
132 #include <config_cmd_default.h>
133
134 #define CONFIG_CMD_EXT2                 /* EXT2 Support */
135 #define CONFIG_CMD_FAT                  /* FAT support */
136 #define CONFIG_CMD_I2C                  /* I2C serial bus support */
137 #define CONFIG_CMD_MMC                  /* MMC support */
138 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands */
139 #define CONFIG_CMD_NAND                 /* NAND support */
140 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands */
141 #define CONFIG_CMD_UBI                  /* UBI commands */
142 #define CONFIG_CMD_UBIFS                /* UBIFS commands */
143 #define CONFIG_LZO                      /* LZO is needed for UBIFS */
144
145 #undef CONFIG_CMD_NET
146 #undef CONFIG_CMD_NFS
147 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support */
148 #undef CONFIG_CMD_IMI                   /* iminfo */
149 #undef CONFIG_CMD_JFFS2                 /* JFFS2 Support */
150
151 /* needed for ubi */
152 #define CONFIG_RBTREE
153 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
154 #define CONFIG_MTD_PARTITIONS
155
156 /* Environment information */
157 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
158
159 #define CONFIG_BOOTDELAY                3
160
161 #define CONFIG_EXTRA_ENV_SETTINGS \
162         "loadaddr=0x82000000\0" \
163         "console=ttyO2,115200n8\0" \
164         "mmcdev=0\0" \
165         "vram=12M\0" \
166         "lcdmode=800x600\0" \
167         "defaultdisplay=lcd\0" \
168         "kernelopts=rw rootwait\0" \
169         "commonargs=" \
170                 "setenv bootargs console=${console} " \
171                 "vram=${vram} " \
172                 "omapfb.mode=lcd:${lcdmode} " \
173                 "omapdss.def_disp=${defaultdisplay}\0" \
174         "mmcargs=" \
175                 "run commonargs; " \
176                 "setenv bootargs ${bootargs} " \
177                 "root=/dev/mmcblk0p2 " \
178                 "${kernelopts}\0" \
179         "nandargs=" \
180                 "run commonargs; " \
181                 "setenv bootargs ${bootargs} " \
182                 "omapfb.mode=lcd:${lcdmode} " \
183                 "omapdss.def_disp=${defaultdisplay} " \
184                 "root=ubi0:root " \
185                 "ubi.mtd=4 " \
186                 "rootfstype=ubifs " \
187                 "${kernelopts}\0" \
188         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
189         "bootscript=echo Running bootscript from mmc ...; " \
190                 "source ${loadaddr}\0" \
191         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
192         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
193         "mmcboot=echo Booting from mmc ...; " \
194                 "run mmcargs; " \
195                 "bootm ${loadaddr}\0" \
196         "loaduimage_ubi=mtd default; " \
197                 "ubi part fs; " \
198                 "ubifsmount ubi:root; " \
199                 "ubifsload ${loadaddr} /boot/uImage\0" \
200         "nandboot=echo Booting from nand ...; " \
201                 "run nandargs; " \
202                 "run loaduimage_ubi; " \
203                 "bootm ${loadaddr}\0" \
204         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
205                         "if run loadbootscript; then " \
206                                 "run bootscript; " \
207                         "else " \
208                                 "if run loaduimage; then " \
209                                         "run mmcboot; " \
210                                 "else run nandboot; " \
211                                 "fi; " \
212                         "fi; " \
213                 "else run nandboot; fi\0"
214
215
216 #define CONFIG_BOOTCOMMAND "run autoboot"
217
218 /* Miscellaneous configurable options */
219 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
220 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
221 #define CONFIG_AUTO_COMPLETE
222 #define CONFIG_SYS_PROMPT               "OMAP3 Tricorder # "
223 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
224 /* Print Buffer Size */
225 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
226                                         sizeof(CONFIG_SYS_PROMPT) + 16)
227 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
228
229 /* Boot Argument Buffer Size */
230 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
231
232 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
233 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
234                                         0x01000000) /* 16MB */
235
236 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
237
238 /*
239  * OMAP3 has 12 GP timers, they can be driven by the system clock
240  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
241  * This rate is divided by a local divisor.
242  */
243 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
244 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
245 #define CONFIG_SYS_HZ                   1000
246
247 /*  Physical Memory Map  */
248 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
249 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
250 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
251
252 /* NAND and environment organization  */
253 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
254
255 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
256
257 #define CONFIG_ENV_IS_IN_NAND           1
258 #define CONFIG_ENV_OFFSET               0x260000 /* environment starts here */
259
260 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
261 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
262 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
263 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
264                                                 CONFIG_SYS_INIT_RAM_SIZE - \
265                                                 GENERATED_GBL_DATA_SIZE)
266
267 /* SRAM config */
268 #define CONFIG_SYS_SRAM_START           0x40200000
269 #define CONFIG_SYS_SRAM_SIZE            0x10000
270
271 /* Defines for SPL */
272 #define CONFIG_SPL
273 #define CONFIG_SPL_FRAMEWORK
274 #define CONFIG_SPL_NAND_SIMPLE
275
276 #define CONFIG_SPL_BOARD_INIT
277 #define CONFIG_SPL_LIBCOMMON_SUPPORT
278 #define CONFIG_SPL_LIBDISK_SUPPORT
279 #define CONFIG_SPL_I2C_SUPPORT
280 #define CONFIG_SPL_LIBGENERIC_SUPPORT
281 #define CONFIG_SPL_SERIAL_SUPPORT
282 #define CONFIG_SPL_POWER_SUPPORT
283 #define CONFIG_SPL_NAND_SUPPORT
284 #define CONFIG_SPL_NAND_BASE
285 #define CONFIG_SPL_NAND_DRIVERS
286 #define CONFIG_SPL_NAND_ECC
287 #define CONFIG_SPL_MMC_SUPPORT
288 #define CONFIG_SPL_FAT_SUPPORT
289 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
290 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
291 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
292 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
293
294 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
295 #define CONFIG_SPL_MAX_SIZE             (55 * 1024)     /* 7 KB for stack */
296 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
297
298 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
299 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
300
301 /* NAND boot config */
302 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
303 #define CONFIG_SYS_NAND_PAGE_COUNT      64
304 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
305 #define CONFIG_SYS_NAND_OOBSIZE         64
306 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
307 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
308 #define CONFIG_SYS_NAND_ECCPOS          {12, 13, 14, 15, 16, 17, 18, 19, 20,\
309                         21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
310                         34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
311                         47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
312                         60, 61, 62, 63}
313
314 #define CONFIG_SYS_NAND_ECCSIZE         512
315 #define CONFIG_SYS_NAND_ECCBYTES        13
316
317 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
318
319 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
320 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
321
322 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
323 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
324
325 #endif /* __CONFIG_H */