4 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/sizes.h>
20 #include <asm/arch/omap.h>
23 * Ka-Ro TX48 board - SoC configuration
25 #define CONFIG_AM33XX_GPIO
26 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
28 #ifndef CONFIG_SPL_BUILD
29 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_SHOW_ACTIVITY
31 #define CONFIG_DISPLAY_CPUINFO
32 #define CONFIG_DISPLAY_BOARDINFO
33 #define CONFIG_BOARD_LATE_INIT
35 /* LCD Logo and Splash screen support */
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_SPLASH_SCREEN_ALIGN
40 #define CONFIG_VIDEO_DA8XX
41 #define DAVINCI_LCD_CNTL_BASE 0x4830e000
42 #define CONFIG_LCD_LOGO
43 #define LCD_BPP LCD_COLOR24
44 #define CONFIG_CMD_BMP
45 #define CONFIG_VIDEO_BMP_RLE8
46 #endif /* CONFIG_LCD */
47 #endif /* CONFIG_SPL_BUILD */
50 #define V_OSCK 24000000 /* Clock output from T2 */
54 * Memory configuration options
56 #define CONFIG_SYS_SDRAM_DDR3
57 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
58 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
59 #define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
61 #define CONFIG_STACKSIZE SZ_64K
62 #define CONFIG_SYS_MALLOC_LEN SZ_4M
64 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
67 #define CONFIG_SYS_CACHELINE_SIZE 64
70 * U-Boot general configurations
72 #define CONFIG_SYS_LONGHELP
73 #define CONFIG_SYS_PROMPT "TX48 U-Boot > "
74 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
75 #define CONFIG_SYS_PBSIZE \
76 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
77 /* Print buffer size */
78 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
80 /* Boot argument buffer size */
81 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
82 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
83 #define CONFIG_CMDLINE_EDITING /* Command history etc */
85 #define CONFIG_SYS_64BIT_VSPRINTF
86 #define CONFIG_SYS_NO_FLASH
89 * Flattened Device Tree (FDT) support
91 #define CONFIG_OF_LIBFDT
92 #ifdef CONFIG_OF_LIBFDT /* set via cmdline parameter thru boards.cfg */
93 #define CONFIG_FDT_FIXUP_PARTITIONS
94 #define CONFIG_OF_BOARD_SETUP
95 #define CONFIG_MACH_TYPE (-1)
96 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
98 #ifndef MACH_TYPE_TIAM335EVM
99 #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
101 #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
107 #define xstr(s) str(s)
109 #define __pfx(x, s) (x##s)
110 #define _pfx(x, s) __pfx(x, s)
112 #define CONFIG_CMDLINE_TAG
113 #define CONFIG_SETUP_MEMORY_TAGS
114 #define CONFIG_BOOTDELAY 3
115 #define CONFIG_ZERO_BOOTDELAY_CHECK
116 #define CONFIG_SYS_AUTOLOAD "no"
117 #define CONFIG_BOOTFILE "uImage"
118 #define CONFIG_BOOTARGS "console=ttyO0,115200 ro debug panic=1"
119 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
120 #define CONFIG_LOADADDR 83000000
121 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
122 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
123 #define CONFIG_HW_WATCHDOG
128 #ifdef CONFIG_OF_LIBFDT
129 #define TX48_BOOTM_CMD \
130 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"
131 #define TX48_MTDPARTS_CMD ""
133 #define TX48_BOOTM_CMD \
135 #define TX48_MTDPARTS_CMD " ${mtdparts}"
138 #define CONFIG_EXTRA_ENV_SETTINGS \
140 "baseboard=stk5-v3\0" \
141 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
142 " root=/dev/mmcblk0p2 rootwait\0" \
143 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
144 " root=/dev/mtdblock4 rootfstype=jffs2\0" \
145 "nfsroot=/tftpboot/rootfs\0" \
146 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
147 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
148 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
149 " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
150 "bootcmd_nand=set autostart no;run bootargs_nand;" \
151 " nboot linux;run bootm_cmd\0" \
152 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
155 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
157 " ${append_bootargs}\0" \
158 "cpu_clk=" xstr(CONFIG_SYS_MPU_CLK) "\0" \
159 "fdtaddr=81000000\0" \
160 "fdtsave=nand erase.part dtb;nand write ${fdtaddr} dtb ${fdtsize}\0" \
161 "mtdids=" MTDIDS_DEFAULT "\0" \
162 "mtdparts=" MTDPARTS_DEFAULT "\0" \
163 "otg_mode=device\0" \
164 "touchpanel=tsc2007\0" \
167 #define MTD_NAME "omap2-nand.0"
168 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
173 #include <config_cmd_default.h>
174 #define CONFIG_CMD_CACHE
175 #define CONFIG_CMD_MMC
176 #define CONFIG_CMD_NAND
177 #define CONFIG_CMD_MTDPARTS
178 #define CONFIG_CMD_BOOTCE
179 #define CONFIG_CMD_TIME
180 #define CONFIG_CMD_MEMTEST
185 #define CONFIG_SYS_NS16550
186 #define CONFIG_SYS_NS16550_SERIAL
187 #define CONFIG_SYS_NS16550_MEM32
188 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
189 #define CONFIG_SYS_NS16550_CLK 48000000
190 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
191 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
192 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
194 #define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
195 #define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
196 #define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
197 #define CONFIG_CONS_INDEX 1 /* one based! */
198 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
199 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
200 #define CONFIG_SYS_CONSOLE_INFO_QUIET
205 #ifdef CONFIG_CMD_NET
206 #define CONFIG_DRIVER_TI_CPSW
207 #define CONFIG_NET_MULTI
208 #define CONFIG_PHY_GIGE
209 #define CONFIG_PHY_SMSC
210 #define CONFIG_PHYLIB
212 #define CONFIG_CMD_MII
213 #define CONFIG_CMD_DHCP
214 #define CONFIG_CMD_PING
215 /* Add for working with "strict" DHCP server */
216 #define CONFIG_BOOTP_SUBNETMASK
217 #define CONFIG_BOOTP_GATEWAY
218 #define CONFIG_BOOTP_DNS
219 #define CONFIG_BOOTP_DNS2
225 #ifdef CONFIG_CMD_NAND
226 #define CONFIG_MTD_DEVICE
227 #define CONFIG_ENV_IS_IN_NAND
228 #define CONFIG_NAND_OMAP_GPMC
229 #ifndef CONFIG_SPL_BUILD
230 #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
232 #define GPMC_NAND_ECC_LP_x8_LAYOUT
233 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
234 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
235 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
236 #define CONFIG_SYS_NAND_OOBSIZE 64
237 #define CONFIG_SYS_NAND_ECCSIZE 512
238 #define CONFIG_SYS_NAND_ECCBYTES 14
239 #define CONFIG_CMD_NAND_TRIMFFS
240 #define CONFIG_SYS_NAND_MAX_CHIPS 1
241 #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
242 #define CONFIG_SYS_MAX_NAND_DEVICE 1
243 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
244 #define CONFIG_SYS_NAND_USE_FLASH_BBT
245 #ifdef CONFIG_ENV_IS_IN_NAND
246 #define CONFIG_ENV_OVERWRITE
247 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
248 #define CONFIG_ENV_SIZE SZ_128K
249 #define CONFIG_ENV_RANGE 0x60000
250 #endif /* CONFIG_ENV_IS_IN_NAND */
251 #define CONFIG_SYS_NAND_BASE 0x00100000
252 #define CONFIG_SYS_NAND_SIZE SZ_128M
253 #define NAND_BASE CONFIG_SYS_NAND_BASE
254 #endif /* CONFIG_CMD_NAND */
259 #ifdef CONFIG_CMD_MMC
260 #ifndef CONFIG_ENV_IS_IN_NAND
261 #define CONFIG_ENV_IS_IN_MMC
264 #define CONFIG_GENERIC_MMC
265 #define CONFIG_OMAP_HSMMC
266 #define CONFIG_OMAP_MMC_DEV_1
268 #define CONFIG_DOS_PARTITION
269 #define CONFIG_CMD_FAT
270 #define CONFIG_CMD_EXT2
273 * Environments on MMC
275 #ifdef CONFIG_ENV_IS_IN_MMC
276 #define CONFIG_SYS_MMC_ENV_DEV 0
277 #define CONFIG_ENV_OVERWRITE
278 /* Associated with the MMC layout defined in mmcops.c */
279 #define CONFIG_ENV_OFFSET SZ_1K
280 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
281 #define CONFIG_DYNAMIC_MMC_DEVNO
282 #endif /* CONFIG_ENV_IS_IN_MMC */
283 #endif /* CONFIG_CMD_MMC */
285 #ifdef CONFIG_ENV_OFFSET_REDUND
286 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
287 "128k(u-boot-spl)," \
289 xstr(CONFIG_ENV_RANGE) \
291 xstr(CONFIG_ENV_RANGE) \
292 "(env2),4m(linux),16m(rootfs),107904k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
294 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
295 "128k(u-boot-spl)," \
297 xstr(CONFIG_ENV_RANGE) \
298 "(env),4m(linux),16m(rootfs),108288k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
301 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
302 #define SRAM0_SIZE SZ_64K
303 #define OCMC_SRAM_BASE 0x40300000
304 #define CONFIG_SPL_STACK (OCMC_SRAM_BASE + 0xb800)
305 #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + SZ_32K)
307 /* Platform/Board specific defs */
308 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
309 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
311 /* Defines for SPL */
313 #define CONFIG_SPL_FRAMEWORK
314 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
315 #define CONFIG_SPL_GPIO_SUPPORT
316 #ifdef CONFIG_NAND_OMAP_GPMC
317 #define CONFIG_SPL_NAND_SUPPORT
318 #define CONFIG_SPL_NAND_DRIVERS
319 #define CONFIG_SPL_NAND_BASE
320 #define CONFIG_SPL_NAND_ECC
321 #define CONFIG_SPL_NAND_AM33XX_BCH
322 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
323 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
324 CONFIG_SYS_NAND_PAGE_SIZE)
325 #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
326 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
327 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
328 10, 11, 12, 13, 14, 15, 16, 17, \
329 18, 19, 20, 21, 22, 23, 24, 25, \
330 26, 27, 28, 29, 30, 31, 32, 33, \
331 34, 35, 36, 37, 38, 39, 40, 41, \
332 42, 43, 44, 45, 46, 47, 48, 49, \
333 50, 51, 52, 53, 54, 55, 56, 57, }
336 #define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
337 #define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
339 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
341 #define CONFIG_SPL_LIBCOMMON_SUPPORT
342 #define CONFIG_SPL_LIBGENERIC_SUPPORT
343 #define CONFIG_SPL_SERIAL_SUPPORT
344 #define CONFIG_SPL_YMODEM_SUPPORT
345 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
348 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
349 * 64 bytes before this address should be set aside for u-boot.img's
350 * header. That is 0x800FFFC0--0x80100000 should not be used for any
353 #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
354 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
356 #endif /* __CONFIG_H */