2 * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX51 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX51 board - SoC configuration
19 #define CONFIG_SYS_MX5_IOMUX_V3
20 #define CONFIG_MXC_GPIO /* GPIO control */
21 #define CONFIG_SYS_MX5_HCLK 24000000
22 #define CONFIG_SYS_DDR_CLKSEL 0
23 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
24 #define CONFIG_SHOW_ACTIVITY
25 #define CONFIG_DISPLAY_BOARDINFO
26 #define CONFIG_BOARD_LATE_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
29 #if CONFIG_SYS_CPU_CLK == 600
30 #define TX51_MOD_PREFIX "6"
31 #elif CONFIG_SYS_CPU_CLK == 800
32 #define TX51_MOD_PREFIX "8"
33 #define CONFIG_MX51_PLL_ERRATA
35 #error Invalid CPU clock
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_IPUV3
44 #define CONFIG_IPUV3_CLK 200000000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
52 * Memory configuration options
54 #ifndef CONFIG_SYS_SDRAM_CLK
55 #define CONFIG_SYS_SDRAM_CLK 166
57 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
58 #define PHYS_SDRAM_1_SIZE SZ_128M
59 #if CONFIG_NR_DRAM_BANKS > 1
60 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
61 #define PHYS_SDRAM_2_SIZE SZ_128M
63 #define CONFIG_STACKSIZE SZ_128K
64 #define CONFIG_SYS_MALLOC_LEN SZ_8M
65 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
66 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
67 #define CONFIG_SYS_SDRAM_CLK 166
68 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
71 * U-Boot general configurations
73 #define CONFIG_SYS_LONGHELP
74 #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
75 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
76 #define CONFIG_SYS_PBSIZE \
77 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
78 /* Print buffer size */
79 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
80 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
81 /* Boot argument buffer size */
82 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
83 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
84 #define CONFIG_CMDLINE_EDITING /* Command history etc */
86 #define CONFIG_SYS_64BIT_VSPRINTF
87 #define CONFIG_SYS_NO_FLASH
90 * Flattened Device Tree (FDT) support
92 #define CONFIG_OF_LIBFDT
93 #define CONFIG_OF_BOARD_SETUP
94 #define CONFIG_DEFAULT_DEVICE_TREE tx51
95 #define CONFIG_ARCH_DEVICE_TREE mx51
96 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
101 #define xstr(s) str(s)
103 #define __pfx(x, s) (x##s)
104 #define _pfx(x, s) __pfx(x, s)
106 #define CONFIG_CMDLINE_TAG
107 #define CONFIG_SETUP_MEMORY_TAGS
108 #define CONFIG_BOOTDELAY 3
109 #define CONFIG_ZERO_BOOTDELAY_CHECK
110 #define CONFIG_SYS_AUTOLOAD "no"
111 #define CONFIG_BOOTFILE "uImage"
112 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
113 #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
114 #define CONFIG_LOADADDR 94000000
115 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
116 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
117 #define CONFIG_HW_WATCHDOG
120 * Extra Environment Settings
122 #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_CPU_CLK)
124 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "baseboard=stk5-v3\0" \
127 "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
128 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
129 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
130 " root=/dev/mmcblk0p2 rootwait\0" \
131 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
132 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
134 "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
135 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
136 "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
138 "bootcmd_mmc=set autostart no;run bootargs_mmc" \
139 ";fatload mmc 0 ${loadaddr} uImage\0" \
140 "bootcmd_nand=set autostart no;run bootargs_ubifs" \
142 "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
144 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
146 "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
147 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
148 " ${append_bootargs}\0" \
149 "fdtaddr=91000000\0" \
150 "fdtsave=nand erase.part dtb" \
151 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
152 "mtdids=" MTDIDS_DEFAULT "\0" \
153 "mtdparts=" MTDPARTS_DEFAULT "\0" \
154 "nfsroot=/tftpboot/rootfs\0" \
155 "otg_mode=device\0" \
156 "touchpanel=tsc2007\0" \
159 #define MTD_NAME "mxc_nand"
160 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
161 #define CONFIG_FDT_FIXUP_PARTITIONS
166 #include <config_cmd_default.h>
167 #define CONFIG_CMD_CACHE
168 #define CONFIG_CMD_MMC
169 #define CONFIG_CMD_NAND
170 #define CONFIG_CMD_MTDPARTS
171 #define CONFIG_CMD_BOOTCE
172 #define CONFIG_CMD_TIME
173 #define CONFIG_CMD_MEMTEST
178 #define CONFIG_MXC_UART
179 #define CONFIG_MXC_UART_BASE UART1_BASE
180 #define CONFIG_MXC_GPIO
181 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
182 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
183 #define CONFIG_SYS_CONSOLE_INFO_QUIET
188 #define CONFIG_FEC_MXC
189 #ifdef CONFIG_FEC_MXC
190 #define IMX_FEC_BASE FEC_BASE_ADDR
191 #define CONFIG_FEC_MXC_PHYADDR 0x1f
192 #define CONFIG_PHYLIB
193 #define CONFIG_PHY_SMSC
195 #define CONFIG_FEC_XCV_TYPE MII100
196 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
197 #define CONFIG_CMD_MII
198 #define CONFIG_CMD_DHCP
199 #define CONFIG_CMD_PING
200 /* Add for working with "strict" DHCP server */
201 #define CONFIG_BOOTP_SUBNETMASK
202 #define CONFIG_BOOTP_GATEWAY
203 #define CONFIG_BOOTP_DNS
209 #ifdef CONFIG_CMD_NAND
210 #define CONFIG_MTD_DEVICE
211 #define CONFIG_ENV_IS_IN_NAND
212 #define CONFIG_NAND_MXC
213 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
214 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
215 #define CONFIG_MXC_NAND_HWECC
216 #define CONFIG_CMD_NAND_TRIMFFS
217 #define CONFIG_SYS_NAND_MAX_CHIPS 1
218 #define CONFIG_SYS_MAX_NAND_DEVICE 1
219 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
220 #define CONFIG_SYS_NAND_USE_FLASH_BBT
221 #ifdef CONFIG_ENV_IS_IN_NAND
222 #define CONFIG_ENV_OVERWRITE
223 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
224 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
225 #define CONFIG_ENV_RANGE 0x60000
227 #define CONFIG_SYS_NAND_BASE 0x00000000
228 #define CONFIG_CMD_ROMUPDATE
229 #endif /* CONFIG_CMD_NAND */
234 #ifdef CONFIG_CMD_MMC
235 #ifndef CONFIG_ENV_IS_IN_NAND
236 #define CONFIG_ENV_IS_IN_MMC
239 #define CONFIG_GENERIC_MMC
240 #define CONFIG_FSL_ESDHC
241 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
242 #define CONFIG_SYS_FSL_ESDHC_NUM 2
244 #define CONFIG_DOS_PARTITION
245 #define CONFIG_CMD_FAT
246 #define CONFIG_CMD_EXT2
249 * Environments on MMC
251 #ifdef CONFIG_ENV_IS_IN_MMC
252 #define CONFIG_SYS_MMC_ENV_DEV 0
253 #define CONFIG_ENV_OVERWRITE
254 /* Associated with the MMC layout defined in mmcops.c */
255 #define CONFIG_ENV_OFFSET SZ_1K
256 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
257 #define CONFIG_DYNAMIC_MMC_DEVNO
258 #endif /* CONFIG_ENV_IS_IN_MMC */
259 #endif /* CONFIG_CMD_MMC */
261 #ifdef CONFIG_ENV_OFFSET_REDUND
262 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
264 xstr(CONFIG_ENV_RANGE) \
266 xstr(CONFIG_ENV_RANGE) \
267 "(env2),4m(linux),16m(rootfs),108032k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
269 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
271 xstr(CONFIG_ENV_RANGE) \
272 "(env),4m(linux),16m(rootfs),108416k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
275 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
276 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
277 GENERATED_GBL_DATA_SIZE)
279 #ifdef CONFIG_CMD_IIM
280 #define CONFIG_FSL_IIM
283 #endif /* __CONFIG_H */