include/configs/vexpress_aemv8a.h

   1 /*
   2  * Configuration for Versatile Express. Parts were derived from other ARM
   3  *   configurations.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __VEXPRESS_AEMV8A_H
   9 #define __VEXPRESS_AEMV8A_H
  10
  11 #define DEBUG
  12
  13 #define CONFIG_REMAKE_ELF
  14
  15 #define CONFIG_GICV3
  16
  17 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
  18
  19 /*#define CONFIG_SYS_GENERIC_BOARD*/
  20
  21 #define CONFIG_SYS_NO_FLASH
  22
  23 #define CONFIG_SUPPORT_RAW_INITRD
  24
  25 /* Cache Definitions */
  26 #define CONFIG_SYS_DCACHE_OFF
  27 #define CONFIG_SYS_ICACHE_OFF
  28
  29 #define CONFIG_IDENT_STRING             " vexpress_aemv8a"
  30 #define CONFIG_BOOTP_VCI_STRING         "U-boot.armv8.vexpress_aemv8a"
  31
  32 /* Link Definitions */
  33 #define CONFIG_SYS_TEXT_BASE            0x80000000
  34 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  35
  36 /* Flat Device Tree Definitions */
  37 #define CONFIG_OF_LIBFDT
  38
  39 #define CONFIG_DEFAULT_DEVICE_TREE      vexpress64
  40
  41 /* SMP Spin Table Definitions */
  42 #define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  43
  44 /* CS register bases for the original memory map. */
  45 #define V2M_PA_CS0                      0x00000000
  46 #define V2M_PA_CS1                      0x14000000
  47 #define V2M_PA_CS2                      0x18000000
  48 #define V2M_PA_CS3                      0x1c000000
  49 #define V2M_PA_CS4                      0x0c000000
  50 #define V2M_PA_CS5                      0x10000000
  51
  52 #define V2M_PERIPH_OFFSET(x)            (x << 16)
  53 #define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  54 #define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  55 #define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  56
  57 #define V2M_BASE                        0x80000000
  58
  59 /*
  60  * Physical addresses, offset from V2M_PA_CS0-3
  61  */
  62 #define V2M_NOR0                        (V2M_PA_CS0)
  63 #define V2M_NOR1                        (V2M_PA_CS4)
  64 #define V2M_SRAM                        (V2M_PA_CS1)
  65
  66 /* Common peripherals relative to CS7. */
  67 #define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  68 #define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  69 #define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  70 #define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  71
  72 #define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  73 #define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  74 #define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  75 #define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  76
  77 #define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  78
  79 #define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  80 #define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  81
  82 #define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  83 #define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  84
  85 #define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  86
  87 #define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  88
  89 /* System register offsets. */
  90 #define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
  91 #define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
  92 #define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
  93
  94 /* Generic Timer Definitions */
  95 #define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
  96
  97 /* Generic Interrupt Controller Definitions */
  98 #ifdef CONFIG_GICV3
  99 #define GICD_BASE                       (0x2f000000)
 100 #define GICR_BASE                       (0x2f100000)
 101 #else
 102 #define GICD_BASE                       (0x2C001000)
 103 #define GICC_BASE                       (0x2C002000)
 104 #endif
 105
 106 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 107 #define CONFIG_SYS_MEMTEST_END          (V2M_BASE + 0x80000000)
 108
 109 /* Size of malloc() pool */
 110 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 111
 112 /* SMSC91C111 Ethernet Configuration */
 113 #define CONFIG_SMC91111                 1
 114 #define CONFIG_SMC91111_BASE            (0x01A000000)
 115
 116 /* PL011 Serial Configuration */
 117 #define CONFIG_PL011_SERIAL
 118 #define CONFIG_PL011_CLOCK              24000000
 119 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 120                                          (void *)CONFIG_SYS_SERIAL1}
 121 #define CONFIG_CONS_INDEX               0
 122
 123 #define CONFIG_BAUDRATE                 115200
 124 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 125 #define CONFIG_SYS_SERIAL0              V2M_UART0
 126 #define CONFIG_SYS_SERIAL1              V2M_UART1
 127
 128 /* Command line configuration */
 129 #define CONFIG_MENU
 130 /*#define CONFIG_MENU_SHOW*/
 131 #define CONFIG_CMD_CACHE
 132 #define CONFIG_CMD_BDI
 133 #define CONFIG_CMD_DHCP
 134 #define CONFIG_CMD_PXE
 135 #define CONFIG_CMD_ENV
 136 #define CONFIG_CMD_FLASH
 137 #define CONFIG_CMD_IMI
 138 #define CONFIG_CMD_MEMORY
 139 #define CONFIG_CMD_MII
 140 #define CONFIG_CMD_NET
 141 #define CONFIG_CMD_PING
 142 #define CONFIG_CMD_SAVEENV
 143 #define CONFIG_CMD_RUN
 144 #define CONFIG_CMD_BOOTD
 145 #define CONFIG_CMD_ECHO
 146 #define CONFIG_CMD_SOURCE
 147 #define CONFIG_CMD_FAT
 148 #define CONFIG_DOS_PARTITION
 149
 150 /* BOOTP options */
 151 #define CONFIG_BOOTP_BOOTFILESIZE
 152 #define CONFIG_BOOTP_BOOTPATH
 153 #define CONFIG_BOOTP_GATEWAY
 154 #define CONFIG_BOOTP_HOSTNAME
 155 #define CONFIG_BOOTP_PXE
 156 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 157
 158 /* Miscellaneous configurable options */
 159 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 160
 161 /* Physical Memory Map */
 162 #define CONFIG_NR_DRAM_BANKS            1
 163 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 164 #define PHYS_SDRAM_1_SIZE               0x80000000      /* 2048 MB */
 165 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 166
 167 /* Initial environment variables */
 168 #define CONFIG_EXTRA_ENV_SETTINGS       \
 169                                         "kernel_addr=0x200000\0"        \
 170                                         "initrd_addr=0xa00000\0"        \
 171                                         "initrd_size=0x2000000\0"       \
 172                                         "fdt_addr=0x100000\0"           \
 173                                         "fdt_high=0xa0000000\0"
 174
 175 #define CONFIG_BOOTARGS                 "console=ttyAMA0 root=/dev/ram0"
 176 #define CONFIG_BOOTCOMMAND              "bootm $kernel_addr " \
 177                                         "$initrd_addr:$initrd_size $fdt_addr"
 178 #define CONFIG_BOOTDELAY                -1
 179
 180 /* Do not preserve environment */
 181 #define CONFIG_ENV_IS_NOWHERE           1
 182 #define CONFIG_ENV_SIZE                 0x1000
 183
 184 /* Monitor Command Prompt */
 185 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 186 #define CONFIG_SYS_PROMPT               "VExpress64# "
 187 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 188                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 189 #define CONFIG_SYS_HUSH_PARSER
 190 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 191 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 192 #define CONFIG_SYS_LONGHELP
 193 #define CONFIG_CMDLINE_EDITING          1
 194 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 195
 196 #endif /* __VEXPRESS_AEMV8A_H */