add new board vl_ma2sc
[karo-tx-uboot.git] / include / configs / vl_ma2sc.h
1 /*
2  * (C) Copyright 2009-2012
3  * Jens Scharsig  <esw@bus-elekronik.de>
4  * BuS Elektronik GmbH & Co. KG
5  *
6  * Configuation settings for the VL_MA2SC board.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 /*--------------------------------------------------------------------------*/
31
32 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
33 #define CONFIG_ARM926EJS                /* This is an ARM926EJS Core    */
34 #define CONFIG_AT91FAMILY
35 #define CONFIG_AT91SAM9263              /* It's an Atmel AT91SAM9263 SoC*/
36 #define CONFIG_VL_MA2SC                 /* on an VL_MA2SC Board */
37 #define CONFIG_ARCH_CPU_INIT
38 #define CONFIG_MISC_INIT_R
39
40 #include <asm/hardware.h>
41
42 #define MACH_TYPE_VL_MA2SC              2412
43 #define CONFIG_MACH_TYPE                MACH_TYPE_VL_MA2SC
44
45 #define CONFIG_SYS_DCACHE_OFF
46
47 #ifdef CONFIG_RAMLOAD
48 #define CONFIG_SYS_TEXT_BASE            0x21000000
49 #else
50 #define CONFIG_SYS_TEXT_BASE            0x00000000
51 #endif
52 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
53
54 #define CONFIG_IDENT_STRING             " on MiS Activ 2"
55 #define CONFIG_VERSION_VARIABLE
56 #define CONFIG_AT91_GPIO
57
58 #if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
59 #define CONFIG_SYS_USE_NORFLASH
60 #define CONFIG_SYS_USE_BOOT_NORFLASH
61 #endif
62
63 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
64 #define CONFIG_SETUP_MEMORY_TAGS
65 #define CONFIG_INITRD_TAG
66
67 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
68 #define CONFIG_SKIP_LOWLEVEL_INIT
69 #endif
70
71 /*
72  * Hardware drivers
73  */
74
75 #define CONFIG_BOARD_EARLY_INIT_F
76
77 #define CONFIG_WATCHDOG
78
79 #define CONFIG_ATMEL_USART
80 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
81 #define CONFIG_USART_ID                 ATMEL_ID_SYS
82
83 /* LCD */
84 #define CONFIG_LCD
85 #define CONFIG_ATMEL_LCD
86 #define CONFIG_SPLASH_SCREEN
87 #define CONFIG_SYS_BLACK_ON_WHITE
88 #define LCD_BPP                         LCD_COLOR8
89 #define CONFIG_ATMEL_LCD_BGR555
90
91 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
92 #define CONFIG_BOOTDELAY                3
93
94 /*
95  * BOOTP options
96  */
97 #define CONFIG_BOOTP_BOOTFILESIZE
98 #define CONFIG_BOOTP_BOOTPATH
99 #define CONFIG_BOOTP_GATEWAY
100 #define CONFIG_BOOTP_HOSTNAME
101
102 /*
103  * Command line configuration.
104  */
105 #include <config_cmd_default.h>
106 #undef CONFIG_CMD_BDI
107 #undef CONFIG_CMD_FPGA
108 #undef CONFIG_CMD_IMI
109 #undef CONFIG_CMD_LOADS
110
111 #define CONFIG_CMD_BMP
112 #define CONFIG_CMD_DATE
113 #define CONFIG_CMD_DHCP
114 #define CONFIG_CMD_I2C
115 #define CONFIG_CMD_NAND
116 #define CONFIG_CMD_MII
117 #define CONFIG_CMD_PING
118 #define CONFIG_CMD_MD5SUM
119 #define CONFIG_CMD_SHA1SUM
120 /*
121 #define CONFIG_CMD_SPI
122 */
123 #define CONFIG_CMD_FAT
124 #define CONFIG_CMD_USB
125
126 #define CONFIG_SYS_LONGHELP
127 #define CONFIG_MD5
128 #define CONFIG_SHA1
129
130 /*----------------------------------------------------------------------------
131  * Hardware confuguration
132  *---------------------------------------------------------------------------*/
133
134 /* USB */
135 #define CONFIG_USB_ATMEL
136 #define CONFIG_USB_OHCI_NEW
137 #define CONFIG_DOS_PARTITION
138 #define CONFIG_SYS_USB_OHCI_CPU_INIT
139 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* UHP_BASE */
140 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
141 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
142 #define CONFIG_USB_STORAGE
143 #define CONFIG_AT91C_PQFP_UHPBUG
144
145 /* I2C-Bus */
146
147 #define CONFIG_SYS_I2C_SPEED                    50000
148 #define CONFIG_SYS_I2C_SLAVE                    0               /* not used */
149
150 #ifndef CONFIG_HARD_I2C
151 #define CONFIG_SOFT_I2C
152
153 /* Software  I2C driver configuration */
154
155 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
156
157 #define AT91_PIN_SDA    (1<<4)          /* AT91C_PIO_PB4 */
158 #define AT91_PIN_SCL    (1<<5)          /* AT91C_PIO_PB5 */
159
160 #define I2C_INIT        i2c_init_board();
161 #define I2C_ACTIVE      writel(AT91_PIN_SDA, &pio->piob.mddr);
162 #define I2C_TRISTATE    writel(AT91_PIN_SDA, &pio->piob.mder);
163 #define I2C_READ        ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
164 #define I2C_SDA(bit)                                            \
165         do {                                                    \
166                 if (bit)                                        \
167                         writel(AT91_PIN_SDA, &pio->piob.sodr);  \
168                 else                                            \
169                         writel(AT91_PIN_SDA, &pio->piob.codr);  \
170         } while (0);
171 #define I2C_SCL(bit)                                            \
172         do {                                                    \
173                 if (bit)                                        \
174                         writel(AT91_PIN_SCL, &pio->piob.sodr);  \
175                 else                                            \
176                         writel(AT91_PIN_SCL, &pio->piob.codr);  \
177         } while (0);
178 #endif
179
180 /* I2C-RTC */
181
182 #ifdef CONFIG_CMD_DATE
183 #define CONFIG_RTC_DS1338
184 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
185 #endif
186
187 /* EEPROM */
188
189 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
190 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
191
192 /* define PDC[31:16] as DATA[31:16] */
193 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
194 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
195
196 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
197 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL                                   \
198         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
199          AT91_MATRIX_CSA_EBI_CS1A)
200
201 /* user reset enable */
202 #define CONFIG_SYS_RSTC_RMR_VAL                 \
203                 (AT91_RSTC_KEY |                \
204                 AT91_RSTC_MR_URSTEN |           \
205                 AT91_RSTC_MR_ERSTL(15))
206
207 /* Disable Watchdog */
208 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
209                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
210                  AT91_WDT_MR_WDV(0xFFF) |                       \
211                  AT91_WDT_MR_WDDIS |                            \
212                  AT91_WDT_MR_WDD(0xFFF))
213
214 /* clocks */
215
216 #define CONFIG_SYS_HZ                   1000
217 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
218
219 #define MHZ180
220 #if defined(MHZ199)
221 /* 199,8994 MHZ */
222 #define MASTER_PLL_MUL          911
223 #define MASTER_PLL_DIV          56
224 #define MASTER_PLL_OUT          2
225 #elif defined(MHZ180)
226 /* 180 MHZ */
227 #define MASTER_PLL_MUL          1875
228 #define MASTER_PLL_DIV          128
229 #define MASTER_PLL_OUT          2
230 #elif defined(MHZTEST)
231 /* Test MHZ */
232 #define CONFIG_DISPLAY_CPUINFO
233 #define MASTER_PLL_MUL          8
234 #define MASTER_PLL_DIV          1
235 #define MASTER_PLL_OUT          2
236 #else
237 /* 176.9472 MHZ */
238 #define MASTER_PLL_MUL          72
239 #define MASTER_PLL_DIV          5
240 #define MASTER_PLL_OUT          2
241 #endif
242
243 #define CONFIG_SYS_MOR_VAL                                      \
244         (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
245
246 #define CONFIG_SYS_PLLAR_VAL                                    \
247         (AT91_PMC_PLLAR_29 |                                    \
248         AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
249         AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
250         AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
251         AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
252
253 /* PCK/2 = MCK Master Clock from PLLA */
254 #define CONFIG_SYS_MCKR1_VAL            \
255         (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
256          AT91_PMC_MCKR_MDIV_2)
257
258 /* PCK/2 = MCK Master Clock from PLLA */
259 #define CONFIG_SYS_MCKR2_VAL            \
260         (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
261         AT91_PMC_MCKR_MDIV_2)
262
263 /* SDRAM */
264 #define CONFIG_NR_DRAM_BANKS            1
265 #define CONFIG_SYS_SDRAM_BASE           0x20000000
266 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
267 #define CONFIG_SYS_INIT_SP_ADDR         0x00504000  /* use internal SRAM0 */
268
269 #define CONFIG_SYS_SDRC_MR_VAL1         0
270 #define CONFIG_SYS_SDRC_TR_VAL1         700
271 #define CONFIG_SYS_SDRC_CR_VAL                                          \
272                 (AT91_SDRAMC_NC_9 |                                     \
273                  AT91_SDRAMC_NR_13 |                                    \
274                  AT91_SDRAMC_NB_4 |                                     \
275                  AT91_SDRAMC_CAS_3 |                                    \
276                  AT91_SDRAMC_DBW_32 |                                   \
277                  (2 <<  8) |            /* Write Recovery Delay */      \
278                  (7 << 12) |            /* Row Cycle Delay */           \
279                  (2 << 16) |            /* Row Precharge Delay */       \
280                  (2 << 20) |            /* Row to Column Delay */       \
281                  (5 << 24) |            /* Active to Precharge Delay */ \
282                  (8 << 28))             /* Exit Self Refresh to Active Delay */
283
284 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
285 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
286 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
287 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
288 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
289 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
290 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
291 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
292 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
293 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
294 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
295 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
296 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
297 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
298 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
299 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
300 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
301 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
302
303 /* NOR flash */
304
305 #define CONFIG_FLASH_SHOW_PROGRESS      45
306 #define CONFIG_SYS_FLASH_CFI
307 #define CONFIG_FLASH_CFI_DRIVER
308 #define PHYS_FLASH_1                    0x10000000
309 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
310 #define CONFIG_SYS_MAX_FLASH_SECT       256
311 #define CONFIG_SYS_MAX_FLASH_BANKS      1
312
313 #define CONFIG_ENV_IS_IN_FLASH
314 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x00060000)
315
316 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
317 #define CONFIG_SYS_SMC0_SETUP0_VAL                              \
318         (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
319          AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
320 #define CONFIG_SYS_SMC0_PULSE0_VAL                              \
321         (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
322          AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
323 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
324         (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
325 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
326         (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
327          AT91_SMC_MODE_DBW_16 |                                 \
328          AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
329
330 /* NAND flash */
331 #ifdef CONFIG_CMD_NAND
332 #define CONFIG_NAND_ATMEL
333 #define CONFIG_SYS_MAX_NAND_DEVICE      1
334 #define CONFIG_SYS_NAND_BASE            0x40000000
335 #define CONFIG_SYS_NAND_DBW_8           1
336 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)       /* our ALE is AD21 */
337 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)       /* our CLE is AD22 */
338 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIO_PORTD, 15
339 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIO_PORTB, 0
340 #define CONFIG_SYS_64BIT_VSPRINTF       /* needed for nand_util.c */
341 #endif
342
343 /* Ethernet */
344 #define CONFIG_MACB
345 #define CONFIG_RMII
346 #define CONFIG_NET_MULTI
347 #define CONFIG_NET_RETRY_COUNT          5
348
349 #define CONFIG_OVERWRITE_ETHADDR_ONCE
350
351 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
352
353 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
354 #define CONFIG_SYS_MEMTEST_END          0x21e00000
355
356 /* Address and size of Primary Environment Sector */
357 #ifdef CONFIG_ENV_IS_IN_FLASH
358 #define CONFIG_ENV_SIZE                 0x20000
359 #else
360 #define CONFIG_ENV_SIZE                 0x2000
361 #endif
362
363 #define CONFIG_BAUDRATE                 115200
364 #define CONFIG_SYS_BAUDRATE_TABLE       {312500, 230400, 115200, 19200, \
365                                                 38400, 57600, 9600 }
366
367 #define CONFIG_SYS_PROMPT       "U-Boot> "
368 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
369 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
370 #define CONFIG_SYS_PBSIZE       \
371         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
372 #define CONFIG_CMDLINE_EDITING
373 #define CONFIG_AUTO_COMPLETE
374
375 /*
376  * Size of malloc() pool
377  */
378 #define CONFIG_SYS_MALLOC_LEN           \
379         ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
380 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* 128 bytes for initial data */
381
382 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
383
384 #ifndef CONFIG_RAMLOAD
385 #define CONFIG_BOOTCOMMAND              "run nfsboot"
386 #endif
387 #define CONFIG_BOOT_RETRY_TIME          -1
388 #define CONFIG_BOOT_RETRY_MIN           15
389
390 #define CONFIG_NFSBOOTCOMMAND                                           \
391                 "dhcp $(copy_addr) $(kernelname);"                      \
392                 "run bootargsdefaults;"                                 \
393                 "set bootargs $(bootargs) boot=nfs "                    \
394                 ";echo $(bootargs)"                                     \
395         ";bootm"
396
397 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
398         "ubootaddr=10000000\0"                                          \
399         "splashimage=10080000\0"                                        \
400         "kerneladdr=100A0000\0"                                         \
401         "kernelsize=00800000\0"                                         \
402         "minifsaddr=108A0000\0"                                         \
403         "minifssize=00060000\0"                                         \
404         "rootfsaddr=10900000\0"                                         \
405         "copy_addr=20200000\0"                                          \
406         "rootfssize=01700000\0"                                         \
407         "kernelname=uImage_vl_ma2sc\0"                                  \
408         "bootargsdefaults=set bootargs "                                \
409                 "console=ttyS0,115200 "                                 \
410                 "video=atmel_lcdfb "                                    \
411                 "mem=62M "                                              \
412                 "panic=10 "                                             \
413                 "boardrevison=\\\"${revision}\\\" "                     \
414                 "uboot=\\\"${ver}\\\" "                                 \
415                 "\0"                                                    \
416         "update_all=run update_kernel;run update_root;"                 \
417                 "run update_splash; run update_uboot\0"                 \
418         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
419                 "dhcp $(copy_addr) $(kernelname);"                      \
420                 "erase $(kerneladdr) +$(kernelsize);"                   \
421                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
422                 "protect on $(kerneladdr) +$(kernelsize)"               \
423                 "\0"                                                    \
424         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
425                 "dhcp $(copy_addr) vl_ma2sc.root;"                      \
426                 "erase $(rootfsaddr) +$(rootfssize);"                   \
427                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
428                 "\0"                                                    \
429         "update_splash=protect off $(splashimage) +20000;"              \
430                 "dhcp $(copy_addr) splash_vl_ma2sc.bmp;"                \
431                 "erase $(splashimage) +20000;"                          \
432                 "cp.b $(fileaddr) 10080000 $(filesize);"                \
433                 "protect on $(splashimage) +20000\0"                    \
434         "update_uboot=protect off 10000000 1005FFFF;"                   \
435                 "dhcp $(copy_addr) u-boot_vl_ma2sc;"                    \
436                 "erase 10000000 1005FFFF;"                              \
437                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
438                 "protect on 10000000 1005FFFF;reset\0"                  \
439         "emergency=run bootargsdefaults;"                               \
440                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
441                 ";bootm $(kerneladdr)\0"                                \
442         "netemergency=run bootargsdefaults;"                            \
443                 "dhcp $(copy_addr) $(kernelname);"                      \
444                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
445                 ";bootm $(copy_addr)\0"                                 \
446         "norboot=run bootargsdefaults;"                                 \
447                 "set bootargs $(bootargs) root=initramfs boot=local quiet " \
448                 ";bootm $(kerneladdr)\0"                                \
449         "nandboot=run bootargsdefaults;"                                \
450                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
451                 ";bootm $(kerneladdr)\0"                                \
452         "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0"  \
453         "clearenv=protect off 10060000 1007FFFF;"                       \
454                 "erase 10060000 1007FFFF;reset\0"                       \
455         " "
456
457 /*--------------------------------------------------------------------------*/
458
459 #ifdef CONFIG_USE_IRQ
460 #error CONFIG_USE_IRQ not supported
461 #endif
462
463 #endif