include/configs/zipitz2.h

   1 /*
   2  * Aeronix Zipit Z2 configuration file
   3  *
   4  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 #define CONFIG_ZIPITZ2          1       /* Zipit Z2 board */
  17 #define CONFIG_SYS_TEXT_BASE    0x0
  18
  19 #undef  CONFIG_BOARD_LATE_INIT
  20 #undef  CONFIG_SKIP_LOWLEVEL_INIT
  21 #define CONFIG_PREBOOT
  22
  23 /*
  24  * Environment settings
  25  */
  26 #define CONFIG_ENV_OVERWRITE
  27 #define CONFIG_ENV_IS_IN_FLASH          1
  28 #define CONFIG_ENV_ADDR                 0x40000
  29 #define CONFIG_ENV_SIZE                 0x20000
  30
  31 /* we will never enable dcache, because we have to setup MMU first */
  32 #define CONFIG_SYS_DCACHE_OFF
  33
  34 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  35 #define CONFIG_ARCH_CPU_INIT
  36
  37 #define CONFIG_BOOTCOMMAND                                              \
  38         "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
  39         "then "                                                         \
  40                 "source 0xa0000000; "                                   \
  41         "else "                                                         \
  42                 "bootm 0x60000; "                                       \
  43         "fi; "
  44 #define CONFIG_BOOTARGS                                                 \
  45         "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
  46 #define CONFIG_TIMESTAMP
  47 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  48 #define CONFIG_CMDLINE_TAG
  49 #define CONFIG_SETUP_MEMORY_TAGS
  50 #define CONFIG_SYS_TEXT_BASE            0x0
  51 #define CONFIG_LZMA                     /* LZMA compression support */
  52
  53 /*
  54  * Serial Console Configuration
  55  * STUART - the lower serial port on Colibri board
  56  */
  57 #define CONFIG_PXA_SERIAL
  58 #define CONFIG_STUART                   1
  59 #define CONFIG_CONS_INDEX               2
  60 #define CONFIG_BAUDRATE                 115200
  61
  62 /*
  63  * Bootloader Components Configuration
  64  */
  65 #include <config_cmd_default.h>
  66
  67 #undef  CONFIG_CMD_NET
  68 #undef  CONFIG_CMD_NFS
  69 #define CONFIG_CMD_ENV
  70 #undef  CONFIG_CMD_IMLS
  71 #define CONFIG_CMD_MMC
  72 #define CONFIG_CMD_SPI
  73
  74 /*
  75  * MMC Card Configuration
  76  */
  77 #ifdef  CONFIG_CMD_MMC
  78 #define CONFIG_MMC
  79 #define CONFIG_GENERIC_MMC
  80 #define CONFIG_PXA_MMC_GENERIC
  81 #define CONFIG_SYS_MMC_BASE             0xF0000000
  82 #define CONFIG_CMD_FAT
  83 #define CONFIG_CMD_EXT2
  84 #define CONFIG_DOS_PARTITION
  85 #endif
  86
  87 /*
  88  * SPI and LCD
  89  */
  90 #ifdef  CONFIG_CMD_SPI
  91 #define CONFIG_SOFT_SPI
  92 #define CONFIG_LCD
  93 #define CONFIG_PXA_LCD
  94 #define CONFIG_LMS283GF05
  95 #define CONFIG_VIDEO_LOGO
  96 #define CONFIG_CMD_BMP
  97 #define CONFIG_SPLASH_SCREEN
  98 #define CONFIG_SPLASH_SCREEN_ALIGN
  99 #define CONFIG_VIDEO_BMP_GZIP
 100 #define CONFIG_VIDEO_BMP_RLE8
 101 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
 102
 103 #define SPI_DELAY       udelay(10)
 104 #define SPI_SDA(val)    zipitz2_spi_sda(val)
 105 #define SPI_SCL(val)    zipitz2_spi_scl(val)
 106 #define SPI_READ        zipitz2_spi_read()
 107 #ifndef __ASSEMBLY__
 108 void zipitz2_spi_sda(int);
 109 void zipitz2_spi_scl(int);
 110 unsigned char zipitz2_spi_read(void);
 111 #endif
 112 #endif
 113
 114 /*
 115  * KGDB
 116  */
 117 #ifdef  CONFIG_CMD_KGDB
 118 #define CONFIG_KGDB_BAUDRATE            230400          /* speed to run kgdb serial port */
 119 #endif
 120
 121 /*
 122  * HUSH Shell Configuration
 123  */
 124 #define CONFIG_SYS_HUSH_PARSER          1
 125
 126 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 127 #ifdef  CONFIG_SYS_HUSH_PARSER
 128 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 129 #endif
 130 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
 131 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 132 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 133 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 134 #define CONFIG_SYS_DEVICE_NULLDEV       1
 135
 136 /*
 137  * Clock Configuration
 138  */
 139 #undef  CONFIG_SYS_CLKS_IN_HZ
 140 #define CONFIG_SYS_CPUSPEED             0x190           /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
 141
 142 /*
 143  * SRAM Map
 144  */
 145 #define PHYS_SRAM                       0x5c000000      /* SRAM Bank #1 */
 146 #define PHYS_SRAM_SIZE                  0x00040000      /* 256k */
 147
 148 /*
 149  * DRAM Map
 150  */
 151 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 152 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 153 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
 154
 155 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 156 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
 157
 158 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 159 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 160
 161 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 162
 163 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 164 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
 165
 166 /*
 167  * NOR FLASH
 168  */
 169 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 170 #define PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
 171 #define PHYS_FLASH_SECT_SIZE            0x00010000      /* 64 KB sectors */
 172 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 173
 174 #define CONFIG_SYS_FLASH_CFI
 175 #define CONFIG_FLASH_CFI_DRIVER         1
 176 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 177
 178 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 179 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 180
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 182 #define CONFIG_SYS_MAX_FLASH_SECT       256
 183
 184 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 185
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     240000
 188 #define CONFIG_SYS_FLASH_LOCK_TOUT      240000
 189 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
 190 #define CONFIG_SYS_FLASH_PROTECTION
 191
 192 /*
 193  * GPIO settings
 194  */
 195 #define CONFIG_SYS_GAFR0_L_VAL  0x02000140
 196 #define CONFIG_SYS_GAFR0_U_VAL  0x59188000
 197 #define CONFIG_SYS_GAFR1_L_VAL  0x63900002
 198 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa03950
 199 #define CONFIG_SYS_GAFR2_L_VAL  0x0aaaaaaa
 200 #define CONFIG_SYS_GAFR2_U_VAL  0x29000308
 201 #define CONFIG_SYS_GAFR3_L_VAL  0x54000000
 202 #define CONFIG_SYS_GAFR3_U_VAL  0x000000d5
 203 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 204 #define CONFIG_SYS_GPCR1_VAL    0x00000020
 205 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 206 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 207 #define CONFIG_SYS_GPDR0_VAL    0xdafcee00
 208 #define CONFIG_SYS_GPDR1_VAL    0xffa3aaab
 209 #define CONFIG_SYS_GPDR2_VAL    0x8fe9ffff
 210 #define CONFIG_SYS_GPDR3_VAL    0x001b1f8a
 211 #define CONFIG_SYS_GPSR0_VAL    0x06080400
 212 #define CONFIG_SYS_GPSR1_VAL    0x007f0000
 213 #define CONFIG_SYS_GPSR2_VAL    0x032a0000
 214 #define CONFIG_SYS_GPSR3_VAL    0x00000180
 215
 216 #define CONFIG_SYS_PSSR_VAL     0x30
 217
 218 /*
 219  * Clock settings
 220  */
 221 #define CONFIG_SYS_CKEN         0x00511220
 222 #define CONFIG_SYS_CCCR         0x00000190
 223
 224 /*
 225  * Memory settings
 226  */
 227 #define CONFIG_SYS_MSC0_VAL     0x2ffc38f8
 228 #define CONFIG_SYS_MSC1_VAL     0x0000ccd1
 229 #define CONFIG_SYS_MSC2_VAL     0x0000b884
 230 #define CONFIG_SYS_MDCNFG_VAL   0x08000ba9
 231 #define CONFIG_SYS_MDREFR_VAL   0x2011a01e
 232 #define CONFIG_SYS_MDMRS_VAL    0x00000000
 233 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 234 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 235
 236 /*
 237  * PCMCIA and CF Interfaces
 238  */
 239 #define CONFIG_SYS_MECR_VAL     0x00000001
 240 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 241 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 242 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 243 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 244 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 245 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 246
 247 #endif  /* __CONFIG_H */