sf: Add S25FL128S_256K IDs

[karo-tx-uboot.git] / README

diff --git a/README b/README
index a4a450efeec89302e96ad10e4c3dfdae91a363fc..216f0c70aa9403534127dcd256627fa55e12f08e 100644 (file)
--- a/README
+++ b/README
@@ -141,7 +141,6 @@ Directory Hierarchy:
        /s3c24x0        Files specific to Samsung S3C24X0 CPUs
       /arm926ejs       Files specific to ARM 926 CPUs
       /arm1136         Files specific to ARM 1136 CPUs
        /s3c24x0        Files specific to Samsung S3C24X0 CPUs
       /arm926ejs       Files specific to ARM 926 CPUs
       /arm1136         Files specific to ARM 1136 CPUs

-      /ixp             Files specific to Intel XScale IXP CPUs

       /pxa             Files specific to Intel XScale PXA CPUs
       /sa1100          Files specific to Intel StrongARM SA1100 CPUs
     /lib               Architecture specific library files
       /pxa             Files specific to Intel XScale PXA CPUs
       /sa1100          Files specific to Intel StrongARM SA1100 CPUs
     /lib               Architecture specific library files


@@ -423,9 +422,10 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 

-               CONFIG_SYS_FSL_DDR_EMU
-               Specify emulator support for DDR. Some DDR features such as
-               deskew training are not available.
+               CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               Single Source Clock is clocking mode present in some of FSL SoC's.
+               In this mode, a single differential clock is used to supply
+               clocks to the sysclock, ddrclock and usbclock.

 
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN


@@ -433,6 +433,75 @@ The following options need to be configured:
                Defines the endianess of the CPU. Implementation of those
                values is arch specific.
 
                Defines the endianess of the CPU. Implementation of those
                values is arch specific.
 

+               CONFIG_SYS_FSL_DDR
+               Freescale DDR driver in use. This type of DDR controller is
+               found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+               SoCs.
+
+               CONFIG_SYS_FSL_DDR_ADDR
+               Freescale DDR memory-mapped register base.
+
+               CONFIG_SYS_FSL_DDR_EMU
+               Specify emulator support for DDR. Some DDR features such as
+               deskew training are not available.
+
+               CONFIG_SYS_FSL_DDRC_GEN1
+               Freescale DDR1 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN2
+               Freescale DDR2 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN3
+               Freescale DDR3 controller.
+
+               CONFIG_SYS_FSL_DDRC_ARM_GEN3
+               Freescale DDR3 controller for ARM-based SoCs.
+
+               CONFIG_SYS_FSL_DDR1
+               Board config to use DDR1. It can be enabled for SoCs with
+               Freescale DDR1 or DDR2 controllers, depending on the board
+               implemetation.
+
+               CONFIG_SYS_FSL_DDR2
+               Board config to use DDR2. It can be eanbeld for SoCs with
+               Freescale DDR2 or DDR3 controllers, depending on the board
+               implementation.
+
+               CONFIG_SYS_FSL_DDR3
+               Board config to use DDR3. It can be enabled for SoCs with
+               Freescale DDR3 controllers.
+
+               CONFIG_SYS_FSL_IFC_BE
+               Defines the IFC controller register space as Big Endian
+
+               CONFIG_SYS_FSL_IFC_LE
+               Defines the IFC controller register space as Little Endian
+
+               CONFIG_SYS_FSL_PBL_PBI
+               It enables addition of RCW (Power on reset configuration) in built image.
+               Please refer doc/README.pblimage for more details
+
+               CONFIG_SYS_FSL_PBL_RCW
+               It adds PBI(pre-boot instructions) commands in u-boot build image.
+               PBI commands can be used to configure SoC before it starts the execution.
+               Please refer doc/README.pblimage for more details
+
+               CONFIG_SYS_FSL_DDR_BE
+               Defines the DDR controller register space as Big Endian
+
+               CONFIG_SYS_FSL_DDR_LE
+               Defines the DDR controller register space as Little Endian
+
+               CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+               Physical address from the view of DDR controllers. It is the
+               same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+               it could be different for ARM SoCs.
+
+               CONFIG_SYS_FSL_DDR_INTLV_256B
+               DDR controller interleaving on 256-byte. This is a special
+               interleaving mode, handled by Dickens for Freescale layerscape
+               SoCs with ARM core.
+

 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 


@@ -784,6 +853,22 @@ The following options need to be configured:
                as a convenience, when switching between booting from
                RAM and NFS.
 
                as a convenience, when switching between booting from
                RAM and NFS.
 

+- Bootcount:
+               CONFIG_BOOTCOUNT_LIMIT
+               Implements a mechanism for detecting a repeating reboot
+               cycle, see:
+               http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
+
+               CONFIG_BOOTCOUNT_ENV
+               If no softreset save registers are found on the hardware
+               "bootcount" is stored in the environment. To prevent a
+               saveenv on all reboots, the environment variable
+               "upgrade_available" is used. If "upgrade_available" is
+               0, "bootcount" is always 0, if "upgrade_available" is
+               1 "bootcount" is incremented in the environment.
+               So the Userspace Applikation must set the "upgrade_available"
+               and "bootcount" variable to 0, if a boot was successfully.
+

 - Pre-Boot Commands:
                CONFIG_PREBOOT
 
 - Pre-Boot Commands:
                CONFIG_PREBOOT
 


@@ -832,6 +917,7 @@ The following options need to be configured:
                CONFIG_CMD_BSP          * Board specific commands
                CONFIG_CMD_BOOTD          bootd
                CONFIG_CMD_CACHE        * icache, dcache
                CONFIG_CMD_BSP          * Board specific commands
                CONFIG_CMD_BOOTD          bootd
                CONFIG_CMD_CACHE        * icache, dcache

+               CONFIG_CMD_CLK          * clock command support

                CONFIG_CMD_CONSOLE        coninfo
                CONFIG_CMD_CRC32        * crc32
                CONFIG_CMD_DATE         * support for RTC, date/time...
                CONFIG_CMD_CONSOLE        coninfo
                CONFIG_CMD_CRC32        * crc32
                CONFIG_CMD_DATE         * support for RTC, date/time...


@@ -852,10 +938,11 @@ The following options need to be configured:
                CONFIG_CMD_EXPORTENV    * export the environment
                CONFIG_CMD_EXT2         * ext2 command support
                CONFIG_CMD_EXT4         * ext4 command support
                CONFIG_CMD_EXPORTENV    * export the environment
                CONFIG_CMD_EXT2         * ext2 command support
                CONFIG_CMD_EXT4         * ext4 command support

+               CONFIG_CMD_FS_GENERIC   * filesystem commands (e.g. load, ls)
+                                         that work for multiple fs types

                CONFIG_CMD_SAVEENV        saveenv
                CONFIG_CMD_FDC          * Floppy Disk Support
                CONFIG_CMD_FAT          * FAT command support
                CONFIG_CMD_SAVEENV        saveenv
                CONFIG_CMD_FDC          * Floppy Disk Support
                CONFIG_CMD_FAT          * FAT command support

-               CONFIG_CMD_FDOS         * Dos diskette Support

                CONFIG_CMD_FLASH          flinfo, erase, protect
                CONFIG_CMD_FPGA           FPGA device initialization support
                CONFIG_CMD_FUSE         * Device fuse support
                CONFIG_CMD_FLASH          flinfo, erase, protect
                CONFIG_CMD_FPGA           FPGA device initialization support
                CONFIG_CMD_FUSE         * Device fuse support


@@ -1033,7 +1120,6 @@ The following options need to be configured:
 
 - GPIO Support:
                CONFIG_PCA953X          - use NXP's PCA953X series I2C GPIO
 
 - GPIO Support:
                CONFIG_PCA953X          - use NXP's PCA953X series I2C GPIO

-               CONFIG_PCA953X_INFO     - enable pca953x info command

 
                The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
                chip-ngpio pairs that tell the PCA953X driver the number of
 
                The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
                chip-ngpio pairs that tell the PCA953X driver the number of


@@ -1368,6 +1454,13 @@ The following options need to be configured:
                        for your device
                        - CONFIG_USBD_PRODUCTID 0xFFFF
 
                        for your device
                        - CONFIG_USBD_PRODUCTID 0xFFFF
 

+               Some USB device drivers may need to check USB cable attachment.
+               In this case you can enable following config in BoardName.h:
+                       CONFIG_USB_CABLE_CHECK
+                       This enables function definition:
+                       - usb_cable_connected() in include/usb.h
+                       Implementation of this function is board-specific.
+

 - ULPI Layer Support:
                The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
                the generic ULPI layer. The generic layer accesses the ULPI PHY
 - ULPI Layer Support:
                The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
                the generic ULPI layer. The generic layer accesses the ULPI PHY


@@ -1648,7 +1741,7 @@ CBFS (Coreboot Filesystem) support
 
                If this option is set, then U-Boot will prevent the environment
                variable "splashimage" from being set to a problematic address
 
                If this option is set, then U-Boot will prevent the environment
                variable "splashimage" from being set to a problematic address

-               (see README.displaying-bmps and README.arm-unaligned-accesses).
+               (see README.displaying-bmps).

                This option is useful for targets where, due to alignment
                restrictions, an improperly aligned BMP image will cause a data
                abort. If you think you will not have problems with unaligned
                This option is useful for targets where, due to alignment
                restrictions, an improperly aligned BMP image will cause a data
                abort. If you think you will not have problems with unaligned


@@ -1957,6 +2050,21 @@ CBFS (Coreboot Filesystem) support
                kernel). Defining CONFIG_STATUS_LED enables this
                feature in U-Boot.
 
                kernel). Defining CONFIG_STATUS_LED enables this
                feature in U-Boot.
 

+               Additional options:
+
+               CONFIG_GPIO_LED
+               The status LED can be connected to a GPIO pin.
+               In such cases, the gpio_led driver can be used as a
+               status LED backend implementation. Define CONFIG_GPIO_LED
+               to include the gpio_led driver in the U-Boot binary.
+
+               CONFIG_GPIO_LED_INVERTED_TABLE
+               Some GPIO connected LEDs may have inverted polarity in which
+               case the GPIO high value corresponds to LED off state and
+               GPIO low value corresponds to LED on state.
+               In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+               with a list of GPIO LEDs that have inverted polarity.
+

 - CAN Support: CONFIG_CAN_DRIVER
 
                Defining CONFIG_CAN_DRIVER enables CAN driver support
 - CAN Support: CONFIG_CAN_DRIVER
 
                Defining CONFIG_CAN_DRIVER enables CAN driver support


@@ -2034,6 +2142,48 @@ CBFS (Coreboot Filesystem) support
                  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
                  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 
                  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
                  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 

+               - drivers/i2c/sh_i2c.c:
+                 - activate this driver with CONFIG_SYS_I2C_SH
+                 - This driver adds from 2 to 5 i2c buses
+
+                 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+                 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+                 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+                 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+                 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+                 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+                 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+                 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+                 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+                 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+                 - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+                 - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+                 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+               - drivers/i2c/omap24xx_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+                 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+               - drivers/i2c/zynq_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_ZYNQ
+                 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+                 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
+               - drivers/i2c/s3c24x0_i2c.c:
+                 - activate this driver with CONFIG_SYS_I2C_S3C24X0
+                 - This driver adds i2c buses (11 for Exynos5250, Exynos5420
+                   9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
+                   with a fix speed from 100000 and the slave addr 0!
+

                additional defines:
 
                CONFIG_SYS_NUM_I2C_BUSES
                additional defines:
 
                CONFIG_SYS_NUM_I2C_BUSES


@@ -2638,6 +2788,12 @@ CBFS (Coreboot Filesystem) support
                Define this option to use the Bank addr/Extended addr
                support on SPI flashes which has size > 16Mbytes.
 
                Define this option to use the Bank addr/Extended addr
                support on SPI flashes which has size > 16Mbytes.
 

+               CONFIG_SF_DUAL_FLASH            Dual flash memories
+
+               Define this option to use dual flash support where two flash
+               memories can be connected with a given cs line.
+               currently Xilinx Zynq qspi support these type of connections.
+

 - SystemACE Support:
                CONFIG_SYSTEMACE
 
 - SystemACE Support:
                CONFIG_SYSTEMACE
 


@@ -2708,11 +2864,31 @@ CBFS (Coreboot Filesystem) support
                CONFIG_RSA
 
                This enables the RSA algorithm used for FIT image verification
                CONFIG_RSA
 
                This enables the RSA algorithm used for FIT image verification

-               in U-Boot. See doc/uImage/signature for more information.
+               in U-Boot. See doc/uImage.FIT/signature.txt for more information.

 
                The signing part is build into mkimage regardless of this
                option.
 
 
                The signing part is build into mkimage regardless of this
                option.
 

+- bootcount support:
+               CONFIG_BOOTCOUNT_LIMIT
+
+               This enables the bootcounter support, see:
+               http://www.denx.de/wiki/DULG/UBootBootCountLimit
+
+               CONFIG_AT91SAM9XE
+               enable special bootcounter support on at91sam9xe based boards.
+               CONFIG_BLACKFIN
+               enable special bootcounter support on blackfin based boards.
+               CONFIG_SOC_DA8XX
+               enable special bootcounter support on da850 based boards.
+               CONFIG_BOOTCOUNT_RAM
+               enable support for the bootcounter in RAM
+               CONFIG_BOOTCOUNT_I2C
+               enable support for the bootcounter on an i2c (like RTC) device.
+                       CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+                       CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
+                                                   the bootcounter.
+                       CONFIG_BOOTCOUNT_ALEN = address len

 
 - Show boot progress:
                CONFIG_SHOW_BOOT_PROGRESS
 
 - Show boot progress:
                CONFIG_SHOW_BOOT_PROGRESS


@@ -3140,7 +3316,7 @@ FIT uImage format:
 
                CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
                Set for the SPL on PPC mpc8xxx targets, support for
 
                CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
                Set for the SPL on PPC mpc8xxx targets, support for

-               arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+               drivers/ddr/fsl/libddr.o in SPL binary.

 
                CONFIG_SPL_COMMON_INIT_DDR
                Set for common ddr init with serial presence detect in
 
                CONFIG_SPL_COMMON_INIT_DDR
                Set for common ddr init with serial presence detect in


@@ -3154,6 +3330,9 @@ FIT uImage format:
                Defines the size and behavior of the NAND that SPL uses
                to read U-Boot
 
                Defines the size and behavior of the NAND that SPL uses
                to read U-Boot
 

+               CONFIG_SPL_NAND_BOOT
+               Add support NAND boot
+

                CONFIG_SYS_NAND_U_BOOT_OFFS
                Location in NAND to read U-Boot from
 
                CONFIG_SYS_NAND_U_BOOT_OFFS
                Location in NAND to read U-Boot from
 


@@ -3291,6 +3470,9 @@ typically in board_init_f() and board_init_r().
 Configuration Settings:
 -----------------------
 
 Configuration Settings:
 -----------------------
 

+- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
+               Optionally it can be defined to support 64-bit memory commands.
+

 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
                undefine this when you're short of memory.
 
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
                undefine this when you're short of memory.
 


@@ -3563,12 +3745,6 @@ Configuration Settings:
        its config.mk file). If you find problems enabling this option on
        your board please report the problem and send patches!
 
        its config.mk file). If you find problems enabling this option on
        your board please report the problem and send patches!
 

-- CONFIG_SYS_SYM_OFFSETS
-       This is set by architectures that use offsets for link symbols
-       instead of absolute values. So bss_start is obtained using an
-       offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
-       directly. You should not need to touch this setting.
-

 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
        This is set by OMAP boards for the max time that reset should
        be asserted. See doc/README.omap-reset-time for details on how
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
        This is set by OMAP boards for the max time that reset should
        be asserted. See doc/README.omap-reset-time for details on how


@@ -4297,6 +4473,9 @@ Low Level (hardware related) configuration options:
 
                NOTE : currently only supported on AM335x platforms.
 
 
                NOTE : currently only supported on AM335x platforms.
 

+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+               Enables the RTC32K OSC on AM33xx based plattforms
+

 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 


@@ -5136,6 +5315,15 @@ when your kernel is intended to use an initial ramdisk:
        Load Address: 0x00000000
        Entry Point:  0x00000000
 
        Load Address: 0x00000000
        Entry Point:  0x00000000
 

+The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
+option performs the converse operation of the mkimage's second form (the "-d"
+option). Given an image built by mkimage, the dumpimage extracts a "data file"
+from the image:
+
+       tools/dumpimage -i image -p position data_file
+         -i ==> extract from the 'image' a specific 'data_file', \
+          indexed by 'position'
+

 
 Installing a Linux Image:
 -------------------------
 
 Installing a Linux Image:
 -------------------------