spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3

[karo-tx-uboot.git] / README

diff --git a/README b/README
index a0646c36657b3b69b37a9a1816a27fcdb55d8d43..fe48ccd292ed0ca0d87e3a2dbf4cc04b636d75af 100644 (file)
--- a/README
+++ b/README
@@ -472,6 +472,21 @@ The following options need to be configured:
                Board config to use DDR3. It can be enabled for SoCs with
                Freescale DDR3 controllers.
 
+               CONFIG_SYS_FSL_IFC_BE
+               Defines the IFC controller register space as Big Endian
+
+               CONFIG_SYS_FSL_IFC_LE
+               Defines the IFC controller register space as Little Endian
+
+               CONFIG_SYS_FSL_PBL_PBI
+               It enables addition of RCW (Power on reset configuration) in built image.
+               Please refer doc/README.pblimage for more details
+
+               CONFIG_SYS_FSL_PBL_RCW
+               It adds PBI(pre-boot instructions) commands in u-boot build image.
+               PBI commands can be used to configure SoC before it starts the execution.
+               Please refer doc/README.pblimage for more details
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -887,6 +902,7 @@ The following options need to be configured:
                CONFIG_CMD_BSP          * Board specific commands
                CONFIG_CMD_BOOTD          bootd
                CONFIG_CMD_CACHE        * icache, dcache
+               CONFIG_CMD_CLK          * clock command support
                CONFIG_CMD_CONSOLE        coninfo
                CONFIG_CMD_CRC32        * crc32
                CONFIG_CMD_DATE         * support for RTC, date/time...
@@ -2756,6 +2772,12 @@ CBFS (Coreboot Filesystem) support
                Define this option to use the Bank addr/Extended addr
                support on SPI flashes which has size > 16Mbytes.
 
+               CONFIG_SF_DUAL_FLASH            Dual flash memories
+
+               Define this option to use dual flash support where two flash
+               memories can be connected with a given cs line.
+               currently Xilinx Zynq qspi support these type of connections.
+
 - SystemACE Support:
                CONFIG_SYSTEMACE