asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- if (bad_cache_range(start, stop))
+ if (!check_cache_range(start, stop))
return;
while (start < stop) {
void flush_dcache_range(unsigned long start, unsigned long stop)
{
- if (bad_cache_range(start, stop))
+ if (!check_cache_range(start, stop))
return;
while (start < stop) {
flush_dcache_range(start, start + size);
}
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+#endif