sunxi: add sun7i dram setup support

[karo-tx-uboot.git] / arch / arm / cpu / arm1136 / cpu.c

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index f2e30b51985f2e2f1272d7115434f52f65abd509..a7aed4b2b70a720654d0180207e6a903a3e1ed74 100644 (file)
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -8,23 +8,7 @@
  * (C) Copyright 2002
  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -70,10 +54,12 @@ int cleanup_before_linux (void)
 static void cache_flush(void)
 {
        unsigned long i = 0;
-
-       asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-       asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+       /* clean entire data cache */
+       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+       /* invalidate both caches and flush btb */
+       asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+       /* mem barrier to sync things */
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -84,16 +70,16 @@ static void cache_flush(void)
 
 void invalidate_dcache_all(void)
 {
-       asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+       asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
 }
 
 void flush_dcache_all(void)
 {
-       asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
-       asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
 {
        int ok = 1;
 
@@ -112,26 +98,26 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop)
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       if (bad_cache_range(start, stop))
+       if (!check_cache_range(start, stop))
                return;
 
        while (start < stop) {
-               asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+               asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }
 }
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-       if (bad_cache_range(start, stop))
+       if (!check_cache_range(start, stop))
                return;
 
        while (start < stop) {
-               asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+               asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }
 
-       asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)
@@ -139,16 +125,6 @@ void flush_cache(unsigned long start, unsigned long size)
        flush_dcache_range(start, start + size);
 }
 
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-       icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-       dcache_enable();
-#endif
-}
-
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -170,3 +146,15 @@ void flush_cache(unsigned long start, unsigned long size)
 {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+#endif