/*
* armboot - Startup Code for ARM720 CPU-core
*
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Z
üpke <azu@sysgo.de>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Z
üpke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
ldr pc, _irq
ldr pc, _fiq
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt: .word _software_interrupt
+_prefetch_abort: .word _prefetch_abort
+_data_abort: .word _data_abort
+_not_used: .word _not_used
+_irq: .word _irq
+_fiq: .word _fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
+#else
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
+#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
.globl _bss_end_ofs
_bss_end_ofs:
+ .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
-clbss_l:str r2, [r0] /* clear loop... */
+clbss_l:cmp r0, r1 /* clear loop... */
+ bhs clbss_e /* if reached end of bss, exit */
+ str r2, [r0]
add r0, r0, #4
- cmp r0, r1
- bne clbss_l
+ b clbss_l
+clbss_e:
bl coloured_LED_init
- bl red_LED_on
+ bl red_led_on
#endif
/*
*************************************************************************
*/
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-
-/* Interupt-Controller base addresses */
-INTMR1: .word 0x80000280 @ 32 bit size
-INTMR2: .word 0x80001280 @ 16 bit size
-INTMR3: .word 0x80002280 @ 8 bit size
-
-/* SYSCONs */
-SYSCON1: .word 0x80000100
-SYSCON2: .word 0x80001100
-SYSCON3: .word 0x80002200
-
-#define CLKCTL 0x6 /* mask */
-#define CLKCTL_18 0x0 /* 18.432 MHz */
-#define CLKCTL_36 0x2 /* 36.864 MHz */
-#define CLKCTL_49 0x4 /* 49.152 MHz */
-#define CLKCTL_73 0x6 /* 73.728 MHz */
-
-#elif defined(CONFIG_LPC2292)
+#if defined(CONFIG_LPC2292)
PLLCFG_ADR: .word PLLCFG
PLLFEED_ADR: .word PLLFEED
PLLCON_ADR: .word PLLCON
#endif
cpu_init_crit:
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-
- /*
- * mask all IRQs by clearing all bits in the INTMRs
- */
- mov r1, #0x00
- ldr r0, INTMR1
- str r1, [r0]
- ldr r0, INTMR2
- str r1, [r0]
- ldr r0, INTMR3
- str r1, [r0]
-
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15,0,r0,c1,c0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- mcr p15,0,r0,c1,c0
-#elif defined(CONFIG_NETARM)
+#if defined(CONFIG_NETARM)
/*
* prior to software reset : need to set pin PORTC4 to be *HRESET
*/
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
str r1, [r0]
+#elif defined(CONFIG_TEGRA)
+ /* No cpu_init_crit for tegra as yet */
#else
#error No cpu_init_crit() defined for current CPU type
#endif
str r1, [r0]
#endif
-#ifndef CONFIG_LPC2292
+#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
mov ip, lr
/*
* before relocating, we have to setup RAM timing
mov pc, lr
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
bl do_fiq
#endif
+#endif /* CONFIG_SPL_BUILD */
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
- .align 5
-.globl reset_cpu
-reset_cpu:
- mov ip, #0
- mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
- mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
- mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
- bic ip, ip, #0x000f @ ............wcam
- bic ip, ip, #0x2100 @ ..v....s........
- mcr p15, 0, ip, c1, c0, 0 @ ctrl register
- mov pc, r0
-#elif defined(CONFIG_NETARM)
+#if defined(CONFIG_NETARM)
.align 5
.globl reset_cpu
reset_cpu:
.globl reset_cpu
reset_cpu:
mov pc, r0
+#elif defined(CONFIG_TEGRA)
+ /* No specific reset actions for tegra as yet */
#else
#error No reset_cpu() defined for current CPU type
#endif
projects / karo-tx-uboot.git / blobdiff