sunxi: add sun7i dram setup support

[karo-tx-uboot.git] / arch / arm / cpu / arm920t / at91 / clock.c

diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c
index 09d2799831a2511293c984b21413f4c478918232..2813bf7821613d6bc06fe5058faaa9a7c3225b49 100644 (file)
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ b/arch/arm/cpu/arm920t/at91/clock.c
@@ -6,10 +6,7 @@
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
@@ -29,11 +26,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
        case AT91_PMC_MCKR_CSS_SLOW:
                return CONFIG_SYS_AT91_SLOW_CLOCK;
        case AT91_PMC_MCKR_CSS_MAIN:
-               return gd->main_clk_rate_hz;
+               return gd->arch.main_clk_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLA:
-               return gd->plla_rate_hz;
+               return gd->arch.plla_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLB:
-               return gd->pllb_rate_hz;
+               return gd->arch.pllb_rate_hz;
        }
 
        return 0;
@@ -124,10 +121,10 @@ int at91_clock_init(unsigned long main_clock)
                main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
        }
 #endif
-       gd->main_clk_rate_hz = main_clock;
+       gd->arch.main_clk_rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
        /*
@@ -136,9 +133,10 @@ int at91_clock_init(unsigned long main_clock)
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
         */
-       gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+       gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
                             AT91_PMC_PLLBR_USBDIV_2;
-       gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+       gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+                                             gd->arch.at91_pllb_usb_init);
 #endif
 
        /*
@@ -146,13 +144,14 @@ int at91_clock_init(unsigned long main_clock)
         * For now, assume this parentage won't change.
         */
        mckr = readl(&pmc->mckr);
-       gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-       freq = gd->mck_rate_hz;
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
 
        freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
        /* mdiv */
-       gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-       gd->cpu_clk_rate_hz = freq;
+       gd->arch.mck_rate_hz = freq /
+                       (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+       gd->arch.cpu_clk_rate_hz = freq;
 
        return 0;
 }