writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
- gd->tbu = gd->tbl = 0;
+ gd->arch.tbu = gd->arch.tbl = 0;
return 0;
}
ulong now = readl(&pit->piir);
/* increment tbu if tbl has rolled over */
- if (now < gd->tbl)
- gd->tbu++;
- gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
void __udelay(unsigned long usec)