*/
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
+ udelay(100);
/*
* TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
- early_delay(1);
+ udelay(1);
if (timeout-- < 0)
break;
}
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
- early_delay(500000);
+ udelay(500000);
volt = mxs_get_batt_volt();
{
debug("SPL: Pre-Configuring power block\n");
- debug("SPL: Pre-Configuring power block\n");
-
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
if (!fixed_batt_supply) {
/* 5V to battery handoff ... FIXME */
setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
+ udelay(30);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
}
{
debug("SPL: Configuring common 4P2 regulator params\n");
- debug("SPL: Configuring common 4P2 regulator params\n");
-
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
if (xfer) {
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
- early_delay(20);
+ udelay(20);
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
POWER_DCDC4P2_ENABLE_DCDC);
}
- early_delay(25);
+ udelay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
- early_delay(100);
+ udelay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
- early_delay(100);
+ udelay(100);
}
}
}
{
debug("SPL: Switching DC-DC converters to 4P2\n");
- debug("SPL: Switching DC-DC converters to 4P2\n");
-
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
debug("SPL: Already switched - aborting\n");
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
- early_delay(20);
+ udelay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
- early_delay(20);
+ udelay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
{
debug("SPL: Booting from 5V supply\n");
- debug("SPL: Booting from 5V supply\n");
-
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
{
debug("SPL: Configuring power block to boot from battery\n");
- debug("SPL: Configuring power block to boot from battery\n");
-
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
/* 5V to battery handoff. */
setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
+ udelay(30);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
{
debug("SPL: Configuring power block to boot from 5V input\n");
- debug("SPL: Configuring power block to boot from 5V input\n");
-
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
return;
}
- early_delay(1000);
+ udelay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
{
debug("SPL: Initialising battery brown-out level to 3.0V\n");
- debug("SPL: Initialising battery brown-out level to 3.0V\n");
-
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
{
debug("SPL: Switching VDDD to DC-DC converters\n");
- debug("SPL: Switching VDDD to DC-DC converters\n");
-
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
{
debug("SPL: Enabling output rail protection\n");
- debug("SPL: Enabling output rail protection\n");
-
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO)) {
- early_delay(500);
+ udelay(500);
} else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK)) {
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
- early_delay(10);
+ udelay(10);
}
/**
{
debug("SPL: Initialising Power Block\n");
- debug("SPL: Initialising Power Block\n");
-
mxs_ungate_power();
mxs_power_clock2xtal();