- setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
- CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
- setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
- CLKCTRL_CLKSEQ_BYPASS_CPU);
+ debug("SPL: Switching CPU core clock source to PLL\n");
+
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+ /*
+ * The PLL is documented to lock within 10 µs from setting
+ * the POWER bit.
+ */
+ udelay(15);
+
+ /*
+ * TODO: Should the PLL0 FORCE_LOCK bit be set here followed by a
+ * wait on the PLL0 LOCK bit?
+ */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);