+struct mxs_vddx_cfg {
+ uint32_t *reg;
+ uint8_t step_mV;
+ uint16_t lowest_mV;
+ uint16_t highest_mV;
+ int (*powered_by_linreg)(void);
+ uint32_t trg_mask;
+ uint32_t bo_irq;
+ uint32_t bo_enirq;
+ uint32_t bo_offset_mask;
+ uint32_t bo_offset_offset;
+ uint16_t bo_min_mV;
+ uint16_t bo_max_mV;
+};
+
+#define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+ .reg = POWER_REG(hw_power_vddioctrl),
+#if defined(CONFIG_SOC_MX23)
+ .step_mV = 25,
+#else
+ .step_mV = 50,
+#endif
+ .lowest_mV = 2800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vddio_power_source_off,
+ .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
+ .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 2700,
+ .bo_max_mV = 3475,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+ .reg = POWER_REG(hw_power_vdddctrl),
+ .step_mV = 25,
+ .lowest_mV = 800,
+ .highest_mV = 1575,
+ .powered_by_linreg = mxs_get_vddd_power_source_off,
+ .trg_mask = POWER_VDDDCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
+ .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 800,
+ .bo_max_mV = 1475,
+};
+
+static const struct mxs_vddx_cfg mxs_vdda_cfg = {
+ .reg = POWER_REG(hw_power_vddactrl),
+ .step_mV = 25,
+ .lowest_mV = 1800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vdda_power_source_off,
+ .trg_mask = POWER_VDDACTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
+ .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 1400,
+ .bo_max_mV = 2175,
+};
+
+#ifdef CONFIG_SOC_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+ .reg = POWER_REG(hw_power_vddmemctrl),
+ .step_mV = 50,
+ .lowest_mV = 1500,
+ .highest_mV = 1700,
+ .powered_by_linreg = NULL,
+ .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
+ .bo_irq = 0,
+ .bo_enirq = 0,
+ .bo_offset_mask = 0,
+ .bo_offset_offset = 0,
+};
+#endif