am335x: fix GPMC config for NAND and NOR SPL boot

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / mem.c

diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b6eb46678fafe1cca053beb95d4fd8209e994cf7..56c9e7dbceb306fb22fec21454c3fff550f5252b 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -22,17 +22,6 @@
 
 struct gpmc *gpmc_cfg;
 
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       M_NAND_GPMC_CONFIG1,
-       M_NAND_GPMC_CONFIG2,
-       M_NAND_GPMC_CONFIG3,
-       M_NAND_GPMC_CONFIG4,
-       M_NAND_GPMC_CONFIG5,
-       M_NAND_GPMC_CONFIG6, 0
-};
-#endif
-
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size)
@@ -61,11 +50,34 @@ void gpmc_init(void)
 {
        /* putting a blanket check on GPMC based on ZeBu for now */
        gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-#ifdef CONFIG_CMD_NAND
-       const u32 *gpmc_config = NULL;
-       u32 base = 0;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+       const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
+                                               STNOR_GPMC_CONFIG2,
+                                               STNOR_GPMC_CONFIG3,
+                                               STNOR_GPMC_CONFIG4,
+                                               STNOR_GPMC_CONFIG5,
+                                               STNOR_GPMC_CONFIG6,
+                                               STNOR_GPMC_CONFIG7
+                                               };
+       u32 size = GPMC_SIZE_16M;
+       u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+       const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
+                                               M_NAND_GPMC_CONFIG2,
+                                               M_NAND_GPMC_CONFIG3,
+                                               M_NAND_GPMC_CONFIG4,
+                                               M_NAND_GPMC_CONFIG5,
+                                               M_NAND_GPMC_CONFIG6,
+                                               0
+                                               };
+       u32 size = GPMC_SIZE_256M;
+       u32 base = CONFIG_SYS_NAND_BASE;
+#else
+       const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
        u32 size = 0;
+       u32 base = 0;
 #endif
        /* global settings */
        writel(0x00000008, &gpmc_cfg->sysconfig);
@@ -81,12 +93,6 @@ void gpmc_init(void)
         */
        writel(0, &gpmc_cfg->cs[0].config7);
        sdelay(1000);
-
-#ifdef CONFIG_CMD_NAND
-       gpmc_config = gpmc_m_nand;
-
-       base = PISMO1_NAND_BASE;
-       size = PISMO1_NAND_SIZE;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
+       /* enable chip-select specific configurations */
+       enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }