*
* Copyright (C) 2012 Samsung Electronics
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
#include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+#define FSYS1_MMC0_DIV_MASK 0xff0f
+#define FSYS1_MMC0_DIV_VAL 0x0701
DECLARE_GLOBAL_DATA_PTR;
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGx_CHIP_COL_10 |
- DMC_MEMCONFIGx_CHIP_ROW_15 |
- DMC_MEMCONFIGx_CHIP_BANK_8,
+ .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
.prechconfig_tp_cnt = 0xff,
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGx_CHIP_COL_10 |
- DMC_MEMCONFIGx_CHIP_ROW_15 |
- DMC_MEMCONFIGx_CHIP_BANK_8,
+ .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
.prechconfig_tp_cnt = 0xff,
* @param frequency_mhz Returns memory speed in MHz
* @param arm_freq Returns ARM clock speed in MHz
* @param mem_manuf Return Memory Manufacturer name
- * @return 0 if all ok
*/
-static int clock_get_mem_selection(enum ddr_mode *mem_type,
+static void clock_get_mem_selection(enum ddr_mode *mem_type,
unsigned *frequency_mhz, unsigned *arm_freq,
enum mem_manuf *mem_manuf)
{
*frequency_mhz = params->frequency_mhz;
*arm_freq = params->arm_freq_mhz;
*mem_manuf = params->mem_manuf;
-
- return 0;
}
/* Get the ratios for setting ARM clock */
unsigned frequency_mhz, arm_freq;
int i;
- if (clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf))
- ;
+ clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf);
+
for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
i++, arm_ratio++) {
if (arm_ratio->arm_freq_mhz == arm_freq)
unsigned frequency_mhz, arm_freq;
int i;
- if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf)) {
- for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
- i++, mem++) {
- if (mem->mem_type == mem_type &&
- mem->frequency_mhz == frequency_mhz &&
- mem->mem_manuf == mem_manuf)
- return mem;
- }
+ clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf);
+ for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+ i++, mem++) {
+ if (mem->mem_type == mem_type &&
+ mem->frequency_mhz == frequency_mhz &&
+ mem->mem_manuf == mem_manuf)
+ return mem;
}
/* will hang if failed to find memory timings */
void system_clock_init()
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
struct mem_timings *mem;
struct arm_clk_ratios *arm_clk_ratio;
u32 val, tmp;
val = readl(&clk->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
- clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
- while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+ while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
;
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
- while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+ while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
- while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+ while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
- while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+ while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0);
- while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+ while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
- while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+ while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
- while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+ while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
void clock_init_dp_clock(void)
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
/* DP clock enable */
setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
/* We run DP at 267 Mhz */
setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
}
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div_mmc;
+
+ div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+ div_mmc |= FSYS1_MMC0_DIV_VAL;
+ writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
projects / karo-tx-uboot.git / blobdiff