Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / exynos / dmc_init_ddr3.c

diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
similarity index 83%
rename from board/samsung/smdk5250/dmc_init_ddr3.c
rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e05079028a5b0a57a1db13404dd7ab17542f91e4..5f5914ede8cf654626cbfb049b61defbdeafc240 100644 (file)
--- a/board/samsung/smdk5250/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -3,23 +3,7 @@
  *
  * Copyright (C) 2012 Samsung Electronics
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
@@ -27,31 +11,36 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT 10000
 
 static void reset_phy_ctrl(void)
 {
-       struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
 
        writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
        writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+                      int reset)
 {
        unsigned int val;
        struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
        struct exynos5_dmc *dmc;
        int i;
 
-       phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
-       phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
-       dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+       phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+       phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+                                                       + DMC_OFFSET);
+       dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
 
-       reset_phy_ctrl();
+       if (reset)
+               reset_phy_ctrl();
 
        /* Set Impedance Output Driver */
        val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
@@ -100,14 +89,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
        /* Start DLL locking */
        writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-               &phy0_ctrl->phy_con12);
+              &phy0_ctrl->phy_con12);
        writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-               &phy1_ctrl->phy_con12);
+              &phy1_ctrl->phy_con12);
 
        update_reset_dll(dmc, DDR_MODE_DDR3);
 
        writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-               &dmc->concontrol);
+              &dmc->concontrol);
 
        /* Memory Channel Inteleaving Size */
        writel(mem->iv_size, &dmc->ivcontrol);
@@ -119,7 +108,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
        /* Precharge Configuration */
        writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-               &dmc->prechconfig);
+              &dmc->prechconfig);
 
        /* Power Down mode Configuration */
        writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |