karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / clock.c

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index db8f752218d443d20c9460bd527604094e7ff8af..443fb997826244080a4dd3d4ce7a1a979ee1e802 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -46,6 +46,8 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
 #define EMI_DIV_MAX     8
 #define NFC_DIV_MAX     8
 
+#define MXC_IPG_PER_CLK        MXC_IPG_PERCLK
+
 struct fixed_pll_mfd {
        u32 ref_clk_hz;
        u32 mfd;
@@ -172,7 +174,7 @@ void set_usboh3_clk(void)
                        MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
-void enable_usboh3_clk(unsigned char enable)
+void enable_usboh3_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -275,7 +277,7 @@ void ldb_clk_disable(int ldb)
 }
 #endif
 
-#ifdef CONFIG_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
@@ -303,7 +305,7 @@ void set_usb_phy_clk(void)
 }
 
 #if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -312,12 +314,12 @@ void enable_usb_phy1_clk(unsigned char enable)
                        MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
        /* i.MX51 has a single USB PHY clock, so do nothing here. */
 }
 #elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -326,7 +328,7 @@ void enable_usb_phy1_clk(unsigned char enable)
                        MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -626,6 +628,17 @@ static u32 get_emi_slow_clk(void)
        return  get_periph_clk() / (pdf + 1);
 }
 
+static u32 get_nfc_clk(void)
+{
+       u32 parent_rate = get_emi_slow_clk();
+       u32 div = readl(&mxc_ccm->cbcdr);
+
+       div &= MXC_CCM_CBCDR_NFC_PODF_MASK;
+       div >>= MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+       div++;
+       return parent_rate / div;
+}
+
 static u32 get_ddr_clk(void)
 {
        u32 ret_val = 0;
@@ -695,6 +708,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_ahb_clk();
        case MXC_DDR_CLK:
                return get_ddr_clk();
+       case MXC_AXI_A_CLK:
+               return get_axi_a_clk();
+       case MXC_AXI_B_CLK:
+               return get_axi_b_clk();
+       case MXC_EMI_SLOW_CLK:
+               return get_emi_slow_clk();
+       case MXC_NFC_CLK:
+               return get_nfc_clk();
        default:
                break;
        }
@@ -960,6 +981,18 @@ void enable_nfc_clk(unsigned char enable)
                MXC_CCM_CCGR5_EMI_ENFC(cg));
 }
 
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+       if (enable)
+               setbits_le32(&mxc_ccm->cgpr,
+                            MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+       else
+               clrbits_le32(&mxc_ccm->cgpr,
+                            MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
@@ -1140,9 +1173,13 @@ static int do_mx5_showclocks(void)
 
        printf("\n");
        pr_clk(AHB);
+       pr_clk(AXI_A);
+       pr_clk(AXI_B);
        pr_clk(IPG);
-       pr_clk(IPG);
+       pr_clk(IPG_PER);
        pr_clk(DDR);
+       pr_clk(EMI_SLOW);
+       pr_clk(NFC);
 #ifdef CONFIG_MXC_SPI
        pr_clk(CSPI);
 #endif