imx-common/cmd_bmode.c: add imx bmode (bootmode) command

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / soc.c

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 98203ba514c19f2230171559983b3c17b5b16a0d..263658aa4be46857f2b00abc0a97a18fbce5a2c2 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -30,6 +30,7 @@
 
 #include <asm/errno.h>
 #include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
 
 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
 #error "CPU_TYPE not defined"
@@ -123,3 +124,33 @@ void set_chipselect_size(int const cs_size)
 
        writel(reg, &iomuxc_regs->gpr1);
 }
+
+#ifdef CONFIG_MX53
+void boot_mode_apply(unsigned cfg_val)
+{
+       writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ *
+ * If bit 28 of LPGR is set upon watchdog reset,
+ * bits[25:0] of LPGR will move to SBMR.
+ */
+const struct boot_mode soc_boot_modes[] = {
+       {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+       /* usb or serial download */
+       {"usb",         MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
+       {"sata",        MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
+       {"escpi1:0",    MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
+       {"escpi1:1",    MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
+       {"escpi1:2",    MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
+       {"escpi1:3",    MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
+       /* 4 bit bus width */
+       {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+       {"esdhc2",      MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+       {"esdhc3",      MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
+       {"esdhc4",      MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+       {NULL,          0},
+};
+#endif