Merge branch 'master' of git://git.denx.de/u-boot-usb

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / soc.c

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 7c7a565665f5c644ee3a2421731a08f526e1b671..3753c14df3977c7b70459d5db2e3df0a05791f95 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -4,46 +4,32 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
 #include <asm/errno.h>
 #include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
 
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-#if defined(CONFIG_MX51)
-#define CPU_TYPE 0x51000
-#else
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
 #error "CPU_TYPE not defined"
 #endif
 
 u32 get_cpu_rev(void)
 {
-       int system_rev = CPU_TYPE;
+#ifdef CONFIG_MX51
+       int system_rev = 0x51000;
+#else
+       int system_rev = 0x53000;
+#endif
        int reg = __raw_readl(ROM_SI_REV);
 
+#if defined(CONFIG_MX51)
        switch (reg) {
        case 0x02:
                system_rev |= CHIP_REV_1_1;
@@ -57,64 +43,74 @@ u32 get_cpu_rev(void)
        case 0x20:
                system_rev |= CHIP_REV_3_0;
                break;
-       return system_rev;
        default:
                system_rev |= CHIP_REV_1_0;
                break;
        }
+#else
+       if (reg < 0x20)
+               system_rev |= CHIP_REV_1_0;
+       else
+               system_rev |= reg;
+#endif
        return system_rev;
 }
 
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
 {
-       u32 cpurev;
-
-       cpurev = get_cpu_rev();
-       printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-               (cpurev & 0xFF000) >> 12,
-               (cpurev & 0x000F0) >> 4,
-               (cpurev & 0x0000F) >> 0,
-               mxc_get_clock(MXC_ARM_CLK) / 1000000);
-       return 0;
+       return get_cpu_rev();
 }
 #endif
 
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-#if defined(CONFIG_FEC_MXC)
-extern int fecmxc_initialize(bd_t *bis);
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
 #endif
 
-int cpu_eth_init(bd_t *bis)
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-       int rc = -ENODEV;
+       int i;
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       struct fuse_bank *bank = &iim->bank[1];
+       struct fuse_bank1_regs *fuse =
+                       (struct fuse_bank1_regs *)bank->fuse_regs;
 
-#if defined(CONFIG_FEC_MXC)
-       rc = fecmxc_initialize(bis);
+       for (i = 0; i < 6; i++)
+               mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
 #endif
 
-       return rc;
+#ifdef CONFIG_MX53
+void boot_mode_apply(unsigned cfg_val)
+{
+       writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
 }
-
 /*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
+ * cfg_val will be used for
+ * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ *
+ * If bit 28 of LPGR is set upon watchdog reset,
+ * bits[25:0] of LPGR will move to SBMR.
  */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_FSL_ESDHC
-       return fsl_esdhc_mmc_init(bis);
-#else
-       return 0;
+const struct boot_mode soc_boot_modes[] = {
+       {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+       /* usb or serial download */
+       {"usb",         MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
+       {"sata",        MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
+       {"escpi1:0",    MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
+       {"escpi1:1",    MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
+       {"escpi1:2",    MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
+       {"escpi1:3",    MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
+       /* 4 bit bus width */
+       {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+       {"esdhc2",      MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+       {"esdhc3",      MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
+       {"esdhc4",      MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+       {NULL,          0},
+};
 #endif
-}
-
-
-void reset_cpu(ulong addr)
-{
-       __raw_writew(4, WDOG1_BASE_ADDR);
-}