arm: mx6: fix cpu_rev calculation

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 6f74175c57c008b877aa83d303035601b30885f3..1db85a1d8a43c21941fb55f22d2e93be5e7bf261 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -116,6 +116,20 @@ u32 get_cpu_rev(void)
                        type = MXC_CPU_MX6DP;
        }
        reg &= 0xff;            /* mx6 silicon revision */
+       if (type == MXC_CPU_MX6Q) {
+               switch (reg) {
+               case 0x02:
+                       break;
+               case 0x05:
+                       reg = 0x03;
+                       break;
+               case 0x06:
+                       reg = 0x06;
+                       break;
+               default:
+                       printf("Unknown CPU Rev.: 0x%02x\n", reg);
+               }
+       }
        return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
@@ -152,7 +166,7 @@ u32 get_cpu_speed_grade_hz(void)
        case OCOTP_CFG3_SPEED_850MHZ:
                if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
                        return 852000000;
-       /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+       /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6ULL */
        case OCOTP_CFG3_SPEED_800MHZ:
                return 792000000;
        }
@@ -214,13 +228,12 @@ u32 __weak get_board_rev(void)
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
        struct aipstz_regs *aips3;
 #endif
-
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
        aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
 #endif
 
@@ -249,7 +262,7 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
         * not forced to user-mode.
@@ -404,7 +417,8 @@ static void imx_set_wdog_powerdown(bool enable)
        struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
        struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+           is_cpu_type(MXC_CPU_MX6ULL))
                writew(enable, &wdog3->wmcr);
 
        /* Write to the PDE (Power Down Enable) bit */
@@ -555,7 +569,7 @@ void enable_caches(void)
 #endif
 
 #if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
        unsigned int mac0, mac1;
 
@@ -628,7 +642,8 @@ void s_init(void)
        u32 mask528;
        u32 reg, periph1, periph2;
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+           is_cpu_type(MXC_CPU_MX6ULL))
                return;
 
        /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs