#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
-#define VDDPU_MASK (0x1f << 9)
-
enum ldo_reg {
LDO_ARM,
LDO_SOC,
writew(enable, &wdog2->wmcr);
}
-static void imx_set_vddpu_power_down(void)
+static void set_ahb_rate(u32 val)
{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
-
- u32 reg;
-
- /*
- * Disable the brown out detection since we are going to be
- * disabling the LDO.
- */
- reg = readl(&anatop->ana_misc2);
- reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
- writel(reg, &anatop->ana_misc2);
-
- /* need to power down xPU in GPC before turning off PU LDO */
- reg = readl(&gpc->gpu_ctrl);
- writel(reg | 0x1, &gpc->gpu_ctrl);
-
- reg = readl(&gpc->ctrl);
- writel(reg | 0x1, &gpc->ctrl);
- while (readl(&gpc->ctrl) & 0x1)
- ;
-
- /* Mask the ANATOP brown out interrupt in the GPC. */
- reg = readl(&gpc->imr4);
- reg |= 0x80000000;
- writel(reg, &gpc->imr4);
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, div;
- /* disable VDDPU */
- writel(VDDPU_MASK, &anatop->reg_core_clr);
+ div = get_periph_clk() / val - 1;
+ reg = readl(&mxc_ccm->cbcdr);
- /* Clear the BO interrupt in the ANATOP. */
- reg = readl(&anatop->ana_misc1);
- reg |= 0x80000000;
- writel(reg, &anatop->ana_misc1);
+ writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+ (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}
int arch_cpu_init(void)
{
init_aips();
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
- imx_set_vddpu_power_down();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */