imx6: ensure AHB clock is 132MHz in low freq boot mode

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d8ccf3a18aa6e9babc142986dc20192557fb58be..33a293941514ac243d9c9b81fb802296a1d766d7 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -124,7 +124,7 @@ static void clear_ldo_ramp(void)
 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       u32 val, reg = readl(&anatop->reg_core);
+       u32 val, step, old, reg = readl(&anatop->reg_core);
        u8 shift;
 
        if (mv < 725)
@@ -150,9 +150,20 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
                return -EINVAL;
        }
 
+       old = (reg & (0x1F << shift)) >> shift;
+       step = abs(val - old);
+       if (step == 0)
+               return 0;
+
        reg = (reg & ~(0x1F << shift)) | (val << shift);
        writel(reg, &anatop->reg_core);
 
+       /*
+        * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+        * step
+        */
+       udelay(3 * step);
+
        return 0;
 }
 
@@ -166,11 +177,29 @@ static void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog2->wmcr);
 }
 
+static void set_ahb_rate(u32 val)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg, div;
+
+       div = get_periph_clk() / val - 1;
+       reg = readl(&mxc_ccm->cbcdr);
+
+       writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+               (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
 int arch_cpu_init(void)
 {
        init_aips();
 
-       set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+       /*
+        * When low freq boot is enabled, ROM will not set AHB
+        * freq, so we need to ensure AHB freq is 132MHz in such
+        * scenario.
+        */
+       if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+               set_ahb_rate(132000000);
 
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
@@ -182,6 +211,13 @@ int arch_cpu_init(void)
        return 0;
 }
 
+int board_postclk_init(void)
+{
+       set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+
+       return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {